OpenCores
URL https://opencores.org/ocsvn/raptor64/raptor64/trunk

Subversion Repositories raptor64

[/] [raptor64/] [trunk/] [rtl/] [verilog/] [lib/] [rolx16.v] - Blame information for rev 3

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 3 robfinch
//=============================================================================
2
//      (C) 2006-2011  Robert Finch
3
//      All rights reserved.
4
//      robfinch@opencores.org
5
//
6
//      rolx16.v
7
//              Rotate or shift left by multiples of sixteen bits.
8
//
9
//
10
//
11
// This source file is free software: you can redistribute it and/or modify 
12
// it under the terms of the GNU Lesser General Public License as published 
13
// by the Free Software Foundation, either version 3 of the License, or     
14
// (at your option) any later version.                                      
15
//                                                                          
16
// This source file is distributed in the hope that it will be useful,      
17
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
18
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
19
// GNU General Public License for more details.                             
20
//                                                                          
21
// You should have received a copy of the GNU General Public License        
22
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
23
//                                                                          
24
//=============================================================================
25
//
26
// rol 0,16,32 or 48 bits
27
module rolx16(op, a, b, o);
28
parameter DBW = 32;
29
localparam DMSB = DBW-1;
30
input op;
31
input [DMSB:0] a;
32
input [1:0] b;
33
output [DMSB:0] o;
34
reg [DMSB:0] o;
35
 
36
wire [47:0] opx = {48{op}};
37
always @(b or a or opx) begin
38
        case (b)
39
        2'd0:   o <= a;
40
        2'd1:   o <= {a[DMSB-16:0],a[DMSB:DMSB-15]&opx[15:0]};
41
        2'd2:   o <= {a[DMSB-(32%DBW):0],a[DMSB:DMSB-(31%DBW)]&opx[31:0]};
42
        2'd3:   o <= {a[DMSB-(48%DBW):0],a[DMSB:DMSB-(47%DBW)]&opx[47:0]};
43
        endcase
44
end
45
 
46
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.