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[/] [raptor64/] [trunk/] [rtl/] [verilog/] [lib/] [rolx16.v] - Blame information for rev 26

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1 3 robfinch
//=============================================================================
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//      (C) 2006-2011  Robert Finch
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//      All rights reserved.
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//      robfinch@opencores.org
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//
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//      rolx16.v
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//              Rotate or shift left by multiples of sixteen bits.
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//
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//
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//
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// This source file is free software: you can redistribute it and/or modify 
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// it under the terms of the GNU Lesser General Public License as published 
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// by the Free Software Foundation, either version 3 of the License, or     
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// (at your option) any later version.                                      
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//                                                                          
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// This source file is distributed in the hope that it will be useful,      
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// but WITHOUT ANY WARRANTY; without even the implied warranty of           
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
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// GNU General Public License for more details.                             
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//                                                                          
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// You should have received a copy of the GNU General Public License        
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// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
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//                                                                          
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//=============================================================================
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//
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// rol 0,16,32 or 48 bits
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module rolx16(op, a, b, o);
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parameter DBW = 32;
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localparam DMSB = DBW-1;
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input op;
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input [DMSB:0] a;
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input [1:0] b;
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output [DMSB:0] o;
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reg [DMSB:0] o;
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wire [47:0] opx = {48{op}};
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always @(b or a or opx) begin
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        case (b)
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        2'd0:   o <= a;
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        2'd1:   o <= {a[DMSB-16:0],a[DMSB:DMSB-15]&opx[15:0]};
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        2'd2:   o <= {a[DMSB-(32%DBW):0],a[DMSB:DMSB-(31%DBW)]&opx[31:0]};
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        2'd3:   o <= {a[DMSB-(48%DBW):0],a[DMSB:DMSB-(47%DBW)]&opx[47:0]};
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        endcase
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end
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endmodule

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