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robfinch |
// ============================================================================
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// (C) 2012 Robert Finch
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// All Rights Reserved.
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// robfinch@<remove>@opencores.org
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//
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// syncRam512x32_1rw1r.v
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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// ============================================================================
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//
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`define SYNTHESIS
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`define VENDOR_XILINX
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`define SPARTAN3
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module syncRam512x32_1rw1r(
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input wrst,
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input wclk,
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input wce,
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input we,
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input [8:0] wadr,
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input [31:0] i,
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output [31:0] wo,
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input rrst,
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input rclk,
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input rce,
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input [8:0] radr,
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output [31:0] o
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);
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`ifdef SYNTHESIS
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`ifdef VENDOR_XILINX
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`ifdef SPARTAN3
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RAMB16_S36_S36 ram0(
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.CLKA(wclk), .ADDRA(wadr), .DIA(i), .DIPA({^i[31:24],^i[23:16],^i[15:8],^i[7:0]}), .DOA(wo), .ENA(wce), .WEA(we), .SSRA(wrst),
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.CLKB(rclk), .ADDRB(radr), .DIB(32'hFFFF_FFFF), .DIPB(4'b1111), .DOB(o), .ENB(rce), .WEB(1'b0), .SSRB(rrst) );
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`endif
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`ifdef SPARTAN2
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RAMB4_S4_S4 ram0(
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.CLKA(wclk), .ADDRA(wadr), .DIA(i[3:0]), .DOA(wo[3:0]), .ENA(wce), .WEA(we), .RSTA(wrst),
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.CLKB(rclk), .ADDRB(radr), .DIB(4'hF), .DOB(o[3:0]), .ENB(rce), .WEB(1'b0), .RSTB(rrst) );
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RAMB4_S4_S4 ram1(
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.CLKA(wclk), .ADDRA(wadr), .DIA(i[7:4]), .DOA(wo[7:4]), .ENA(wce), .WEA(we), .RSTA(wrst),
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.CLKB(rclk), .ADDRB(radr), .DIB(4'hF), .DOB(o[7:4]), .ENB(rce), .WEB(1'b0), .RSTB(rrst) );
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RAMB4_S4_S4 ram2(
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.CLKA(wclk), .ADDRA(wadr), .DIA(i[11:8]), .DOA(wo[11:8]), .ENA(wce), .WEA(we), .RSTA(wrst),
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.CLKB(rclk), .ADDRB(radr), .DIB(4'hF), .DOB(o[11:8]), .ENB(rce), .WEB(1'b0), .RSTB(rrst) );
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RAMB4_S4_S4 ram3(
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.CLKA(wclk), .ADDRA(wadr), .DIA(i[15:12]), .DOA(wo[15:12]), .ENA(wce), .WEA(we), .RSTA(wrst),
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.CLKB(rclk), .ADDRB(radr), .DIB(4'hF), .DOB(o[15:12]), .ENB(rce), .WEB(1'b0), .RSTB(rrst) );
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`endif
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`endif
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`ifdef VENDOR_ALTERA
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reg [31:0] mem [511:0];
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reg [8:0] rradr;
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reg [8:0] rwadr;
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reg rrrst;
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reg rwrst;
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// register read addresses
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always @(posedge rclk)
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if (rce) rradr <= radr;
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always @(posedge rclk)
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if (rce) rrrst <= rrst;
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assign o = rrrst ? 0 : mem[rradr];
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// write side
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always @(posedge wclk)
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if (wce) rwadr <= wadr;
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always @(posedge wclk)
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if (wce) rwrst <= wrst;
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always @(posedge wclk)
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if (wce) mem[wadr] <= i;
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assign wo = rwrst ? 0 : mem[rwadr];
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`endif
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`else
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reg [31:0] mem [511:0];
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reg [8:0] rradr;
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reg [8:0] rwadr;
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reg rrrst;
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reg rwrst;
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// register read addresses
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always @(posedge rclk)
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if (rce) rradr <= radr;
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always @(posedge rclk)
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if (rce) rrrst <= rrst;
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assign o = rrrst ? 0 : mem[rradr];
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// write side
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always @(posedge wclk)
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if (wce) rwadr <= wadr;
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always @(posedge wclk)
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if (wce) rwrst <= wrst;
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always @(posedge wclk)
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if (wce) mem[wadr] <= i;
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assign wo = rwrst ? 0 : mem[rwadr];
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`endif
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endmodule
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