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[/] [raptor64/] [trunk/] [rtl/] [verilog/] [memory/] [internal/] [syncRam512x64_1rw2r.v] - Blame information for rev 3

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1 3 robfinch 
// ============================================================================
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// (C) 2011 Robert Finch
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// All Rights Reserved.
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// robfinch@<remove>@sympatico.ca
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//
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//      syncRam512x64_1rw2r.v
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program.  If not, see <http://www.gnu.org/licenses/>.
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//
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// ============================================================================
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//
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module syncRam512x64_1rw2r(
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input wrst,
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input wclk,
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input wce,
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input we,
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input [8:0] wadr,
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input [63:0] i,
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output [63:0] wo,
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input rrsta,
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input rclka,
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input rcea,
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input [8:0] radra,
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output [63:0] roa,
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input rrstb,
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input rclkb,
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input rceb,
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input [8:0] radrb,
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output [63:0] rob
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);
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syncRam512x64_1rw1r u1
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(
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        .wrst(wrst),
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        .wclk(wclk),
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        .wce(wce),
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        .we(we),
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        .wadr(wadr),
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        .i(i[63:0]),
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        .wo(wo[63:0]),
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        .rrst(rrsta),
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        .rclk(rclka),
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        .rce(rcea),
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        .radr(radra),
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        .ro(roa[63:0])
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);
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syncRam512x64_1rw1r u2
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(
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        .wrst(wrst),
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        .wclk(wclk),
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        .wce(wce),
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        .we(we),
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        .wadr(wadr),
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        .i(i[63:0]),
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        .wo(),
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        .rrst(rrstb),
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        .rclk(rclkb),
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        .rce(rceb),
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        .radr(radrb),
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        .ro(rob[63:0])
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);
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endmodule

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