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jguarin200 |
library ieee;
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use ieee.std_logic_1164.all;
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--! Memory Compiler Library
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library lpm;
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use lpm.all;
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package arithpack is
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--! Estados para la maquina de estados.
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type macState is (LOAD_INSTRUCTION,FLUSH_ARITH_PIPELINE,EXECUTE_INSTRUCTION);
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--! Estados para el controlador de interrupciones.
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type iCtrlState is (WAITING_FOR_AN_EVENT,FIRING_INTERRUPTIONS,SUSPEND);
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--! Constante de reseteo
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constant rstMasterValue : std_logic :='0';
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--! Constantes periodicas.
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constant tclk : time := 20 ns;
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constant tclk_2 : time := tclk/2;
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constant tclk_4 : time := tclk/4;
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--! Contadores para la má:quina de estados.
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component customCounter
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generic (
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EOBFLAG : string ;
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ZEROFLAG : string ;
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BACKWARDS : string ;
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EQUALFLAG : string ;
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subwidth : integer;
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width : integer
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);
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port (
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clk,rst,go,set : in std_logic;
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setValue,cmpBlockValue : in std_Logic_vector(width-1 downto subwidth);
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zero_flag,eob_flag,eq_flag : out std_logic;
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count : out std_logic_vector(width-1 downto 0)
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);
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end component;
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--! LPM Memory Compiler.
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component scfifo
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generic (
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add_ram_output_register :string;
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almost_full_value :natural;
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allow_wrcycle_when_full :string;
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intended_device_family :string;
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lpm_hint :string;
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lpm_numwords :natural;
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lpm_showahead :string;
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lpm_type :string;
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lpm_width :natural;
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lpm_widthu :natural;
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overflow_checking :string;
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underflow_checking :string;
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use_eab :string
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);
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port(
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rdreq : in std_logic;
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aclr : in std_logic;
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empty : out std_logic;
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clock : in std_logic;
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q : out std_logic_vector(lpm_width-1 downto 0);
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wrreq : in std_logic;
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data : in std_logic_vector(lpm_width-1 downto 0);
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almost_full : out std_logic;
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full : out std_logic
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);
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end component;
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component altsyncram
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generic (
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address_aclr_b : string;
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address_reg_b : string;
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clock_enable_input_a : string;
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clock_enable_input_b : string;
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clock_enable_output_b : string;
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intended_device_family : string;
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lpm_type : string;
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numwords_a : natural;
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numwords_b : natural;
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operation_mode : string;
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outdata_aclr_b : string;
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outdata_reg_b : string;
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power_up_uninitialized : string;
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ram_block_type : string;
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rdcontrol_reg_b : string;
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read_during_write_mode_mixed_ports : string;
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widthad_a : natural;
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widthad_b : natural;
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width_a : natural;
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width_b : natural;
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width_byteena_a : natural
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);
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port (
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wren_a : in std_logic;
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clock0 : in std_logic;
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address_a : in std_logic_vector(8 downto 0);
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address_b : in std_logic_vector(8 downto 0);
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rden_b : in std_logic;
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q_b : out std_logic_vector(31 downto 0);
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data_a : in std_logic_vector(31 downto 0)
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);
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end component;
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--! Maquina de Estados.
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component sm
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generic (
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width : integer ;
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widthadmemblock : integer
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--!external_readable_widthad :
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);
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port (
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--! Señales normales de secuencia.
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clk,rst: in std_logic;
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--! Vector con las instrucción codficada
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instrQq:in std_logic_vector(31 downto 0);
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--! Señal de cola vacia.
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instrQ_empty:in std_logic;
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adda,addb:out std_logic_vector (8 downto 0);
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sync_chain_0,instrRdAckd:out std_logic;
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full_r: in std_logic; --! Indica que la cola de resultados no puede aceptar mas de 32 elementos.
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--! End Of Instruction Event
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eoi : out std_logic;
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--! DataPath Control uca code.
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dpc_uca : out std_logic_vector (2 downto 0);
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state : out macState
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);
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end component;
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--! Maquina de Interrupciones
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component im
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generic (
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num_events : integer ;
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cycles_to_wait : integer
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);
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port (
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clk,rst: in std_logic;
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rfull_events: in std_logic_vector(num_events-1 downto 0); --! full results queue events
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eoi_events: in std_logic_vector(num_events-1 downto 0); --! end of instruction related events
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eoi_int: out std_logic_vector(num_events-1 downto 0);--! end of instruction related interruptions
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rfull_int: out std_logic_vector(num_events-1downto 0); --! full results queue related interruptions
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state: out iCtrlState
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);
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end component;
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--! Bloque de memorias
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component memblock
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generic (
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width : integer;
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blocksize : integer;
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widthadmemblock : integer;
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external_writeable_blocks : integer;
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external_readable_blocks : integer;
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external_readable_widthad : integer;
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external_writeable_widthad : integer
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);
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port (
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clk,rst,dpfifo_rd,normfifo_rd,dpfifo_wr,normfifo_wr : in std_logic;
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instrfifo_rd : in std_logic;
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resultfifo_wr: in std_logic_vector(external_readable_blocks-1 downto 0);
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instrfifo_empty: out std_logic; ext_rd,ext_wr: in std_logic;
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ext_wr_add : in std_logic_vector(external_writeable_widthad+widthadmemblock-1 downto 0);
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ext_rd_add : in std_logic_vector(external_readable_widthad-1 downto 0);
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ext_d: in std_logic_vector(width-1 downto 0);
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int_d : in std_logic_vector(external_readable_blocks*width-1 downto 0);
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resultfifo_full : out std_logic_vector(3 downto 0);
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ext_q,instrfifo_q : out std_logic_vector(width-1 downto 0);
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int_q : out std_logic_vector(external_writeable_blocks*width-1 downto 0);
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int_rd_add : in std_logic_vector(2*widthadmemblock-1 downto 0);
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dpfifo_d : in std_logic_vector(width*2-1 downto 0);
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normfifo_d : in std_logic_vector(width*3-1 downto 0);
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dpfifo_q : out std_logic_vector(width*2-1 downto 0);
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normfifo_q : out std_logic_vector(width*3-1 downto 0)
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);
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end component;
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--! Bloque decodificacion DataPath Control.
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component dpc
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generic (
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width : integer
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);
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port (
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clk,rst : in std_logic;
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paraminput : in std_logic_vector ((12*width)-1 downto 0); --! Vectores A,B,C,D
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prd32blko : in std_logic_vector ((06*width)-1 downto 0); --! Salidas de los 6 multiplicadores.
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add32blko : in std_logic_vector ((04*width)-1 downto 0); --! Salidas de los 4 sumadores.
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sqr32blko,inv32blko : in std_logic_vector (width-1 downto 0); --! Salidas de la raiz cuadradas y el inversor.
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fifo32x23_q : in std_logic_vector (03*width-1 downto 0); --! Salida de la cola intermedia.
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fifo32x09_q : in std_logic_vector (02*width-1 downto 0); --! Salida de las colas de producto punto.
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unary,crossprod,addsub : in std_logic; --! Bit con el identificador del bloque AB vs CD e identificador del sub bloque (A/B) o (C/D).
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sync_chain_0 : in std_logic; --! Señal de dato valido que se va por toda la cadena de sincronizacion.
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eoi_int : in std_logic; --! Sennal de interrupción de final de instrucción.
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eoi_demuxed_int : out std_logic_vector (3 downto 0); --! Señal de interrupción de final de instrucción pero esta vez va asociada a la instruccón UCA.
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sqr32blki,inv32blki : out std_logic_vector (width-1 downto 0); --! Salidas de las 2 raices cuadradas y los 2 inversores.
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fifo32x26_d : out std_logic_vector (03*width-1 downto 0); --! Entrada a la cola intermedia para la normalización.
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fifo32x09_d : out std_logic_vector (02*width-1 downto 0); --! Entrada a las colas intermedias del producto punto.
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prd32blki : out std_logic_vector ((12*width)-1 downto 0); --! Entrada de los 12 factores en el bloque de multiplicación respectivamente.
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add32blki : out std_logic_vector ((08*width)-1 downto 0); --! Entrada de los 8 sumandos del bloque de 4 sumadores.
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resw : out std_logic_vector (4 downto 0); --! Salidas de escritura y lectura en las colas de resultados.
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fifo32x09_w : out std_logic;
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fifo32x23_w,fifo32x09_r : out std_logic;
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fifo32x23_r : out std_logic;
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resf_vector : in std_logic_vector(3 downto 0); --! Entradas de la señal de full de las colas de resultados.
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resf_event : out std_logic; --! Salida decodificada que indica que la cola de resultados de la operación que está en curso.
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resultoutput : out std_logic_vector ((08*width)-1 downto 0) --! 8 salidas de resultados, pues lo máximo que podrá calcularse por cada clock son 2 vectores.
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);
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end component;
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--! Bloque Aritmetico de Sumadores y Multiplicadores (madd)
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component arithblock
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port (
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clk : in std_logic;
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rst : in std_logic;
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dpc : in std_logic;
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f : in std_logic_vector (12*32-1 downto 0);
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a : in std_logic_vector (8*32-1 downto 0);
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s : out std_logic_vector (4*32-1 downto 0);
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p : out std_logic_vector (6*32-1 downto 0)
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);
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end component;
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--! Bloque de Raiz Cuadrada
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component sqrt32
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port (
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clk : in std_logic;
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rd32: in std_logic_vector(31 downto 0);
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sq32: out std_logic_vector(31 downto 0)
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);
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end component;
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--! Bloque de Inversores.
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component invr32
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port (
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clk : in std_logic;
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dvd32 : in std_logic_vector(31 downto 0);
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qout32 : out std_logic_vector(31 downto 0)
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);
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end component;
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end package;
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