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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.math_real.all;
 
library std;
use std.textio.all;
 
 
 
--! Memory Compiler Library
library altera_mf;
use altera_mf.all;
library lpm;
use lpm.all;
 
 
 
package arithpack is
        --! Estados para la maquina de estados.
        type macState is (LOAD_INSTRUCTION,FLUSH_ARITH_PIPELINE,EXECUTE_INSTRUCTION);
        --! Estados para el controlador de interrupciones.
        type iCtrlState is (WAITING_FOR_AN_EVENT,FIRING_INTERRUPTIONS,SUSPEND);
 
        --! Float data blocks
        constant floatwidth : integer := 32;
        constant widthadmemblock : integer := 9;
 
 
        subtype xfloat32 is std_logic_vector(31 downto 0);
        type    v3f     is array(02 downto 0) of xfloat32;
 
        --! Constantes para definir 
 
        --!type vectorblock12 is array (11 downto 0) of std_logic_vector(floatwidth-1 downto 0);
        type    vectorblock12 is array (11 downto 0) of xfloat32;
 
        type    vectorblock08 is array (07 downto 0) of xfloat32;
        type    vectorblock06 is array (05 downto 0) of std_logic_vector(floatwidth-1 downto 0);
        type    vectorblock04 is array (03 downto 0) of std_logic_vector(floatwidth-1 downto 0);
        type    vectorblock03 is array (02 downto 0) of std_logic_vector(floatwidth-1 downto 0);
        type    vectorblock02 is array (01 downto 0) of std_logic_vector(floatwidth-1 downto 0);
        type    vectorblockadd02 is array (01 downto 0) of std_logic_vector(widthadmemblock-1 downto 0);
 
 
 
 
 
        --! Constante de reseteo
        constant rstMasterValue : std_logic :='0';
        --! Constantes periodicas.
        constant tclk   : time := 20 ns;
        constant tclk_2 : time := tclk/2;
        constant tclk_4 : time := tclk/4;
 
 
        component raytrac
        port (
 
                clk : in std_logic;
                rst : in std_logic;
 
                --! Se&ntilde;al de lectura de alguna de las colas de resultados.
                rd      : in std_logic;
 
                --! Se&ntilde;al de escritura en alguno de los bloques de memoria de operandos o en la cola de instrucciones.
                wr      : in std_logic;
 
                --! Direccion de escritura o lectura
                add : in std_logic_vector (12 downto 0);
 
                --! datos de entrada
                d       : in std_logic_vector (31 downto 0);
 
                --! Interrupciones
                int     : out std_logic_vector (7 downto 0);
 
                --! Salidas
                q : out std_logic_vector (31 downto 0)
 
 
 
        );
        end component;
 
        --! Componentes Aritm&eacute;ticos
 
        component fadd32
        port (
                clk : in std_logic;
                dpc : in std_logic;
                a32 : in xfloat32;
                b32 : in xfloat32;
                c32 : out xfloat32
        );
        end component;
        component fmul32
        port (
                clk : in std_logic;
                a32 : in xfloat32;
                b32 : in xfloat32;
                p32 : out xfloat32
        );
        end component;
 
 
        --! Contadores para la m&aacute;quina de estados.
 
        component customCounter
        generic (
                EOBFLAG         : string ;
                ZEROFLAG        : string ;
                BACKWARDS       : string ;
                EQUALFLAG       : string ;
                subwidth        : integer;
                width           : integer
 
        );
        port (
                clk,rst,go,set  : in std_logic;
                setValue,cmpBlockValue          : in std_Logic_vector(width-1 downto subwidth);
                zero_flag,eob_flag,eq_flag      : out std_logic;
                count                   : out std_logic_vector(width-1 downto 0)
        );
        end component;
 
        --! LPM_MULTIPLIER
        component lpm_mult
        generic (
                lpm_hint                        : string;
                lpm_pipeline            : natural;
                lpm_representation      : string;
                lpm_type                        : string;
                lpm_widtha                      : natural;
                lpm_widthb                      : natural;
                lpm_widthp                      : natural
        );
        port (
                dataa   : in std_logic_vector ( lpm_widtha-1 downto 0 );
                datab   : in std_logic_vector ( lpm_widthb-1 downto 0 );
                result  : out std_logic_vector( lpm_widthp-1 downto 0 )
        );
        end component;
        --! LPM Memory Compiler.
        component scfifo
        generic (
                add_ram_output_register :string;
                almost_full_value               :natural;
                allow_rwcycle_when_full :string;
                intended_device_family  :string;
                lpm_hint                                :string;
                lpm_numwords                    :natural;
                lpm_showahead                   :string;
                lpm_type                                :string;
                lpm_width                               :natural;
                lpm_widthu                              :natural;
                overflow_checking               :string;
                underflow_checking              :string;
                use_eab                                 :string
        );
        port(
                rdreq           : in std_logic;
                aclr            : in std_logic;
                empty           : out std_logic;
                clock           : in std_logic;
                q                       : out std_logic_vector(lpm_width-1 downto 0);
                wrreq           : in std_logic;
                data            : in std_logic_vector(lpm_width-1 downto 0);
                almost_full : out std_logic;
                full            : out std_logic
        );
        end component;
 
 
        component altsyncram
        generic (
                address_aclr_b                  : string;
                address_reg_b                   : string;
                clock_enable_input_a    : string;
                clock_enable_input_b    : string;
                clock_enable_output_b   : string;
                intended_device_family  : string;
                lpm_type                                : string;
                numwords_a                              : natural;
                numwords_b                              : natural;
                operation_mode                  : string;
                outdata_aclr_b                  : string;
                outdata_reg_b                   : string;
                power_up_uninitialized  : string;
                ram_block_type                  : string;
                rdcontrol_reg_b                 : string;
                read_during_write_mode_mixed_ports      : string;
                widthad_a                               : natural;
                widthad_b                               : natural;
                width_a                                 : natural;
                width_b                                 : natural;
                width_byteena_a                 : natural
        );
        port (
                wren_a          : in std_logic;
                clock0          : in std_logic;
                address_a       : in std_logic_vector(8 downto 0);
                address_b       : in std_logic_vector(8 downto 0);
                rden_b          : in std_logic;
                q_b                     : out std_logic_vector(31 downto 0);
                data_a          : in std_logic_vector(31 downto 0)
 
        );
        end component;
 
        --! Maquina de Estados.
        component sm
 
        port (
 
                --! Se&ntilde;ales normales de secuencia.
                clk,rst:                        in std_logic;
                --! Vector con las instrucci&oacute;n codficada
                instrQq:in std_logic_vector(31 downto 0);
                --! Se&ntilde;al de cola vacia.
                instrQ_empty:in std_logic;
                adda,addb:out std_logic_vector (8 downto 0);
                sync_chain_0,instrRdAckd:out std_logic;
                full_r:         in std_logic;   --! Indica que la cola de resultados no puede aceptar mas de 32 elementos.
                --! End Of Instruction Event
                eoi     : out std_logic;
 
                --! DataPath Control uca code.
                dpc_uca : out std_logic_vector (2 downto 0);
                state   : out macState
        );
        end component;
        --! Maquina de Interrupciones
        component im
        generic (
                num_events : integer ;
                cycles_to_wait : integer
        );
        port (
                clk,rst:                in std_logic;
                rfull_events:   in std_logic_vector(num_events-1 downto 0);      --! full results queue events
                eoi_events:             in std_logic_vector(num_events-1 downto 0);      --! end of instruction related events
                eoi_int:                out std_logic_vector(num_events-1 downto 0);--! end of instruction related interruptions
                rfull_int:              out std_logic_vector(num_events-1downto 0);      --! full results queue related interruptions
                state:                  out iCtrlState
        );
        end component;
        --! Bloque de memorias
        component memblock
        generic (
                blocksize                                       : integer;
                external_readable_widthad       : integer;
                external_writeable_widthad      : integer
        );
        port (
 
 
                clk,rst,dpfifo_rd,normfifo_rd,dpfifo_wr,normfifo_wr : in std_logic;
                instrfifo_rd : in std_logic;
                resultfifo_wr: in std_logic_vector(8-1 downto 0);
                instrfifo_empty: out std_logic; ext_rd,ext_wr: in std_logic;
                ext_wr_add : in std_logic_vector(external_writeable_widthad+widthadmemblock-1 downto 0);
                ext_rd_add : in std_logic_vector(external_readable_widthad-1 downto 0);
                ext_d: in std_logic_vector(floatwidth-1 downto 0);
                int_d : in vectorblock08;
                resultfifo_full  : out std_logic_vector(3 downto 0);
                ext_q,instrfifo_q : out std_logic_vector(floatwidth-1 downto 0);
                int_q : out vectorblock12;
                int_rd_add : in std_logic_vector(2*widthadmemblock-1 downto 0);
                dpfifo_d : in std_logic_vector(floatwidth*2-1 downto 0);
                normfifo_d : in std_logic_vector(floatwidth*3-1 downto 0);
                dpfifo_q : out std_logic_vector(floatwidth*2-1 downto 0);
                normfifo_q : out std_logic_vector(floatwidth*3-1 downto 0)
        );
        end component;
        --! Bloque decodificacion DataPath Control.
        component dpc
        port (
                clk,rst                                 : in    std_logic;
                paraminput                              : in    vectorblock12;  --! Vectores A,B,C,D
                prd32blko                               : in    vectorblock06;  --! Salidas de los 6 multiplicadores.
                add32blko                               : in    vectorblock04;  --! Salidas de los 4 sumadores.
                sqr32blko,inv32blko             : in    std_logic_vector (floatwidth-1 downto 0);                --! Salidas de la raiz cuadradas y el inversor.
                fifo32x23_q                             : in    std_logic_vector (03*floatwidth-1 downto 0);             --! Salida de la cola intermedia.
                fifo32x09_q                             : in    std_logic_vector (02*floatwidth-1 downto 0);     --! Salida de las colas de producto punto. 
                unary,crossprod,addsub  : in    std_logic;                                                                      --! Bit con el identificador del bloque AB vs CD e identificador del sub bloque (A/B) o (C/D). 
                sync_chain_0                    : in    std_logic;                                                                      --! Se&ntilde;al de dato valido que se va por toda la cadena de sincronizacion.
                eoi_int                                 : in    std_logic;                                                                      --! Se&ntilde;al de interrupci&oacute;n de final de instrucci&ocaute;n.
                eoi_demuxed_int                 : out   std_logic_vector (3 downto 0);                           --! Se&ntilde;al de interrup&ocaute;n de final de instrucci&oacute;n pero esta vez va asociada a la instrucc&oacute;n UCA.
                sqr32blki,inv32blki             : out   std_logic_vector (floatwidth-1 downto 0);                --! Salidas de las 2 raices cuadradas y los 2 inversores.
                fifo32x26_d                             : out   std_logic_vector (03*floatwidth-1 downto 0);             --! Entrada a la cola intermedia para la normalizaci&oacute;n.
                fifo32x09_d                             : out   std_logic_vector (02*floatwidth-1 downto 0);             --! Entrada a las colas intermedias del producto punto.         
                prd32blki                               : out   vectorblock12;  --! Entrada de los 12 factores en el bloque de multiplicaci&oacute;n respectivamente.
                add32blki                               : out   vectorblock08;  --! Entrada de los 8 sumandos del bloque de 4 sumadores.  
                resw                                    : out   std_logic_vector (4 downto 0);                           --! Salidas de escritura y lectura en las colas de resultados.
                fifo32x09_w                             : out   std_logic;
                fifo32x23_w,fifo32x09_r : out   std_logic;
                fifo32x23_r                             : out   std_logic;
                resf_vector                             : in    std_logic_vector(3 downto 0);                            --! Entradas de la se&ntilde;al de full de las colas de resultados. 
                resf_event                              : out   std_logic;                                                                      --! Salida decodificada que indica que la cola de resultados de la operaci&oacute;n que est&aacute; en curso.
                resultoutput                    : out   vectorblock08   --! 8 salidas de resultados, pues lo m&aacute;ximo que podr&aacute; calcularse por cada clock son 2 vectores.
        );
        end component;
        --! Bloque Aritmetico de Sumadores y Multiplicadores (madd)
        component arithblock
        port (
 
                clk     : in std_logic;
                rst : in std_logic;
 
                dpc : in std_logic;
 
                f       : in vectorblock12;
                a       : in vectorblock08;
 
                s       : out vectorblock04;
                p       : out vectorblock06
 
        );
        end component;
        --! Bloque de Raiz Cuadrada
        component sqrt32
        port (
 
                clk     : in std_logic;
                rd32: in xfloat32;
                sq32: out xfloat32
        );
        end component;
        --! Bloque de Inversores.
        component invr32
        port (
 
                clk             : in std_logic;
                dvd32   : in xfloat32;
                qout32  : out xfloat32
        );
        end component;
 
 
 
 
        type apCamera is record
                resx,resy : integer;
                width,height : real;
                dist : real;
        end record;
 
        --! Funci&oacute;n que convierte un std_logic_vector en un numero entero
        function ap_slv2int(sl:std_logic_vector) return integer;
 
        --! Funci&oacute;n que convierte un n&uacute;mero flotante IEE754 single float, en un n&uacute;mero std_logic_vector.
        function ap_fp2slv (f:real) return std_logic_vector;
 
        --! Funci&oacute;n que convierte un n&uacute;mero std_logic_vector en un ieee754 single float.
        function ap_slv2fp (sl:std_logic_vector) return real;
 
        --! Funci&oacute;n que devuelve un vector en punto flotante IEEE754 a trav&eacute;s de un   
        function ap_slv_calc_xyvec (x,y:integer; cam:apCamera) return v3f;
 
        --! Funci&oacute;n que devuelve una cadena con el n&uacute;mero flotante IEEE 754 &oacute; a una cadena de cifras hexadecimales.
        function ap_slvf2string(sl:std_logic_vector) return string;
        function ap_slv2hex (s:std_logic_vector) return string;
        --! Funci&oacute;n que devuelve una cadena con el estado de macState.
        function ap_macState2string(s:macState) return string;
 
        --! Funci&oacute;n que devuelve la cadena de caracteres de 8 datos en punto flotante IEEE 754.
        function ap_vblk082string(v8:vectorblock08) return string;
 
        --! Funci&oacute;n que devuelve la cadena de caracteres de 12 datos en punto flotante IEEE 754.
        function ap_vblk122string(v12:vectorblock12) return string;
 
        --! Funci&oacute;n que convierte un array de 2 std_logic_vectors que contienen un par de direcciones en string
        function ap_vnadd022string(va2:vectorblockadd02) return string;
 
        --! Funci&oacute;n que devuelve una cadena de caracteres con el estado de la maquina de estados que controla las interrupciones
        function ap_iCtrlState2string(i:iCtrlState) return string;
 
        --! Funci&oacute;n que devuelve una cadena con los componentes de un vector R3 en punto flotante IEEE754        
        function ap_v3f2string(v:v3f) return string;
 
        --! Funci&oacute;n que formatea una instrucci&oacute;n
        function ap_format_instruction(i:string;ac_o,bd_o,ac_f,bd_f:std_logic_vector;comb:std_logic) return std_logic_vector;
 
        --! Funci&oacute;n que devuelve una cadena de caracteres de un solo caracter con el valor de un bit std_logic
        function ap_sl2string(s:std_logic) return string;
 
end package;
 
 
package body arithpack is
 
        function ap_sl2string(s:std_logic) return string is
                variable tmp:string(1 to 1);
        begin
 
                case s is
                        when '1' =>
                                tmp:="1";
                        when '0' =>
                                tmp:="0";
                        when 'U' =>
                                tmp:="U";
                        when 'X' =>
                                tmp:="X";
                        when 'Z' =>
                                tmp:="Z";
                        when 'W' =>
                                tmp:="W";
                        when 'L' =>
                                tmp:="L";
                        when 'H' =>
                                tmp:="H";
                        when others =>
                                tmp:="-"; -- Don't care
                end case;
 
                return tmp;
        end function;
 
        function ap_format_instruction(i:string;ac_o,bd_o,ac_f,bd_f:std_logic_vector;comb:std_logic) return std_logic_vector is
 
                alias aco : std_logic_vector (4 downto 0) is ac_o;
                alias acf : std_logic_vector (4 downto 0) is ac_f;
                alias bdo : std_logic_vector (4 downto 0) is bd_o;
                alias bdf : std_logic_vector (4 downto 0) is bd_f;
                variable ins : std_logic_vector (31 downto 0);
                alias it : string (1 to 3) is i;
        begin
 
                case it is
                        when "mag" =>
                                ins(31 downto 29) := "100";
                                ins(04 downto 00) := x"18";
                        when "nrm" =>
                                ins(31 downto 29) := "101";
                                ins(04 downto 00) := x"1d";
                        when "add" =>
                                ins(31 downto 29) := "001";
                                ins(04 downto 00) := x"0a";
                        when "sub" =>
                                ins(31 downto 29) := "011";
                                ins(04 downto 00) := x"0a";
                        when "dot" =>
                                ins(31 downto 29) := "000";
                                ins(04 downto 00) := x"17";
                        when "crs" =>
                                ins(31 downto 29) := "010";
                                ins(04 downto 00) := x"0e";
                        when others =>
                                ins(31 downto 29) := "111";
                                ins(04 downto 00) := x"05";
                end case;
                ins(28 downto 24) := aco;
                ins(23 downto 19) := acf;
                ins(18 downto 14) := bdo;
                ins(13 downto 09) := bdf;
                ins(08) := comb;
                ins(07 downto 05) := "000";
                return ins;
 
 
        end function;
 
 
 
        function ap_v3f2string(v:v3f) return string is
                variable tmp:string (1 to 1024);
        begin
                tmp:="[X]"&ap_slvf2string(v(0))&"[Y]"&ap_slvf2string(v(1))&"[Z]"&ap_slvf2string(v(2));
                return tmp;
        end function;
 
        function ap_iCtrlState2string(i:iCtrlState) return string is
 
                variable tmp:string (1 to 9);
 
        begin
 
                case i is
                        when WAITING_FOR_AN_EVENT =>
                                tmp:="WAIT_EVNT";
                        when FIRING_INTERRUPTIONS =>
                                tmp:="FIRE_INTx";
                        when SUSPEND =>
                                tmp:="SUSPENDED";
                        when others =>
                                tmp:="ILGL__VAL";
                end case;
 
                return tmp;
 
        end function;
 
        function ap_vnadd022string(va2:vectorblockadd02) return string is
                variable tmp:string (1 to 1024);
        begin
                tmp:="[01]"&ap_slv2hex(va2(1))&" [00]"&ap_slv2hex(va2(0));
                return tmp;
        end function;
 
        function ap_vblk122string(v12:vectorblock12) return string is
                variable tmp:string (1 to 1024);
        begin
 
                tmp:="["&integer'image(11)&"]";
                for i in 11 downto 0 loop
                        tmp:=tmp&ap_slvf2string(v12(i));
                        if i>0 then
                                tmp:=tmp&"["&integer'image(i)&"]";
                        end if;
                end loop;
                return tmp;
 
 
        end function;
 
        function ap_vblk082string(v8:vectorblock08) return string is
                variable tmp:string (1 to 1024);
        begin
 
                tmp:="["&integer'image(7)&"]";
                for i in 7 downto 0 loop
                        tmp:=tmp&ap_slvf2string(v8(i));
                        if i>0 then
                                tmp:=tmp&"["&integer'image(i)&"]";
                        end if;
                end loop;
                return tmp;
 
 
        end function;
 
 
        function ap_macState2string(s:macState) return string is
                variable tmp:string (1 to 6);
        begin
                case s is
                        when LOAD_INSTRUCTION =>
                                tmp:="LD_INS";
                        when FLUSH_ARITH_PIPELINE =>
                                tmp:="FL_ARP";
                        when EXECUTE_INSTRUCTION =>
                                tmp:="EX_INS";
                        when others =>
                                tmp:="HEL_ON";
                end case;
                return tmp;
        end function;
 
        constant hexchars : string (1 to 16) := "0123456789ABCDEF";
        function ap_slv2hex (s:std_logic_vector) return string is
                variable x64 : std_logic_vector(63 downto 0):=x"0000000000000000";
                variable str : string (1 to 16);
        begin
                x64(s'high downto s'low):=s;
                for i in 15 downto 0 loop
                        str(i+1):=hexchars(1+ieee.std_logic_unsigned.conv_integer(x64(i*4+3 downto i*4)));
                end loop;
                return str;
        end function;
 
        function ap_slv2int (sl:std_logic_vector) return integer is
                alias s : std_logic_vector (sl'high downto sl'low) is sl;
                variable i : integer;
        begin
                i:=0;
                for index in s'high downto s'low loop
                        if s(index)='1' then
                                i:=i*2+1;
                        else
                                i:=i*2;
                        end if;
                end loop;
                return i;
 
        end function;
        function ap_fp2slv (f:real) return std_logic_vector is
                variable faux : real;
                variable sef : std_logic_vector (31 downto 0);
        begin
                --! Signo
                if (f<0.0) then
                        sef(31) := '1';
                else
                        sef(31) := '0';
                end if;
 
                --! Exponente
                sef(30 downto 23) := conv_std_logic_vector(integer(floor(log(f,2.0))),8);
 
                --! Fraction
                faux :=f/floor(log(f,2.0));
                faux := faux - 1.0;
 
                sef(22 downto 0)  := conv_std_logic_vector(integer(faux),23);
 
                return sef;
 
        end function;
 
        function ap_slv2fp(sl:std_logic_vector) return real is
                variable expo,frc:integer;
                alias s: std_logic_vector(31 downto 0) is sl;
                variable f: real;
 
        begin
 
 
                expo:=ap_slv2int(s(30 downto 23)) - 127;
                expo:=2**expo;
                frc:=ap_slv2int('1'&s(22 downto 0));
                f:=real(frc)*(2.0**(-23.0));
                f:=f*real(expo);
 
                if s(31)='1' then
                        return -f;
                else
                        return f;
                end if;
 
 
        end function;
 
        function ap_slv_calc_xyvec (x,y:integer; cam:apCamera) return v3f is
 
 
                variable dx,dy : real;
                variable v : v3f;
        begin
 
                dx := cam.width/real(cam.resx);
                dy := cam.height/real(cam.resy);
 
                --! Eje X: Tomando el dedo &iacute;ndice de la mano derecha, este eje queda apuntando en la direcci&on en la que mira la c&aacute;mara u observador siempre.
                v(0):=ap_fp2slv(cam.dist);
 
                --! Eje Y: Tomando el dedo coraz&oacute;n de la mano derecha, este eje queda apuntando a la izquierda del observador, desde el observador.
                v(1):=ap_fp2slv(dx*real(cam.resx)*0.5-dx*0.5);
 
                --! Eje Z: Tomando el dedo pulgar de la mano derecha, este eje queda apuntando hacia arriba del observador, desde el observador.
                v(2):=ap_fp2slv(dy*real(cam.resy)*0.5-dy*0.5);
 
                return v;
 
        end function;
 
        function ap_slvf2string(sl:std_logic_vector) return string is
                alias f: std_logic_vector(31 downto 0) is sl;
                variable r: real;
 
        begin
 
                r:=ap_slv2fp(f);
                return real'image(r);
 
        end function;
 
 
 
 
end package body;

Line No.	Rev	Author	Line
1	151	jguarin200	`library ieee;`
2			`use ieee.std_logic_1164.all;`
3	153	jguarin200	`use ieee.std_logic_arith.all;`
4			`use ieee.math_real.all;`
5	151	jguarin200
6	153	jguarin200	`library std;`
7			`use std.textio.all;`
8
9	159	jguarin200
10
11	151	jguarin200	`--! Memory Compiler Library`
12	159	jguarin200	`library altera_mf;`
13			`use altera_mf.all;`
14	151	jguarin200	`library lpm;`
15			`use lpm.all;`
16
17
18
19			`package arithpack is`
20			`--! Estados para la maquina de estados.`
21			`type macState is (LOAD_INSTRUCTION,FLUSH_ARITH_PIPELINE,EXECUTE_INSTRUCTION);`
22			`--! Estados para el controlador de interrupciones.`
23			`type iCtrlState is (WAITING_FOR_AN_EVENT,FIRING_INTERRUPTIONS,SUSPEND);`
24	152	jguarin200
25			`--! Float data blocks`
26			`constant floatwidth : integer := 32;`
27			`constant widthadmemblock : integer := 9;`
28
29	156	jguarin200
30			`subtype xfloat32 is std_logic_vector(31 downto 0);`
31			`type v3f is array(02 downto 0) of xfloat32;`
32
33			`--! Constantes para definir`
34
35			`--!type vectorblock12 is array (11 downto 0) of std_logic_vector(floatwidth-1 downto 0);`
36			`type vectorblock12 is array (11 downto 0) of xfloat32;`
37
38			`type vectorblock08 is array (07 downto 0) of xfloat32;`
39	152	jguarin200	`type vectorblock06 is array (05 downto 0) of std_logic_vector(floatwidth-1 downto 0);`
40			`type vectorblock04 is array (03 downto 0) of std_logic_vector(floatwidth-1 downto 0);`
41			`type vectorblock03 is array (02 downto 0) of std_logic_vector(floatwidth-1 downto 0);`
42			`type vectorblock02 is array (01 downto 0) of std_logic_vector(floatwidth-1 downto 0);`
43			`type vectorblockadd02 is array (01 downto 0) of std_logic_vector(widthadmemblock-1 downto 0);`
44
45
46	153	jguarin200
47
48	156	jguarin200
49	151	jguarin200	`--! Constante de reseteo`
50			`constant rstMasterValue : std_logic :='0';`
51			`--! Constantes periodicas.`
52			`constant tclk : time := 20 ns;`
53			`constant tclk_2 : time := tclk/2;`
54			`constant tclk_4 : time := tclk/4;`
55
56	152	jguarin200
57			`component raytrac`
58			`port (`
59
60			`clk : in std_logic;`
61			`rst : in std_logic;`
62
63			`--! Señal de lectura de alguna de las colas de resultados.`
64			`rd : in std_logic;`
65
66			`--! Señal de escritura en alguno de los bloques de memoria de operandos o en la cola de instrucciones.`
67			`wr : in std_logic;`
68
69			`--! Direccion de escritura o lectura`
70			`add : in std_logic_vector (12 downto 0);`
71
72			`--! datos de entrada`
73			`d : in std_logic_vector (31 downto 0);`
74
75			`--! Interrupciones`
76			`int : out std_logic_vector (7 downto 0);`
77
78			`--! Salidas`
79			`q : out std_logic_vector (31 downto 0)`
80
81
82
83			`);`
84			`end component;`
85
86			`--! Componentes Aritméticos`
87
88			`component fadd32`
89			`port (`
90			`clk : in std_logic;`
91			`dpc : in std_logic;`
92	158	jguarin200	`a32 : in xfloat32;`
93			`b32 : in xfloat32;`
94			`c32 : out xfloat32`
95	152	jguarin200	`);`
96			`end component;`
97			`component fmul32`
98			`port (`
99			`clk : in std_logic;`
100	158	jguarin200	`a32 : in xfloat32;`
101			`b32 : in xfloat32;`
102			`p32 : out xfloat32`
103	152	jguarin200	`);`
104			`end component;`
105
106
107			`--! Contadores para la máquina de estados.`
108
109	151	jguarin200	`component customCounter`
110			`generic (`
111			`EOBFLAG : string ;`
112			`ZEROFLAG : string ;`
113			`BACKWARDS : string ;`
114			`EQUALFLAG : string ;`
115			`subwidth : integer;`
116			`width : integer`
117
118			`);`
119			`port (`
120			`clk,rst,go,set : in std_logic;`
121			`setValue,cmpBlockValue : in std_Logic_vector(width-1 downto subwidth);`
122			`zero_flag,eob_flag,eq_flag : out std_logic;`
123			`count : out std_logic_vector(width-1 downto 0)`
124			`);`
125			`end component;`
126
127	155	jguarin200	`--! LPM_MULTIPLIER`
128			`component lpm_mult`
129			`generic (`
130			`lpm_hint : string;`
131			`lpm_pipeline : natural;`
132			`lpm_representation : string;`
133			`lpm_type : string;`
134			`lpm_widtha : natural;`
135			`lpm_widthb : natural;`
136			`lpm_widthp : natural`
137			`);`
138			`port (`
139			`dataa : in std_logic_vector ( lpm_widtha-1 downto 0 );`
140			`datab : in std_logic_vector ( lpm_widthb-1 downto 0 );`
141			`result : out std_logic_vector( lpm_widthp-1 downto 0 )`
142			`);`
143			`end component;`
144	151	jguarin200	`--! LPM Memory Compiler.`
145			`component scfifo`
146			`generic (`
147			`add_ram_output_register :string;`
148			`almost_full_value :natural;`
149	159	jguarin200	`allow_rwcycle_when_full :string;`
150	151	jguarin200	`intended_device_family :string;`
151			`lpm_hint :string;`
152			`lpm_numwords :natural;`
153			`lpm_showahead :string;`
154			`lpm_type :string;`
155			`lpm_width :natural;`
156			`lpm_widthu :natural;`
157			`overflow_checking :string;`
158			`underflow_checking :string;`
159			`use_eab :string`
160			`);`
161			`port(`
162			`rdreq : in std_logic;`
163			`aclr : in std_logic;`
164			`empty : out std_logic;`
165			`clock : in std_logic;`
166			`q : out std_logic_vector(lpm_width-1 downto 0);`
167			`wrreq : in std_logic;`
168			`data : in std_logic_vector(lpm_width-1 downto 0);`
169			`almost_full : out std_logic;`
170			`full : out std_logic`
171			`);`
172			`end component;`
173
174
175			`component altsyncram`
176			`generic (`
177			`address_aclr_b : string;`
178			`address_reg_b : string;`
179			`clock_enable_input_a : string;`
180			`clock_enable_input_b : string;`
181			`clock_enable_output_b : string;`
182			`intended_device_family : string;`
183			`lpm_type : string;`
184			`numwords_a : natural;`
185			`numwords_b : natural;`
186			`operation_mode : string;`
187			`outdata_aclr_b : string;`
188			`outdata_reg_b : string;`
189			`power_up_uninitialized : string;`
190			`ram_block_type : string;`
191			`rdcontrol_reg_b : string;`
192			`read_during_write_mode_mixed_ports : string;`
193			`widthad_a : natural;`
194			`widthad_b : natural;`
195			`width_a : natural;`
196			`width_b : natural;`
197			`width_byteena_a : natural`
198			`);`
199			`port (`
200			`wren_a : in std_logic;`
201			`clock0 : in std_logic;`
202			`address_a : in std_logic_vector(8 downto 0);`
203			`address_b : in std_logic_vector(8 downto 0);`
204			`rden_b : in std_logic;`
205			`q_b : out std_logic_vector(31 downto 0);`
206			`data_a : in std_logic_vector(31 downto 0)`
207
208			`);`
209			`end component;`
210
211			`--! Maquina de Estados.`
212			`component sm`
213	152	jguarin200
214	151	jguarin200	`port (`
215
216			`--! Señales normales de secuencia.`
217			`clk,rst: in std_logic;`
218	152	jguarin200	`--! Vector con las instrucción codficada`
219	151	jguarin200	`instrQq:in std_logic_vector(31 downto 0);`
220	152	jguarin200	`--! Señal de cola vacia.`
221	151	jguarin200	`instrQ_empty:in std_logic;`
222			`adda,addb:out std_logic_vector (8 downto 0);`
223			`sync_chain_0,instrRdAckd:out std_logic;`
224			`full_r: in std_logic; --! Indica que la cola de resultados no puede aceptar mas de 32 elementos.`
225			`--! End Of Instruction Event`
226			`eoi : out std_logic;`
227
228			`--! DataPath Control uca code.`
229			`dpc_uca : out std_logic_vector (2 downto 0);`
230			`state : out macState`
231			`);`
232			`end component;`
233			`--! Maquina de Interrupciones`
234			`component im`
235			`generic (`
236			`num_events : integer ;`
237			`cycles_to_wait : integer`
238			`);`
239			`port (`
240			`clk,rst: in std_logic;`
241			`rfull_events: in std_logic_vector(num_events-1 downto 0); --! full results queue events`
242			`eoi_events: in std_logic_vector(num_events-1 downto 0); --! end of instruction related events`
243			`eoi_int: out std_logic_vector(num_events-1 downto 0);--! end of instruction related interruptions`
244			`rfull_int: out std_logic_vector(num_events-1downto 0); --! full results queue related interruptions`
245			`state: out iCtrlState`
246			`);`
247			`end component;`
248			`--! Bloque de memorias`
249			`component memblock`
250			`generic (`
251			`blocksize : integer;`
252			`external_readable_widthad : integer;`
253			`external_writeable_widthad : integer`
254			`);`
255			`port (`
256
257
258			`clk,rst,dpfifo_rd,normfifo_rd,dpfifo_wr,normfifo_wr : in std_logic;`
259			`instrfifo_rd : in std_logic;`
260	158	jguarin200	`resultfifo_wr: in std_logic_vector(8-1 downto 0);`
261	151	jguarin200	`instrfifo_empty: out std_logic; ext_rd,ext_wr: in std_logic;`
262			`ext_wr_add : in std_logic_vector(external_writeable_widthad+widthadmemblock-1 downto 0);`
263			`ext_rd_add : in std_logic_vector(external_readable_widthad-1 downto 0);`
264	152	jguarin200	`ext_d: in std_logic_vector(floatwidth-1 downto 0);`
265	158	jguarin200	`int_d : in vectorblock08;`
266	151	jguarin200	`resultfifo_full : out std_logic_vector(3 downto 0);`
267	152	jguarin200	`ext_q,instrfifo_q : out std_logic_vector(floatwidth-1 downto 0);`
268	158	jguarin200	`int_q : out vectorblock12;`
269	151	jguarin200	`int_rd_add : in std_logic_vector(2*widthadmemblock-1 downto 0);`
270	152	jguarin200	`dpfifo_d : in std_logic_vector(floatwidth*2-1 downto 0);`
271			`normfifo_d : in std_logic_vector(floatwidth*3-1 downto 0);`
272			`dpfifo_q : out std_logic_vector(floatwidth*2-1 downto 0);`
273			`normfifo_q : out std_logic_vector(floatwidth*3-1 downto 0)`
274	151	jguarin200	`);`
275			`end component;`
276			`--! Bloque decodificacion DataPath Control.`
277			`component dpc`
278			`port (`
279			`clk,rst : in std_logic;`
280	158	jguarin200	`paraminput : in vectorblock12; --! Vectores A,B,C,D`
281			`prd32blko : in vectorblock06; --! Salidas de los 6 multiplicadores.`
282			`add32blko : in vectorblock04; --! Salidas de los 4 sumadores.`
283	152	jguarin200	`sqr32blko,inv32blko : in std_logic_vector (floatwidth-1 downto 0); --! Salidas de la raiz cuadradas y el inversor.`
284			`fifo32x23_q : in std_logic_vector (03*floatwidth-1 downto 0); --! Salida de la cola intermedia.`
285			`fifo32x09_q : in std_logic_vector (02*floatwidth-1 downto 0); --! Salida de las colas de producto punto.`
286	151	jguarin200	`unary,crossprod,addsub : in std_logic; --! Bit con el identificador del bloque AB vs CD e identificador del sub bloque (A/B) o (C/D).`
287	152	jguarin200	`sync_chain_0 : in std_logic; --! Señal de dato valido que se va por toda la cadena de sincronizacion.`
288			`eoi_int : in std_logic; --! Señal de interrupción de final de instrucci&ocaute;n.`
289			`eoi_demuxed_int : out std_logic_vector (3 downto 0); --! Señal de interrup&ocaute;n de final de instrucción pero esta vez va asociada a la instruccón UCA.`
290			`sqr32blki,inv32blki : out std_logic_vector (floatwidth-1 downto 0); --! Salidas de las 2 raices cuadradas y los 2 inversores.`
291			`fifo32x26_d : out std_logic_vector (03*floatwidth-1 downto 0); --! Entrada a la cola intermedia para la normalización.`
292			`fifo32x09_d : out std_logic_vector (02*floatwidth-1 downto 0); --! Entrada a las colas intermedias del producto punto.`
293	158	jguarin200	`prd32blki : out vectorblock12; --! Entrada de los 12 factores en el bloque de multiplicación respectivamente.`
294			`add32blki : out vectorblock08; --! Entrada de los 8 sumandos del bloque de 4 sumadores.`
295	151	jguarin200	`resw : out std_logic_vector (4 downto 0); --! Salidas de escritura y lectura en las colas de resultados.`
296			`fifo32x09_w : out std_logic;`
297			`fifo32x23_w,fifo32x09_r : out std_logic;`
298			`fifo32x23_r : out std_logic;`
299			`resf_vector : in std_logic_vector(3 downto 0); --! Entradas de la señal de full de las colas de resultados.`
300			`resf_event : out std_logic; --! Salida decodificada que indica que la cola de resultados de la operación que está en curso.`
301	158	jguarin200	`resultoutput : out vectorblock08 --! 8 salidas de resultados, pues lo máximo que podrá calcularse por cada clock son 2 vectores.`
302	151	jguarin200	`);`
303			`end component;`
304			`--! Bloque Aritmetico de Sumadores y Multiplicadores (madd)`
305			`component arithblock`
306			`port (`
307
308			`clk : in std_logic;`
309			`rst : in std_logic;`
310
311			`dpc : in std_logic;`
312
313	158	jguarin200	`f : in vectorblock12;`
314			`a : in vectorblock08;`
315	151	jguarin200
316	158	jguarin200	`s : out vectorblock04;`
317			`p : out vectorblock06`
318	151	jguarin200
319			`);`
320			`end component;`
321			`--! Bloque de Raiz Cuadrada`
322			`component sqrt32`
323			`port (`
324
325			`clk : in std_logic;`
326	158	jguarin200	`rd32: in xfloat32;`
327			`sq32: out xfloat32`
328	151	jguarin200	`);`
329			`end component;`
330			`--! Bloque de Inversores.`
331			`component invr32`
332			`port (`
333
334			`clk : in std_logic;`
335	158	jguarin200	`dvd32 : in xfloat32;`
336			`qout32 : out xfloat32`
337	151	jguarin200	`);`
338			`end component;`
339	153	jguarin200
340
341
342
343			`type apCamera is record`
344			`resx,resy : integer;`
345			`width,height : real;`
346			`dist : real;`
347			`end record;`
348
349			`--! Función que convierte un std_logic_vector en un numero entero`
350			`function ap_slv2int(sl:std_logic_vector) return integer;`
351
352			`--! Función que convierte un número flotante IEE754 single float, en un número std_logic_vector.`
353			`function ap_fp2slv (f:real) return std_logic_vector;`
354
355			`--! Función que convierte un número std_logic_vector en un ieee754 single float.`
356			`function ap_slv2fp (sl:std_logic_vector) return real;`
357
358			`--! Función que devuelve un vector en punto flotante IEEE754 a través de un`
359			`function ap_slv_calc_xyvec (x,y:integer; cam:apCamera) return v3f;`
360
361	156	jguarin200	`--! Función que devuelve una cadena con el número flotante IEEE 754 ó a una cadena de cifras hexadecimales.`
362	155	jguarin200	`function ap_slvf2string(sl:std_logic_vector) return string;`
363	156	jguarin200	`function ap_slv2hex (s:std_logic_vector) return string;`
364			`--! Función que devuelve una cadena con el estado de macState.`
365			`function ap_macState2string(s:macState) return string;`
366	153	jguarin200
367	156	jguarin200	`--! Función que devuelve la cadena de caracteres de 8 datos en punto flotante IEEE 754.`
368			`function ap_vblk082string(v8:vectorblock08) return string;`
369	153	jguarin200
370	156	jguarin200	`--! Función que devuelve la cadena de caracteres de 12 datos en punto flotante IEEE 754.`
371			`function ap_vblk122string(v12:vectorblock12) return string;`
372	153	jguarin200
373	156	jguarin200	`--! Función que convierte un array de 2 std_logic_vectors que contienen un par de direcciones en string`
374			`function ap_vnadd022string(va2:vectorblockadd02) return string;`
375	153	jguarin200
376	156	jguarin200	`--! Función que devuelve una cadena de caracteres con el estado de la maquina de estados que controla las interrupciones`
377			`function ap_iCtrlState2string(i:iCtrlState) return string;`
378
379			`--! Función que devuelve una cadena con los componentes de un vector R3 en punto flotante IEEE754`
380			`function ap_v3f2string(v:v3f) return string;`
381	157	jguarin200
382			`--! Función que formatea una instrucción`
383			`function ap_format_instruction(i:string;ac_o,bd_o,ac_f,bd_f:std_logic_vector;comb:std_logic) return std_logic_vector;`
384
385			`--! Función que devuelve una cadena de caracteres de un solo caracter con el valor de un bit std_logic`
386			`function ap_sl2string(s:std_logic) return string;`
387	156	jguarin200
388	151	jguarin200	`end package;`
389	153	jguarin200
390
391			`package body arithpack is`
392
393	157	jguarin200	`function ap_sl2string(s:std_logic) return string is`
394			`variable tmp:string(1 to 1);`
395			`begin`
396
397			`case s is`
398			`when '1' =>`
399			`tmp:="1";`
400			`when '0' =>`
401			`tmp:="0";`
402			`when 'U' =>`
403			`tmp:="U";`
404			`when 'X' =>`
405			`tmp:="X";`
406			`when 'Z' =>`
407			`tmp:="Z";`
408			`when 'W' =>`
409			`tmp:="W";`
410			`when 'L' =>`
411			`tmp:="L";`
412			`when 'H' =>`
413			`tmp:="H";`
414			`when others =>`
415			`tmp:="-"; -- Don't care`
416			`end case;`
417
418			`return tmp;`
419			`end function;`
420
421			`function ap_format_instruction(i:string;ac_o,bd_o,ac_f,bd_f:std_logic_vector;comb:std_logic) return std_logic_vector is`
422
423			`alias aco : std_logic_vector (4 downto 0) is ac_o;`
424			`alias acf : std_logic_vector (4 downto 0) is ac_f;`
425			`alias bdo : std_logic_vector (4 downto 0) is bd_o;`
426			`alias bdf : std_logic_vector (4 downto 0) is bd_f;`
427			`variable ins : std_logic_vector (31 downto 0);`
428			`alias it : string (1 to 3) is i;`
429			`begin`
430
431			`case it is`
432			`when "mag" =>`
433			`ins(31 downto 29) := "100";`
434			`ins(04 downto 00) := x"18";`
435			`when "nrm" =>`
436			`ins(31 downto 29) := "101";`
437			`ins(04 downto 00) := x"1d";`
438			`when "add" =>`
439			`ins(31 downto 29) := "001";`
440			`ins(04 downto 00) := x"0a";`
441			`when "sub" =>`
442			`ins(31 downto 29) := "011";`
443			`ins(04 downto 00) := x"0a";`
444			`when "dot" =>`
445			`ins(31 downto 29) := "000";`
446			`ins(04 downto 00) := x"17";`
447			`when "crs" =>`
448			`ins(31 downto 29) := "010";`
449			`ins(04 downto 00) := x"0e";`
450			`when others =>`
451			`ins(31 downto 29) := "111";`
452			`ins(04 downto 00) := x"05";`
453			`end case;`
454			`ins(28 downto 24) := aco;`
455			`ins(23 downto 19) := acf;`
456			`ins(18 downto 14) := bdo;`
457			`ins(13 downto 09) := bdf;`
458			`ins(08) := comb;`
459			`ins(07 downto 05) := "000";`
460			`return ins;`
461
462
463			`end function;`
464
465
466
467	156	jguarin200	`function ap_v3f2string(v:v3f) return string is`
468	157	jguarin200	`variable tmp:string (1 to 1024);`
469	155	jguarin200	`begin`
470	156	jguarin200	`tmp:="[X]"&ap_slvf2string(v(0))&"[Y]"&ap_slvf2string(v(1))&"[Z]"&ap_slvf2string(v(2));`
471			`return tmp;`
472			`end function;`
473	155	jguarin200
474	156	jguarin200	`function ap_iCtrlState2string(i:iCtrlState) return string is`
475
476	158	jguarin200	`variable tmp:string (1 to 9);`
477	156	jguarin200
478			`begin`
479
480			`case i is`
481			`when WAITING_FOR_AN_EVENT =>`
482			`tmp:="WAIT_EVNT";`
483			`when FIRING_INTERRUPTIONS =>`
484			`tmp:="FIRE_INTx";`
485			`when SUSPEND =>`
486			`tmp:="SUSPENDED";`
487			`when others =>`
488	158	jguarin200	`tmp:="ILGL__VAL";`
489	156	jguarin200	`end case;`
490
491			`return tmp;`
492
493			`end function;`
494
495			`function ap_vnadd022string(va2:vectorblockadd02) return string is`
496	157	jguarin200	`variable tmp:string (1 to 1024);`
497	156	jguarin200	`begin`
498			`tmp:="[01]"&ap_slv2hex(va2(1))&" [00]"&ap_slv2hex(va2(0));`
499			`return tmp;`
500			`end function;`

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