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Fmax Summary report for cycloneIII_3c25_niosII_video

Wed Aug 15 10:41:42 2012

Quartus II Version 11.0 Build 157 04/27/2011 SJ Web Edition

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; Table of Contents ;

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  1. Legal Notice

  2. Slow 1200mV 85C Model Fmax Summary

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; Legal Notice ;

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(including device programming or simulation files), and any

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applicable agreement for further details.

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; Slow 1200mV 85C Model Fmax Summary                                                                                                                                                                                                                                                  ;

+------------+-----------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------+

; Fmax       ; Restricted Fmax ; Clock Name                                                                                                                                                                                   ; Note                                                  ;

+------------+-----------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------+

; 62.89 MHz  ; 40.0 MHz        ; cycloneIII_3c25_niosII_video_sopc_instance|the_pll|the_pll|altpll_component|auto_generated|pll1|clk[3]                                                                                       ; limit due to minimum period restriction (tmin)        ;

; 74.37 MHz  ; 24.56 MHz       ; altera_reserved_tck                                                                                                                                                                          ; limit due to high minimum pulse width violation (tch) ;

; 83.94 MHz  ; 83.94 MHz       ; cycloneIII_3c25_niosII_video_sopc_instance|the_ddr_sdram|ddr_sdram_controller_phy_inst|ddr_sdram_phy_inst|ddr_sdram_phy_alt_mem_phy_inst|clk|pll|altpll_component|auto_generated|pll1|clk[0] ;                                                       ;

; 95.21 MHz  ; 95.21 MHz       ; cycloneIII_3c25_niosII_video_sopc_instance|the_pll|the_pll|altpll_component|auto_generated|pll1|clk[2]                                                                                       ;                                                       ;

; 117.51 MHz ; 117.51 MHz      ; cycloneIII_3c25_niosII_video_sopc_instance|the_ddr_sdram|ddr_sdram_controller_phy_inst|ddr_sdram_phy_inst|ddr_sdram_phy_alt_mem_phy_inst|clk|scan_clk|q_clock                                ;                                                       ;

; 118.04 MHz ; 118.04 MHz      ; cycloneIII_3c25_niosII_video_sopc_instance|the_pll|the_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                       ;                                                       ;

; 229.62 MHz ; 229.62 MHz      ; top_clkin_50                                                                                                                                                                                 ;                                                       ;

; 238.83 MHz ; 238.83 MHz      ; cycloneIII_3c25_niosII_video_sopc_instance|the_ddr_sdram|ddr_sdram_controller_phy_inst|ddr_sdram_phy_inst|ddr_sdram_phy_alt_mem_phy_inst|clk|pll|altpll_component|auto_generated|pll1|clk[2] ;                                                       ;

; 328.08 MHz ; 315.06 MHz      ; cycloneIII_3c25_niosII_video_sopc_instance|the_ddr_sdram|ddr_sdram_controller_phy_inst|ddr_sdram_phy_inst|ddr_sdram_phy_alt_mem_phy_inst|clk|pll|altpll_component|auto_generated|pll1|clk[3] ; limit due to minimum period restriction (tmin)        ;

; 391.54 MHz ; 391.54 MHz      ; cycloneIII_3c25_niosII_video_sopc_instance|the_ddr_sdram|ddr_sdram_controller_phy_inst|ddr_sdram_phy_inst|ddr_sdram_phy_alt_mem_phy_inst|clk|pll|altpll_component|auto_generated|pll1|clk[4] ;                                                       ;

; 483.09 MHz ; 250.0 MHz       ; cycloneIII_3c25_niosII_video_sopc_instance|the_ddr_sdram|ddr_sdram_controller_phy_inst|ddr_sdram_phy_inst|ddr_sdram_phy_alt_mem_phy_inst|clk|pll|altpll_component|auto_generated|pll1|clk[1] ; limit due to minimum port rate restriction (tmin)     ;

+------------+-----------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------+

This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.