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--! @file dpc.vhd
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--! @brief Decodificador de operacion.
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--! @author Julián Andrés Guarín Reyes.
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--------------------------------------------------------------
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-- RAYTRAC
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-- Author Julian Andres Guarin
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-- dpc.vhd
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-- This file is part of raytrac.
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--
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-- raytrac is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- raytrac is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with raytrac. If not, see <http://www.gnu.org/licenses/>.
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library ieee;
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use ieee.std_logic_1164.all;
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entity dpc is
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generic (
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width : integer := 32
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);
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port (
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paraminput : in std_logic_vector ((12*width)-1 downto 0); --! Vectores A,B,C,D
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prd32blko,add32blko : in std_logic_vector ((06*width)-1 downto 0); --! Salidas de los 6 multiplicadores y los 6 sumadores.
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sqr32blko,inv32blko : in std_logic_vector ((02*width)-1 downto 0); --! Salidas de las 2 raices cuadradas y los 2 inversores.
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fifo32o : in std_logic_vector ( width-1 downto 0); --! Salida de la cola intermedia.
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instr3 : in std_logic_vector ( 2 downto 0); --! Opcode con la instrucción.
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fifo32i : out std_logic_vector ( width-1 downto 0); --! Entrada a la cola intermedia.
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prd32blki,add32blki : out std_logic_vector ((12*width)-1 downto 0); --! Entrada de los 12 sumandos y de los 12 factores en los 2 bloques de suma y el bloque de multiplicación respectivamente.
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add32blks : out std_logic_vector ( 1 downto 0); --! Signos de operación que entran en los 2 bloques de suma.
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resultoutput : out std_logic_vector ((06*width)-1 downto 0) --! 6 salidas de resultados, pues lo máximo que podrá calcularse por cada clock son 2 vectores.
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);
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end dpc;
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architecture dpc_arch of dpc is
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component scfifo
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generic (
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add_ram_output_register : string;
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intended_device_family : string;
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lpm_hint : string;
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lpm_numwords : natural;
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lpm_showahead : string;
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lpm_type : string;
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lpm_width : natural;
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lpm_widthu : natural;
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overflow_checking : string;
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underflow_checking : string;
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use_eab : string
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);
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port (
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rd
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)
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constant az : integer := 00;constant ay : integer := 01;constant ax : integer := 02;constant bz : integer := 03;constant by : integer := 04;constant bx : integer := 05;
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constant cz : integer := 06;constant cy : integer := 07;constant cx : integer := 08;constant dz : integer := 09;constant dy : integer := 10;constant dx : integer := 11;
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constant f0 : integer := 00;constant f1 : integer := 01;constant f2 : integer := 02;constant f3 : integer := 03;constant f4 : integer := 04;constant f5 : integer := 05;
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constant f6 : integer := 06;constant f7 : integer := 07;constant f8 : integer := 08;constant f9 : integer := 09;constant f10: integer := 10;constant f11: integer := 11;
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constant s0 : integer := 00;constant s1 : integer := 01;constant s2 : integer := 02;constant s3 : integer := 03;constant s4 : integer := 04;constant s5 : integer := 05;
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constant s6 : integer := 06;constant s7 : integer := 07;constant s8 : integer := 08;constant s9 : integer := 09;constant s10: integer := 10;constant s11: integer := 11;
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constant a0 : integer := 00;constant a1 : integer := 01;constant a2 : integer := 02;constant aa : integer := 03;constant ab : integer := 04;constant ac : integer := 05;
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constant p0 : integer := 00;constant p1 : integer := 01;constant p2 : integer := 02;constant p3 : integer := 03;constant p4 : integer := 04;constant p5 : integer := 05;
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constant sqrt320 : integer := 00;
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constant sqrt321 : integer := 01;
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constant invr320 : integer := 00;
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constant invr321 : integer := 01;
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type vectorblock12 is array (11 downto 0) of std_logic_vector(width-1 downto 0);
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type vectorblock06 is array (05 downto 0) of std_logic_vector(width-1 downto 0);
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type vectorblock02 is array (01 downto 0) of std_logic_vector(width-1 downto 0);
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signal sparaminput,sfactor,ssumando : vectorblock12;
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signal sprd32blk,sadd32blk,sresult : vectorblock06;
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signal ssqr32blk,sinv32blk : vectorblock02;
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begin
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--! Connect stuff ....
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stuff12:
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for i in 11 downto 0 generate
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sparaminput(i) <= paraminput(i*width+width-1 downto i*width);
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prd32blki(i*width+width-1 downto i*width) <= sfactor(i);
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add32blki(i*width+width-1 downto i*width) <= ssumando(i);
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end generate stuff12;
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stuff06:
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for i in 05 downto 0 generate
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sprd32blk(i) <= prd32blko(i*width+width-1 downto i*width);
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sadd32blk(i) <= add32blko(i*width+width-1 downto i*width);
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resultoutput(i*width+width-1 downto i*width) <= sresult(i);
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end generate stuff06;
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stuff02:
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for i in 05 downto 0 generate
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ssqr32blk(i) <= sqr32blko(i*width+width-1 downto i*width);
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sinv32blk(i) <= inv32blko(i*width+width-1 downto i*width);
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end generate stuff02;
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fifoconnection_proces:process(instr3)
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begin
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case (instr3) is
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end process;
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end dpc_arch;
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