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        --! @file memblock.vhd
--! @brief Bloque de memoria. 
--! @author Juli&aacute;n Andr&eacute;s Guar&iacute;n Reyes
--------------------------------------------------------------
-- RAYTRAC
-- Author Julian Andres Guarin
-- memblock.vhd
-- This file is part of raytrac.
-- 
--     raytrac is free software: you can redistribute it and/or modify
--     it under the terms of the GNU General Public License as published by
--     the Free Software Foundation, either version 3 of the License, or
--     (at your option) any later version.
-- 
--     raytrac is distributed in the hope that it will be useful,
--     but WITHOUT ANY WARRANTY; without even the implied warranty of
--     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--     GNU General Public License for more details.
-- 
--     You should have received a copy of the GNU General Public License
--     along with raytrac.  If not, see <http://www.gnu.org/licenses/>.
 
library ieee;
use ieee.std_logic_1164.all;
 
entity memblock is
        generic (
 
                width : integer := 32;
                blocksize : integer := 512;
                widthadmemblock : integer :=9;
                external_writeable_blocks : integer := 12;
                external_readable_blocks  : integer := 8;
                external_readable_widthad       : integer := 3;
                external_writeable_widthad      : integer := 4
        );
        port (
 
                clk,rst,dpfifo_rd,normfifo_rd,dpfifo_wr,normfifo_wr : in std_logic;
                instrfifo_rd,instrfifo_wr,resultfifo_wr: in std_logic;
                instrfifo_empty: out std_logic;
                ext_rd,ext_wr: in std_logic;
                ext_wr_add : in std_logic_vector(external_writeable_widthad+widthadmemblock-1 downto 0);
                ext_rd_add : in std_logic_vector(external_readable_widthad-1 downto 0);
                ext_d: in std_logic_vector(width-1 downto 0);
                resultfifo_full,resultfifo_empty : out std_logic_vector(external_readable_blocks-1 downto 0);
                int_d : in std_logic_vector(external_readable_blocks*width-1 downto 0);
                ext_q,instrfifo_q : out std_logic_vector(width-1 downto 0);
                int_q : out std_logic_vector(external_writeable_blocks*width-1 downto 0);
                int_rd_add : in std_logic_vector(2*widthadmemblock-1 downto 0);
                instrfifo_d : in std_logic_vector(width-1 downto 0);
                dpfifo_d : in std_logic_vector(width*2-1 downto 0);
                normfifo_d : in std_logic_vector(width*3-1 downto 0);
                dpfifo_q : out std_logic_vector(width*2-1 downto 0);
                normfifo_q : out std_logic_vector(width*3-1 downto 0)
        );
end memblock;
 
architecture memblock_arch of memblock is
 
        type    vectorblock12 is array (11 downto 0) of std_logic_vector(width-1 downto 0);
        type    vectorblock08 is array (07 downto 0) of std_logic_vector(width-1 downto 0);
        type    vectorblock02 is array (01 downto 0) of std_logic_vector(widthadmemblock-1 downto 0);
        constant rstMasterValue : std_logic := '0';
 
        component scfifo
        generic (
                add_ram_output_register :string;
                almost_full_value               :natural;
                allow_wrcycle_when_full :string;
                intended_device_family  :string;
                lpm_hint                                :string;
                lpm_numwords                    :natural;
                lpm_showahead                   :string;
                lpm_type                                :string;
                lpm_width                               :natural;
                lpm_widthu                              :natural;
                overflow_checking               :string;
                underflow_checking              :string;
                use_eab                                 :string
        );
        port(
                rdreq           : in std_logic;
                aclr            : in std_logic;
                empty           : out std_logic;
                clock           : in std_logic;
                q                       : out std_logic_vector(lpm_width-1 downto 0);
                wrreq           : in std_logic;
                data            : in std_logic_vector(lpm_width-1 downto 0);
                almost_full : out std_logic;
                full            : out std_logic
        );
        end component;
 
 
        component altsyncram
        generic (
                address_aclr_b                  : string;
                address_reg_b                   : string;
                clock_enable_input_a    : string;
                clock_enable_input_b    : string;
                clock_enable_output_b   : string;
                intended_device_family  : string;
                lpm_type                                : string;
                numwords_a                              : natural;
                numwords_b                              : natural;
                operation_mode                  : string;
                outdata_aclr_b                  : string;
                outdata_reg_b                   : string;
                power_up_uninitialized  : string;
                ram_block_type                  : string;
                rdcontrol_reg_b                 : string;
                read_during_write_mode_mixed_ports      : string;
                widthad_a                               : natural;
                widthad_b                               : natural;
                width_a                                 : natural;
                width_b                                 : natural;
                width_byteena_a                 : natural
        );
        port (
                wren_a          : in std_logic;
                clock0          : in std_logic;
                address_a       : in std_logic_vector(widthad_a-1 downto 0);
                address_b       : in std_logic_vector(widthad_b-1 downto 0);
                rden_b          : in std_logic;
                q_b                     : out std_logic_vector(width-1 downto 0);
                data_a          : in std_logic_vector(width-1 downto 0)
 
        );
        end component;
        signal s0ext_wr_add_one_hot : std_logic_vector(external_writeable_blocks-1+1 downto 0); --! La se &ntilde;al extra es para la escritura de la cola de instrucciones.
        signal s0ext_wr_add                     : std_logic_vector(external_writeable_widthad+widthadmemblock-1 downto 0);
        signal s0ext_rd_add                     : std_logic_vector(external_readable_widthad-1 downto 0);
        signal s0int_rd_add                     : std_logic_vector(widthadmemblock-1 downto 0);
        signal s0ext_wr,s0ext_rd        : std_logic;
        signal s0ext_d                          : std_logic_vector(width-1 downto 0);
        signal s0ext_rd_ack                     : std_logic_vector(external_readable_blocks-1 downto 0);
        signal s0ext_q,sint_d           : vectorblock08;
        signal sint_rd_add                      : vectorblock02;
        signal s1int_q                          : vectorblock12;
 
begin
 
        --! Cola interna de producto punto, ubicada entre el pipe line aritm&eacute;co. 
        q0q1 : scfifo --! Debe ir registrada la salida.
        generic map (
                add_ram_output_register => "OFF",
                allow_wrcycle_when_full => "OFF",
                intended_device_family  => "CycloneIII",
                lpm_hint                                => "RAM_BLOCK_TYPE=M9K",
                almost_full_value               => 8,
                lpm_numwords                    => 8,
                lpm_showahead                   => "ON",
                lpm_type                                => "SCIFIFO",
                lpm_width                               => 64,
                lpm_widthu                              => 3,
                overflow_checking               => "ON",
                underflow_checking              => "ON",
                use_eab                                 => "ON"
        )
        port    map (
                rdreq           => dpfifo_rd,
                aclr            => '0',
                empty           => open,
                clock           => clk,
                q                       => dpfifo_q,
                wrreq           => dpfifo_wr,
                data            => dpfifo_d
        );
 
        --! Cola interna de normalizaci&oacute;n de vectores, ubicada entre el pipeline aritm&eacute
        qxqyqz : scfifo
        generic map (
                add_ram_output_register => "OFF",
                allow_wrcycle_when_full => "OFF",
                intended_device_family  => "Cyclone III",
                lpm_hint                => "RAM_BLOCK_TYPE=M9K",
                almost_full_value               => 32,
                lpm_numwords                    => 32,
                lpm_showahead                   => "ON",
                lpm_type                                => "SCFIFO",
                lpm_width                               => 96,
                lpm_widthu                              => 5,
                overflow_checking               => "ON",
                underflow_checking              => "ON",
                use_eab                                 => "ON"
        )
        port    map (
                rdreq           => normfifo_rd,
                aclr            => '0',
                empty           => open,
                clock           => clk,
                q                       => normfifo_q,
                wrreq           => normfifo_wr,
                data            => normfifo_d,
                almost_full => open,
                full            => open
        );
 
        --! Cola de instrucciones 
        qi : scfifo
        generic map (
                add_ram_output_register => "OFF",
                allow_wrcycle_when_full => "OFF",
                intended_device_family  => "Cyclone III",
                lpm_hint                                => "RAM_BLOCK_TYPE=M9K",
                almost_full_value               => 32,
                lpm_numwords                    => 32,
                lpm_showahead                   => "OFF",
                lpm_type                                => "SCIFIFO",
                lpm_width                               => 32,
                lpm_widthu                              => 5,
                overflow_checking               => "ON",
                underflow_checking              => "ON",
                use_eab                                 => "ON"
        )
        port    map (
                rdreq           => instrfifo_rd,
                aclr            => '0',
                empty           => instrfifo_empty,
                clock           => clk,
                q                       => instrfifo_q,
                wrreq           => instrfifo_wr,
                data            => instrfifo_d,
                almost_full => open
        );
 
        --! Conectar los registros de lectura interna del bloque de operandos a los arreglos > abstracci&oacute:n de c&oacute;digo, no influye en la sintesis del circuito.
        sint_rd_add (0)<= int_rd_add(widthadmemblock-1 downto 0);
        sint_rd_add (1)<= int_rd_add(2*widthadmemblock-1 downto widthadmemblock);
 
        --! Instanciaci&oacute;n de la cola de resultados de salida.
        operands_blocks:
        for i in 11 downto 0 generate
                int_q((i+1)*width-1 downto width*i) <= s1int_q(i);
                operandsblock : altsyncram
                generic map (
                        address_aclr_b                                          => "NONE",
                        address_reg_b                                           => "CLOCK0",
                        clock_enable_input_a                            => "BYPASS",
                        clock_enable_input_b                            => "BYPASS",
                        clock_enable_output_b                           => "BYPASS",
                        intended_device_family                          => "Cyclone III",
                        lpm_type                                                        => "altsyncram",
                        numwords_a                                                      => 2**widthadmemblock,
                        numwords_b                                                      => 2**widthadmemblock,
                        operation_mode                                          => "DUAL_PORT",
                        outdata_aclr_b                                          => "NONE",
                        outdata_reg_b                                           => "CLOCK0",
                        power_up_uninitialized                          => "FALSE",
                        ram_block_type                                          => "M9K",
                        rdcontrol_reg_b                                         => "CLOCK0",
                        read_during_write_mode_mixed_ports      => "OLD_DATA",
                        widthad_a                                                       => widthadmemblock,
                        widthad_b                                                       => widthadmemblock,
                        width_a                                                         => width,
                        width_b                                                         => width,
                        width_byteena_a                                         => 1
                )
                port map (
                        wren_a          => s0ext_wr_add_one_hot(i),
                        clock0          => clk,
                        address_a       => s0ext_wr_add(widthadmemblock-1 downto 0),
                        address_b       => sint_rd_add((i/3) mod 2),
                        rden_b          => '1',
                        q_b                     => s1int_q(i),
                        data_a          => s0ext_d
                );
        end generate operands_blocks;
 
        --! Instanciaci&oacute;n de la cola de resultados.
        results_blocks:
        for i in 7 downto 0 generate
                sint_d(i) <= int_d((i+1)*width-1 downto i*width);
                resultsfifo : scfifo
                generic map     (
                        add_ram_output_register => "OFF",
                        almost_full_value               => 480,
                        allow_wrcycle_when_full => "OFF",
                        intended_device_family  => "Cyclone III",
                        lpm_hint                                => "RAM_BLOCK_TYPE=M9K",
                        lpm_numwords                    => 512,
                        lpm_showahead                   => "ON",
                        lpm_type                                => "SCIFIFO",
                        lpm_width                               => 32,
                        lpm_widthu                              => 9,
                        overflow_checking               => "ON",
                        underflow_checking              => "ON",
                        use_eab                                 => "ON"
                )
                port    map (
                        rdreq           => s0ext_rd_ack(i),
                        aclr            => '0',
                        empty           => resultfifo_empty(i),
                        clock           => clk,
                        q                       => s0ext_q(i),
                        wrreq           => resultfifo_wr,
                        data            => sint_d(i),
                        almost_full     => resultfifo_full(i),
                        full            => open
                );
        end generate results_blocks;
 
        --! Escritura en registros de operandos de entrada.
        operands_block_proc: process (clk,rst)
        begin
                if rst=rstMasterValue then
                        s0ext_wr_add    <= (others => '0');
                        s0ext_wr                <= '0';
                        s0ext_d                 <= (others => '0');
                elsif clk'event and clk='1' then
                        --! Registro de entrada
                        s0ext_wr_add <= ext_wr_add;
                        s0ext_wr  <= ext_wr;
                        s0ext_d  <= ext_d;
                end if;
        end process;
 
        --! Decodificaci&oacute;n de se&ntilde;al escritura x bloque de memoria, selecciona la memoria en la que se va a escribir a partir de la direcci&oacute;n de entrada.
        operands_block_comb: process (s0ext_wr_add,s0ext_wr)
        begin
 
                --! Etapa 0: Decodificacion de las se&ntilde:ales de escritura.Revisar el capitulo de bloques de memoria para chequear como est&aacute; el pool de direcciones por bloques de vectores.
                --! Las direcciones de bloque 3,7,11,15 corresponden a la cola de instrucciones.
                case s0ext_wr_add(external_writeable_widthad+widthadmemblock-1 downto widthadmemblock) is
                        when x"0" => s0ext_wr_add_one_hot <= '0'&x"00"&"000"&s0ext_wr;
                        when x"1" => s0ext_wr_add_one_hot <= '0'&x"00"&"00"&s0ext_wr&'0';
                        when x"2" => s0ext_wr_add_one_hot <= '0'&x"00"&'0'&s0ext_wr&"00";
                        when x"4" => s0ext_wr_add_one_hot <= '0'&x"00"&s0ext_wr&"000";
                        when x"5" => s0ext_wr_add_one_hot <= '0'&x"0"&"000"&s0ext_wr&x"0";
                        when x"6" => s0ext_wr_add_one_hot <= '0'&x"0"&"00"&s0ext_wr&'0'&x"0";
                        when x"8" => s0ext_wr_add_one_hot <= '0'&x"0"&'0'&s0ext_wr&"00"&x"0";
                        when x"9" => s0ext_wr_add_one_hot <= '0'&x"0"&s0ext_wr&"000"&x"0";
                        when x"A" => s0ext_wr_add_one_hot <= '0'&"000"&s0ext_wr&x"00";
                        when x"C" => s0ext_wr_add_one_hot <= '0'&"00"&s0ext_wr&'0'&x"00";
                        when x"D" => s0ext_wr_add_one_hot <= '0'&'0'&s0ext_wr&"00"&x"00";
                        when x"E" => s0ext_wr_add_one_hot <= '0'&s0ext_wr&"000"&x"00";
                        when others => s0ext_wr_add_one_hot <= '1'&x"000";
                end case;
 
        end process;
 
        --! Decodificaci&oacute;n para seleccionar que cola de resultados se conectar&acute; a la salida del RayTrac. 
        results_block_proc: process(clk,rst)
        begin
                if rst=rstMasterValue then
                        s0ext_rd_add    <= (others => '0');
                        s0ext_rd                <= '0';
                elsif clk'event and clk='1' then
                        --!Registrar entrada
                        s0ext_rd_add    <= ext_rd_add;
                        s0ext_rd                <= ext_rd;
                        --!Etapa 0: Decodificar la cola que se va a mover (rdack! fifo showahead mode) y por ende leer ese dato.
                        case '0'&s0ext_rd_add is
                                when x"0" => ext_q <= s0ext_q(0);
                                when x"1" => ext_q <= s0ext_q(1);
                                when x"2" => ext_q <= s0ext_q(2);
                                when x"3" => ext_q <= s0ext_q(3);
                                when x"4" => ext_q <= s0ext_q(4);
                                when x"5" => ext_q <= s0ext_q(5);
                                when x"6" => ext_q <= s0ext_q(6);
                                when others => ext_q <= s0ext_q(7);
                        end case;
                end if;
        end process;
 
        --! rdack decoder para las colas de resultados de salida.
        results_block_proc_combinatorial_stage: process(s0ext_rd,s0ext_rd_add)
        begin
                case '0'&s0ext_rd_add is
                        when x"0" => s0ext_rd_ack <= x"0"&"000"&s0ext_rd;
                        when x"1" => s0ext_rd_ack <= x"0"&"00"&s0ext_rd&'0';
                        when x"2" => s0ext_rd_ack <= x"0"&"0"&s0ext_rd&"00";
                        when x"3" => s0ext_rd_ack <= x"0"&s0ext_rd&"000";
                        when x"4" => s0ext_rd_ack <= "000"&s0ext_rd&x"0";
                        when x"5" => s0ext_rd_ack <= "00"&s0ext_rd&'0'&x"0";
                        when x"6" => s0ext_rd_ack <= "0"&s0ext_rd&"00"&x"0";
                        when others => s0ext_rd_ack <= s0ext_rd&"000"&x"0";
                end case;
        end process;
end memblock_arch;
 

Line No.	Rev	Author	Line
1	139	jguarin200	`--! @file memblock.vhd`
2	128	jguarin200	`--! @brief Bloque de memoria.`
3			`--! @author Julián Andrés Guarín Reyes`
4			`--------------------------------------------------------------`
5			`-- RAYTRAC`
6			`-- Author Julian Andres Guarin`
7			`-- memblock.vhd`
8			`-- This file is part of raytrac.`
9			`--`
10			`-- raytrac is free software: you can redistribute it and/or modify`
11			`-- it under the terms of the GNU General Public License as published by`
12			`-- the Free Software Foundation, either version 3 of the License, or`
13			`-- (at your option) any later version.`
14			`--`
15			`-- raytrac is distributed in the hope that it will be useful,`
16			`-- but WITHOUT ANY WARRANTY; without even the implied warranty of`
17			`-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
18			`-- GNU General Public License for more details.`
19			`--`
20			`-- You should have received a copy of the GNU General Public License`
21			`-- along with raytrac. If not, see <http://www.gnu.org/licenses/>.`
22
23			`library ieee;`
24			`use ieee.std_logic_1164.all;`
25	129	jguarin200
26	128	jguarin200	`entity memblock is`
27			`generic (`
28	129	jguarin200
29			`width : integer := 32;`
30			`blocksize : integer := 512;`
31	143	jguarin200	`widthadmemblock : integer :=9;`
32	129	jguarin200	`external_writeable_blocks : integer := 12;`
33			`external_readable_blocks : integer := 8;`
34			`external_readable_widthad : integer := 3;`
35			`external_writeable_widthad : integer := 4`
36	128	jguarin200	`);`
37			`port (`
38
39	147	jguarin200	`clk,rst,dpfifo_rd,normfifo_rd,dpfifo_wr,normfifo_wr : in std_logic;`
40			`instrfifo_rd,instrfifo_wr,resultfifo_wr: in std_logic;`
41			`instrfifo_empty: out std_logic;`
42	138	jguarin200	`ext_rd,ext_wr: in std_logic;`
43	129	jguarin200	`ext_wr_add : in std_logic_vector(external_writeable_widthad+widthadmemblock-1 downto 0);`
44	138	jguarin200	`ext_rd_add : in std_logic_vector(external_readable_widthad-1 downto 0);`
45	129	jguarin200	`ext_d: in std_logic_vector(width-1 downto 0);`
46	147	jguarin200	`resultfifo_full,resultfifo_empty : out std_logic_vector(external_readable_blocks-1 downto 0);`
47	129	jguarin200	`int_d : in std_logic_vector(external_readable_blocks*width-1 downto 0);`
48	138	jguarin200	`ext_q,instrfifo_q : out std_logic_vector(width-1 downto 0);`
49	129	jguarin200	`int_q : out std_logic_vector(external_writeable_blocks*width-1 downto 0);`
50	130	jguarin200	`int_rd_add : in std_logic_vector(2*widthadmemblock-1 downto 0);`
51	133	jguarin200	`instrfifo_d : in std_logic_vector(width-1 downto 0);`
52	129	jguarin200	`dpfifo_d : in std_logic_vector(width*2-1 downto 0);`
53			`normfifo_d : in std_logic_vector(width*3-1 downto 0);`
54			`dpfifo_q : out std_logic_vector(width*2-1 downto 0);`
55			`normfifo_q : out std_logic_vector(width*3-1 downto 0)`
56	128	jguarin200	`);`
57			`end memblock;`
58
59			`architecture memblock_arch of memblock is`
60
61	130	jguarin200	`type vectorblock12 is array (11 downto 0) of std_logic_vector(width-1 downto 0);`
62			`type vectorblock08 is array (07 downto 0) of std_logic_vector(width-1 downto 0);`
63			`type vectorblock02 is array (01 downto 0) of std_logic_vector(widthadmemblock-1 downto 0);`
64	147	jguarin200	`constant rstMasterValue : std_logic := '0';`
65	129	jguarin200
66	128	jguarin200	`component scfifo`
67			`generic (`
68			`add_ram_output_register :string;`
69	138	jguarin200	`almost_full_value :natural;`
70			`allow_wrcycle_when_full :string;`
71	128	jguarin200	`intended_device_family :string;`
72			`lpm_hint :string;`
73			`lpm_numwords :natural;`
74			`lpm_showahead :string;`
75			`lpm_type :string;`
76			`lpm_width :natural;`
77			`lpm_widthu :natural;`
78			`overflow_checking :string;`
79			`underflow_checking :string;`
80			`use_eab :string`
81			`);`
82			`port(`
83	138	jguarin200	`rdreq : in std_logic;`
84			`aclr : in std_logic;`
85			`empty : out std_logic;`
86			`clock : in std_logic;`
87			`q : out std_logic_vector(lpm_width-1 downto 0);`
88			`wrreq : in std_logic;`
89			`data : in std_logic_vector(lpm_width-1 downto 0);`
90			`almost_full : out std_logic;`
91			`full : out std_logic`
92	128	jguarin200	`);`
93			`end component;`
94	129	jguarin200
95	147	jguarin200
96	129	jguarin200	`component altsyncram`
97			`generic (`
98			`address_aclr_b : string;`
99			`address_reg_b : string;`
100			`clock_enable_input_a : string;`
101			`clock_enable_input_b : string;`
102			`clock_enable_output_b : string;`
103			`intended_device_family : string;`
104			`lpm_type : string;`
105			`numwords_a : natural;`
106			`numwords_b : natural;`
107			`operation_mode : string;`
108			`outdata_aclr_b : string;`
109			`outdata_reg_b : string;`
110			`power_up_uninitialized : string;`
111			`ram_block_type : string;`
112			`rdcontrol_reg_b : string;`
113			`read_during_write_mode_mixed_ports : string;`
114			`widthad_a : natural;`
115			`widthad_b : natural;`
116			`width_a : natural;`
117			`width_b : natural;`
118			`width_byteena_a : natural`
119			`);`
120			`port (`
121			`wren_a : in std_logic;`
122			`clock0 : in std_logic;`
123			`address_a : in std_logic_vector(widthad_a-1 downto 0);`
124			`address_b : in std_logic_vector(widthad_b-1 downto 0);`
125			`rden_b : in std_logic;`
126			`q_b : out std_logic_vector(width-1 downto 0);`
127			`data_a : in std_logic_vector(width-1 downto 0)`
128
129			`);`
130			`end component;`
131	140	jguarin200	`signal s0ext_wr_add_one_hot : std_logic_vector(external_writeable_blocks-1+1 downto 0); --! La se ñal extra es para la escritura de la cola de instrucciones.`
132	129	jguarin200	`signal s0ext_wr_add : std_logic_vector(external_writeable_widthad+widthadmemblock-1 downto 0);`
133	130	jguarin200	`signal s0ext_rd_add : std_logic_vector(external_readable_widthad-1 downto 0);`
134	129	jguarin200	`signal s0int_rd_add : std_logic_vector(widthadmemblock-1 downto 0);`
135	138	jguarin200	`signal s0ext_wr,s0ext_rd : std_logic;`
136	130	jguarin200	`signal s0ext_d : std_logic_vector(width-1 downto 0);`
137	138	jguarin200	`signal s0ext_rd_ack : std_logic_vector(external_readable_blocks-1 downto 0);`
138			`signal s0ext_q,sint_d : vectorblock08;`
139	130	jguarin200	`signal sint_rd_add : vectorblock02;`
140	138	jguarin200	`signal s1int_q : vectorblock12;`
141	130	jguarin200
142	128	jguarin200	`begin`
143
144	140	jguarin200	`--! Cola interna de producto punto, ubicada entre el pipe line aritméco.`
145			`q0q1 : scfifo --! Debe ir registrada la salida.`
146	147	jguarin200	`generic map (`
147			`add_ram_output_register => "OFF",`
148			`allow_wrcycle_when_full => "OFF",`
149			`intended_device_family => "CycloneIII",`
150			`lpm_hint => "RAM_BLOCK_TYPE=M9K",`
151			`almost_full_value => 8,`
152			`lpm_numwords => 8,`
153			`lpm_showahead => "ON",`
154			`lpm_type => "SCIFIFO",`
155			`lpm_width => 64,`
156			`lpm_widthu => 3,`
157			`overflow_checking => "ON",`
158			`underflow_checking => "ON",`
159			`use_eab => "ON"`
160			`)`
161			`port map (`
162			`rdreq => dpfifo_rd,`
163			`aclr => '0',`
164			`empty => open,`
165			`clock => clk,`
166			`q => dpfifo_q,`
167			`wrreq => dpfifo_wr,`
168			`data => dpfifo_d`
169			`);`
170	140	jguarin200
171			`--! Cola interna de normalización de vectores, ubicada entre el pipeline aritm&eacute`
172			`qxqyqz : scfifo`
173	147	jguarin200	`generic map (`
174			`add_ram_output_register => "OFF",`
175			`allow_wrcycle_when_full => "OFF",`
176			`intended_device_family => "Cyclone III",`
177			`lpm_hint => "RAM_BLOCK_TYPE=M9K",`
178			`almost_full_value => 32,`
179			`lpm_numwords => 32,`
180			`lpm_showahead => "ON",`
181			`lpm_type => "SCFIFO",`
182			`lpm_width => 96,`
183			`lpm_widthu => 5,`
184			`overflow_checking => "ON",`
185			`underflow_checking => "ON",`
186			`use_eab => "ON"`
187			`)`
188			`port map (`
189			`rdreq => normfifo_rd,`
190			`aclr => '0',`
191			`empty => open,`
192			`clock => clk,`
193			`q => normfifo_q,`
194			`wrreq => normfifo_wr,`
195			`data => normfifo_d,`
196			`almost_full => open,`
197			`full => open`
198			`);`
199	140	jguarin200
200			`--! Cola de instrucciones`
201			`qi : scfifo`
202	147	jguarin200	`generic map (`
203			`add_ram_output_register => "OFF",`
204			`allow_wrcycle_when_full => "OFF",`
205			`intended_device_family => "Cyclone III",`
206			`lpm_hint => "RAM_BLOCK_TYPE=M9K",`
207			`almost_full_value => 32,`
208			`lpm_numwords => 32,`
209			`lpm_showahead => "OFF",`
210			`lpm_type => "SCIFIFO",`
211			`lpm_width => 32,`
212			`lpm_widthu => 5,`
213			`overflow_checking => "ON",`
214			`underflow_checking => "ON",`
215			`use_eab => "ON"`
216			`)`
217			`port map (`
218			`rdreq => instrfifo_rd,`
219			`aclr => '0',`
220			`empty => instrfifo_empty,`
221			`clock => clk,`
222			`q => instrfifo_q,`
223			`wrreq => instrfifo_wr,`
224			`data => instrfifo_d,`
225			`almost_full => open`
226			`);`
227	128	jguarin200
228	140	jguarin200	`--! Conectar los registros de lectura interna del bloque de operandos a los arreglos > abstracci&oacute:n de código, no influye en la sintesis del circuito.`
229	130	jguarin200	`sint_rd_add (0)<= int_rd_add(widthadmemblock-1 downto 0);`
230			`sint_rd_add (1)<= int_rd_add(2*widthadmemblock-1 downto widthadmemblock);`
231
232	147	jguarin200	`--! Instanciación de la cola de resultados de salida.`
233			`operands_blocks:`
234			`for i in 11 downto 0 generate`
235			`int_q((i+1)width-1 downto widthi) <= s1int_q(i);`
236			`operandsblock : altsyncram`
237			`generic map (`
238			`address_aclr_b => "NONE",`
239			`address_reg_b => "CLOCK0",`
240			`clock_enable_input_a => "BYPASS",`
241			`clock_enable_input_b => "BYPASS",`
242			`clock_enable_output_b => "BYPASS",`
243			`intended_device_family => "Cyclone III",`
244			`lpm_type => "altsyncram",`
245			`numwords_a => 2**widthadmemblock,`
246			`numwords_b => 2**widthadmemblock,`
247			`operation_mode => "DUAL_PORT",`
248			`outdata_aclr_b => "NONE",`
249			`outdata_reg_b => "CLOCK0",`
250			`power_up_uninitialized => "FALSE",`
251			`ram_block_type => "M9K",`
252			`rdcontrol_reg_b => "CLOCK0",`
253			`read_during_write_mode_mixed_ports => "OLD_DATA",`
254			`widthad_a => widthadmemblock,`
255			`widthad_b => widthadmemblock,`
256			`width_a => width,`
257			`width_b => width,`
258			`width_byteena_a => 1`
259			`)`
260			`port map (`
261			`wren_a => s0ext_wr_add_one_hot(i),`
262			`clock0 => clk,`
263			`address_a => s0ext_wr_add(widthadmemblock-1 downto 0),`
264			`address_b => sint_rd_add((i/3) mod 2),`
265			`rden_b => '1',`
266			`q_b => s1int_q(i),`
267			`data_a => s0ext_d`
268			`);`
269			`end generate operands_blocks;`
270
271	140	jguarin200	`--! Instanciación de la cola de resultados.`
272	130	jguarin200	`results_blocks:`
273			`for i in 7 downto 0 generate`
274			`sint_d(i) <= int_d((i+1)width-1 downto iwidth);`
275	138	jguarin200	`resultsfifo : scfifo`
276	147	jguarin200	`generic map (`
277			`add_ram_output_register => "OFF",`
278			`almost_full_value => 480,`
279			`allow_wrcycle_when_full => "OFF",`
280			`intended_device_family => "Cyclone III",`
281			`lpm_hint => "RAM_BLOCK_TYPE=M9K",`
282			`lpm_numwords => 512,`
283			`lpm_showahead => "ON",`
284			`lpm_type => "SCIFIFO",`
285			`lpm_width => 32,`
286			`lpm_widthu => 9,`
287			`overflow_checking => "ON",`
288			`underflow_checking => "ON",`
289			`use_eab => "ON"`
290			`)`
291			`port map (`
292			`rdreq => s0ext_rd_ack(i),`
293			`aclr => '0',`
294			`empty => resultfifo_empty(i),`
295			`clock => clk,`
296			`q => s0ext_q(i),`
297			`wrreq => resultfifo_wr,`
298			`data => sint_d(i),`
299			`almost_full => resultfifo_full(i),`
300			`full => open`
301			`);`
302	130	jguarin200	`end generate results_blocks;`
303
304	140	jguarin200	`--! Escritura en registros de operandos de entrada.`
305	147	jguarin200	`operands_block_proc: process (clk,rst)`
306	129	jguarin200	`begin`
307	147	jguarin200	`if rst=rstMasterValue then`
308			`s0ext_wr_add <= (others => '0');`
309			`s0ext_wr <= '0';`
310			`s0ext_d <= (others => '0');`
311			`elsif clk'event and clk='1' then`
312			`--! Registro de entrada`
313			`s0ext_wr_add <= ext_wr_add;`
314			`s0ext_wr <= ext_wr;`
315			`s0ext_d <= ext_d;`
316	129	jguarin200	`end if;`
317			`end process;`
318	140	jguarin200
319			`--! Decodificación de señal escritura x bloque de memoria, selecciona la memoria en la que se va a escribir a partir de la dirección de entrada.`
320	138	jguarin200	`operands_block_comb: process (s0ext_wr_add,s0ext_wr)`
321	130	jguarin200	`begin`
322	138	jguarin200
323	140	jguarin200	`--! Etapa 0: Decodificacion de las se&ntilde:ales de escritura.Revisar el capitulo de bloques de memoria para chequear como está el pool de direcciones por bloques de vectores.`
324	141	jguarin200	`--! Las direcciones de bloque 3,7,11,15 corresponden a la cola de instrucciones.`
325	138	jguarin200	`case s0ext_wr_add(external_writeable_widthad+widthadmemblock-1 downto widthadmemblock) is`
326	140	jguarin200	`when x"0" => s0ext_wr_add_one_hot <= '0'&x"00"&"000"&s0ext_wr;`
327			`when x"1" => s0ext_wr_add_one_hot <= '0'&x"00"&"00"&s0ext_wr&'0';`
328			`when x"2" => s0ext_wr_add_one_hot <= '0'&x"00"&'0'&s0ext_wr&"00";`
329			`when x"4" => s0ext_wr_add_one_hot <= '0'&x"00"&s0ext_wr&"000";`
330			`when x"5" => s0ext_wr_add_one_hot <= '0'&x"0"&"000"&s0ext_wr&x"0";`
331			`when x"6" => s0ext_wr_add_one_hot <= '0'&x"0"&"00"&s0ext_wr&'0'&x"0";`
332			`when x"8" => s0ext_wr_add_one_hot <= '0'&x"0"&'0'&s0ext_wr&"00"&x"0";`
333			`when x"9" => s0ext_wr_add_one_hot <= '0'&x"0"&s0ext_wr&"000"&x"0";`
334			`when x"A" => s0ext_wr_add_one_hot <= '0'&"000"&s0ext_wr&x"00";`
335			`when x"C" => s0ext_wr_add_one_hot <= '0'&"00"&s0ext_wr&'0'&x"00";`
336			`when x"D" => s0ext_wr_add_one_hot <= '0'&'0'&s0ext_wr&"00"&x"00";`
337			`when x"E" => s0ext_wr_add_one_hot <= '0'&s0ext_wr&"000"&x"00";`
338			`when others => s0ext_wr_add_one_hot <= '1'&x"000";`
339	138	jguarin200	`end case;`
340
341			`end process;`
342	140	jguarin200
343			`--! Decodificación para seleccionar que cola de resultados se conectar´ a la salida del RayTrac.`
344	147	jguarin200	`results_block_proc: process(clk,rst)`
345	138	jguarin200	`begin`
346	147	jguarin200	`if rst=rstMasterValue then`
347			`s0ext_rd_add <= (others => '0');`
348			`s0ext_rd <= '0';`
349			`elsif clk'event and clk='1' then`
350	130	jguarin200	`--!Registrar entrada`
351	138	jguarin200	`s0ext_rd_add <= ext_rd_add;`
352			`s0ext_rd <= ext_rd;`
353			`--!Etapa 0: Decodificar la cola que se va a mover (rdack! fifo showahead mode) y por ende leer ese dato.`
354			`case '0'&s0ext_rd_add is`
355			`when x"0" => ext_q <= s0ext_q(0);`
356			`when x"1" => ext_q <= s0ext_q(1);`
357			`when x"2" => ext_q <= s0ext_q(2);`
358			`when x"3" => ext_q <= s0ext_q(3);`
359			`when x"4" => ext_q <= s0ext_q(4);`
360			`when x"5" => ext_q <= s0ext_q(5);`
361			`when x"6" => ext_q <= s0ext_q(6);`
362			`when others => ext_q <= s0ext_q(7);`
363	130	jguarin200	`end case;`
364			`end if;`
365			`end process;`
366	140	jguarin200
367			`--! rdack decoder para las colas de resultados de salida.`
368	138	jguarin200	`results_block_proc_combinatorial_stage: process(s0ext_rd,s0ext_rd_add)`
369			`begin`
370			`case '0'&s0ext_rd_add is`
371			`when x"0" => s0ext_rd_ack <= x"0"&"000"&s0ext_rd;`
372			`when x"1" => s0ext_rd_ack <= x"0"&"00"&s0ext_rd&'0';`
373			`when x"2" => s0ext_rd_ack <= x"0"&"0"&s0ext_rd&"00";`
374			`when x"3" => s0ext_rd_ack <= x"0"&s0ext_rd&"000";`
375			`when x"4" => s0ext_rd_ack <= "000"&s0ext_rd&x"0";`
376			`when x"5" => s0ext_rd_ack <= "00"&s0ext_rd&'0'&x"0";`
377			`when x"6" => s0ext_rd_ack <= "0"&s0ext_rd&"00"&x"0";`
378			`when others => s0ext_rd_ack <= s0ext_rd&"000"&x"0";`
379			`end case;`
380			`end process;`
381	128	jguarin200	`end memblock_arch;`
382

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