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--! @file memblock.vhd
--! @brief Bloque de memoria.
--! @author Juli&aacute;n Andr&eacute;s Guar&iacute;n Reyes
--------------------------------------------------------------
-- RAYTRAC
-- Author Julian Andres Guarin
-- memblock.vhd
-- This file is part of raytrac.
-- 
--     raytrac is free software: you can redistribute it and/or modify
--     it under the terms of the GNU General Public License as published by
--     the Free Software Foundation, either version 3 of the License, or
--     (at your option) any later version.
-- 
--     raytrac is distributed in the hope that it will be useful,
--     but WITHOUT ANY WARRANTY; without even the implied warranty of
--     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--     GNU General Public License for more details.
-- 
--     You should have received a copy of the GNU General Public License
--     along with raytrac.  If not, see <http://www.gnu.org/licenses/>.
 
library ieee;
use ieee.std_logic_1164.all;
use work.arithpack.all;
 
entity memblock is
        generic (
 
                blocksize : integer := 512;
 
                external_readable_widthad       : integer := 3;
                external_writeable_widthad      : integer := 4
        );
        port (
 
                clk,rst,dpfifo_rd,normfifo_rd,dpfifo_wr,normfifo_wr : in std_logic;
                instrfifo_rd : in std_logic;
                resultfifo_wr: in std_logic_vector(8-1 downto 0);
                instrfifo_empty: out std_logic;
                ext_rd,ext_wr: in std_logic;
                ext_wr_add : in std_logic_vector(4+widthadmemblock-1 downto 0);
                ext_rd_add : in std_logic_vector(2 downto 0);
                ext_d: in std_logic_vector(floatwidth-1 downto 0);
                resultfifo_full  : out std_logic_vector(3 downto 0);
                int_d : in vectorblock08;
 
                --!Python
                ext_q,instrfifo_q : out std_logic_vector(floatwidth-1 downto 0);
                int_q : out vectorblock12;
                int_rd_add : in std_logic_vector(2*widthadmemblock-1 downto 0);
                dpfifo_d : in std_logic_vector(floatwidth*2-1 downto 0);
                normfifo_d : in std_logic_vector(floatwidth*3-1 downto 0);
                dpfifo_q : out std_logic_vector(floatwidth*2-1 downto 0);
                normfifo_q : out std_logic_vector(floatwidth*3-1 downto 0)
        );
end entity;
 
architecture memblock_arch of memblock is
 
 
 
 
 
        --!TBXSTART:MEMBLOCK_EXTERNAL_WRITE
        signal s0ext_wr_add_one_hot : std_logic_vector(12-1+1 downto 0); --! La se&ntilde;al extra es para la escritura de la cola de instrucciones.
        signal s0ext_wr_add                     : std_logic_vector(4+widthadmemblock-1 downto 0);
        signal s0ext_wr                         : std_logic;
        signal s0ext_d                          : std_logic_vector(floatwidth-1 downto 0);
        --!TBXEND
        --! Se&ntilde;al de soporte
        signal s0ext_wr_add_choice      : std_logic_vector(3 downto 0);
 
        --!TBXSTART:MEMBLOCK_EXTERNAL_READ
        signal s0ext_rd_add                     : std_logic_vector(2 downto 0);
        signal s0ext_rd                         : std_logic;
        signal s0ext_rd_ack                     : std_logic_vector(8-1 downto 0);
        signal s0ext_q                          : vectorblock08;
        --!TBXEND
        --! Se&ntilde;al de soporte
        signal s0ext_rd_add_choice      : std_logic_vector(3 downto 0);
 
 
        --!TBXSTART:MEMBLOCK_INTERNAL_READ
        signal s0int_rd_add                     : std_logic_vector(widthadmemblock-1 downto 0);
        signal sint_rd_add                      : vectorblockadd02;
        signal s1int_q                          : vectorblock12;
        --!TBXEND
 
        --!TBXSTART:MEMBLOCK_INTERNAL_WRITE
        signal sint_d                           : vectorblock08;
        signal sresultfifo_full         : std_logic_vector(7 downto 0);
        --!TBXEND
 
begin
 
        --! Cola interna de producto cccccpunto, ubicada entre el pipe line aritm&eacute;co. 
        q0q1 : scfifo --! Debe ir registrada la salida.
        generic map (
                add_ram_output_register => "OFF",
                allow_rwcycle_when_full => "OFF",
                intended_device_family  => "CycloneIII",
                lpm_hint                                => "RAM_BLOCK_TYPE=M9K",
                almost_full_value               => 8,
                lpm_numwords                    => 8,
                lpm_showahead                   => "ON",
                lpm_type                                => "SCIFIFO",
                lpm_width                               => 64,
                lpm_widthu                              => 3,
                overflow_checking               => "ON",
                underflow_checking              => "ON",
                use_eab                                 => "ON"
        )
        port    map (
                rdreq           => dpfifo_rd,
                aclr            => '0',
                empty           => open,
                clock           => clk,
                q                       => dpfifo_q,
                wrreq           => dpfifo_wr,
                data            => dpfifo_d
        );
 
        --! Cola interna de normalizaci&oacute;n de vectores, ubicada entre el pipeline aritm&eacute;tico
        qxqyqz : scfifo
        generic map (
                add_ram_output_register => "OFF",
                allow_rwcycle_when_full => "OFF",
                intended_device_family  => "Cyclone III",
                lpm_hint                => "RAM_BLOCK_TYPE=M9K",
                almost_full_value               => 32,
                lpm_numwords                    => 32,
                lpm_showahead                   => "ON",
                lpm_type                                => "SCFIFO",
                lpm_width                               => 96,
                lpm_widthu                              => 5,
                overflow_checking               => "ON",
                underflow_checking              => "ON",
                use_eab                                 => "ON"
        )
        port    map (
                rdreq           => normfifo_rd,
                aclr            => '0',
                empty           => open,
                clock           => clk,
                q                       => normfifo_q,
                wrreq           => normfifo_wr,
                data            => normfifo_d,
                almost_full => open,
                full            => open
        );
 
        --! Cola de instrucciones 
        qi : scfifo
        generic map (
                add_ram_output_register => "OFF",
                allow_rwcycle_when_full => "OFF",
                intended_device_family  => "Cyclone III",
                lpm_hint                                => "RAM_BLOCK_TYPE=M9K",
                almost_full_value               => 32,
                lpm_numwords                    => 32,
                lpm_showahead                   => "OFF",
                lpm_type                                => "SCIFIFO",
                lpm_width                               => 32,
                lpm_widthu                              => 5,
                overflow_checking               => "ON",
                underflow_checking              => "ON",
                use_eab                                 => "ON"
        )
        port    map (
                rdreq           => instrfifo_rd,
                aclr            => '0',
                empty           => instrfifo_empty,
                clock           => clk,
                q                       => instrfifo_q,
                wrreq           => s0ext_wr_add_one_hot(12),
                data            => s0ext_d,
                almost_full => open
        );
 
        --! Conectar los registros de lectura interna del bloque de operandos a los arreglos > abstracci&oacute:n de c&oacute;digo, no influye en la sintesis del circuito.
        sint_rd_add (0)<= int_rd_add(widthadmemblock-1 downto 0);
        sint_rd_add (1)<= int_rd_add(2*widthadmemblock-1 downto widthadmemblock);
 
        --! Instanciaci&oacute;n de la cola de resultados de salida.
        int_q <= s1int_q;
        operands_blocks:
        for i in 11 downto 0 generate
                --!int_q((i+1)*floatwidth-1 downto floatwidth*i) <= s1int_q(i);
                operandsblock : altsyncram
                generic map (
                        address_aclr_b                                          => "NONE",
                        address_reg_b                                           => "CLOCK0",
                        clock_enable_input_a                            => "BYPASS",
                        clock_enable_input_b                            => "BYPASS",
                        clock_enable_output_b                           => "BYPASS",
                        intended_device_family                          => "Cyclone III",
                        lpm_type                                                        => "altsyncram",
                        numwords_a                                                      => 2**widthadmemblock,
                        numwords_b                                                      => 2**widthadmemblock,
                        operation_mode                                          => "DUAL_PORT",
                        outdata_aclr_b                                          => "NONE",
                        outdata_reg_b                                           => "CLOCK0",
                        power_up_uninitialized                          => "FALSE",
                        ram_block_type                                          => "M9K",
                        rdcontrol_reg_b                                         => "CLOCK0",
                        read_during_write_mode_mixed_ports      => "OLD_DATA",
                        widthad_a                                                       => widthadmemblock,
                        widthad_b                                                       => widthadmemblock,
                        width_a                                                         => floatwidth,
                        width_b                                                         => floatwidth,
                        width_byteena_a                                         => 1
                )
                port map (
                        wren_a          => s0ext_wr_add_one_hot(i),
                        clock0          => clk,
                        address_a       => s0ext_wr_add(widthadmemblock-1 downto 0),
                        address_b       => sint_rd_add((i/3) mod 2),
                        rden_b          => '1',
                        q_b                     => s1int_q(i),
                        data_a          => s0ext_d
                );
        end generate operands_blocks;
 
        --! Instanciaci&oacute;n de la cola de resultados.
        resultfifo_full(3) <= sresultfifo_full(7) or sresultfifo_full(6) or sresultfifo_full(5);
        resultfifo_full(2) <= sresultfifo_full(4) or sresultfifo_full(2);
        resultfifo_full(1) <= sresultfifo_full(3) or sresultfifo_full(2) or sresultfifo_full(1);
        resultfifo_full(0) <= sresultfifo_full(0);
        sint_d <= int_d;
        results_blocks:
        for i in 7 downto 0 generate
                resultsfifo : scfifo
                generic map     (
                        add_ram_output_register => "OFF",
                        almost_full_value               => 480,
                        allow_rwcycle_when_full => "OFF",
                        intended_device_family  => "Cyclone III",
                        lpm_hint                                => "RAM_BLOCK_TYPE=M9K",
                        lpm_numwords                    => 512,
                        lpm_showahead                   => "ON",
                        lpm_type                                => "SCIFIFO",
                        lpm_width                               => 32,
                        lpm_widthu                              => 9,
                        overflow_checking               => "ON",
                        underflow_checking              => "ON",
                        use_eab                                 => "ON"
                )
                port    map (
                        rdreq           => s0ext_rd_ack(i),
                        aclr            => '0',
                        empty           => open,
                        clock           => clk,
                        q                       => s0ext_q(i),
                        wrreq           => resultfifo_wr(i),
                        data            => sint_d(i),
                        almost_full     => sresultfifo_full(i),
                        full            => open
                );
        end generate results_blocks;
 
        --! Escritura en registros de operandos de entrada.
        operands_block_proc: process (clk,rst)
        begin
                if rst=rstMasterValue then
                        s0ext_wr_add    <= (others => '0');
                        s0ext_wr                <= '0';
                        s0ext_d                 <= (others => '0');
                elsif clk'event and clk='1' then
                        --! Registro de entrada
                        s0ext_wr_add <= ext_wr_add;
                        s0ext_wr  <= ext_wr;
                        s0ext_d  <= ext_d;
                end if;
        end process;
 
        --! Decodificaci&oacute;n de se&ntilde;al escritura x bloque de memoria, selecciona la memoria en la que se va a escribir a partir de la direcci&oacute;n de entrada.
        s0ext_wr_add_choice <= s0ext_wr_add(4+widthadmemblock-1 downto widthadmemblock);
        operands_block_comb: process (s0ext_wr_add_choice,s0ext_wr)
        begin
 
                --! Etapa 0: Decodificacion de las se&ntilde:ales de escritura.Revisar el capitulo de bloques de memoria para chequear como est&aacute; el pool de direcciones por bloques de vectores.
                --! Las direcciones de bloque 3,7,11,15 corresponden a la cola de instrucciones.
                case s0ext_wr_add_choice is
                        when "0000" =>
                                s0ext_wr_add_one_hot <= '0'&x"00"&"000"&s0ext_wr;
                        when x"1" =>
                                s0ext_wr_add_one_hot <= '0'&x"00"&"00"&s0ext_wr&'0';
                        when x"2" =>
                                s0ext_wr_add_one_hot <= '0'&x"00"&'0'&s0ext_wr&"00";
                        when x"4" =>
                                s0ext_wr_add_one_hot <= '0'&x"00"&s0ext_wr&"000";
                        when x"5" =>
                                s0ext_wr_add_one_hot <= '0'&x"0"&"000"&s0ext_wr&x"0";
                        when x"6" =>
                                s0ext_wr_add_one_hot <= '0'&x"0"&"00"&s0ext_wr&'0'&x"0";
                        when x"8" =>
                                s0ext_wr_add_one_hot <= '0'&x"0"&'0'&s0ext_wr&"00"&x"0";
                        when x"9" =>
                                s0ext_wr_add_one_hot <= '0'&x"0"&s0ext_wr&"000"&x"0";
                        when x"A" =>
                                s0ext_wr_add_one_hot <= '0'&"000"&s0ext_wr&x"00";
                        when x"C" =>
                                s0ext_wr_add_one_hot <= '0'&"00"&s0ext_wr&'0'&x"00";
                        when x"D" =>
                                s0ext_wr_add_one_hot <= '0'&'0'&s0ext_wr&"00"&x"00";
                        when x"E" =>
                                s0ext_wr_add_one_hot <= '0'&s0ext_wr&"000"&x"00";
                        when others =>
                                s0ext_wr_add_one_hot <= s0ext_wr&x"000";
                end case;
 
        end process;
 
        --! Decodificaci&oacute;n para seleccionar que cola de resultados se conectar&acute; a la salida del RayTrac. 
        s0ext_rd_add_choice <= '0'&s0ext_rd_add;
        results_block_proc: process(clk,rst)
        begin
                if rst=rstMasterValue then
                        s0ext_rd_add    <= (others => '0');
                        s0ext_rd                <= '0';
                elsif clk'event and clk='1' then
                        --!Registrar entrada
                        s0ext_rd_add    <= ext_rd_add;
                        s0ext_rd                <= ext_rd;
                        --!Etapa 0: Decodificar la cola que se va a mover (rdack! fifo showahead mode) y por ende leer ese dato.
                        case s0ext_rd_add_choice is
                                when x"0" => ext_q <= s0ext_q(0);
                                when x"1" => ext_q <= s0ext_q(1);
                                when x"2" => ext_q <= s0ext_q(2);
                                when x"3" => ext_q <= s0ext_q(3);
                                when x"4" => ext_q <= s0ext_q(4);
                                when x"5" => ext_q <= s0ext_q(5);
                                when x"6" => ext_q <= s0ext_q(6);
                                when others => ext_q <= s0ext_q(7);
                        end case;
                end if;
        end process;
 
        --! rdack decoder para las colas de resultados de salida.
        results_block_proc_combinatorial_stage: process(s0ext_rd,s0ext_rd_add_choice)
        begin
                case s0ext_rd_add_choice is
                        when x"0" => s0ext_rd_ack <= x"0"&"000"&s0ext_rd;
                        when x"1" => s0ext_rd_ack <= x"0"&"00"&s0ext_rd&'0';
                        when x"2" => s0ext_rd_ack <= x"0"&"0"&s0ext_rd&"00";
                        when x"3" => s0ext_rd_ack <= x"0"&s0ext_rd&"000";
                        when x"4" => s0ext_rd_ack <= "000"&s0ext_rd&x"0";
                        when x"5" => s0ext_rd_ack <= "00"&s0ext_rd&'0'&x"0";
                        when x"6" => s0ext_rd_ack <= "0"&s0ext_rd&"00"&x"0";
                        when others => s0ext_rd_ack <= s0ext_rd&"000"&x"0";
                end case;
        end process;
end architecture;
 

Line No.	Rev	Author	Line
1	150	jguarin200	`--! @file memblock.vhd`
2	152	jguarin200	`--! @brief Bloque de memoria.`
3	128	jguarin200	`--! @author Julián Andrés Guarín Reyes`
4			`--------------------------------------------------------------`
5			`-- RAYTRAC`
6			`-- Author Julian Andres Guarin`
7			`-- memblock.vhd`
8			`-- This file is part of raytrac.`
9			`--`
10			`-- raytrac is free software: you can redistribute it and/or modify`
11			`-- it under the terms of the GNU General Public License as published by`
12			`-- the Free Software Foundation, either version 3 of the License, or`
13			`-- (at your option) any later version.`
14			`--`
15			`-- raytrac is distributed in the hope that it will be useful,`
16			`-- but WITHOUT ANY WARRANTY; without even the implied warranty of`
17			`-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
18			`-- GNU General Public License for more details.`
19			`--`
20			`-- You should have received a copy of the GNU General Public License`
21			`-- along with raytrac. If not, see <http://www.gnu.org/licenses/>.`
22
23			`library ieee;`
24			`use ieee.std_logic_1164.all;`
25	151	jguarin200	`use work.arithpack.all;`
26	129	jguarin200
27	128	jguarin200	`entity memblock is`
28			`generic (`
29	129	jguarin200
30			`blocksize : integer := 512;`
31	152	jguarin200
32	129	jguarin200	`external_readable_widthad : integer := 3;`
33			`external_writeable_widthad : integer := 4`
34	128	jguarin200	`);`
35			`port (`
36
37	147	jguarin200	`clk,rst,dpfifo_rd,normfifo_rd,dpfifo_wr,normfifo_wr : in std_logic;`
38	150	jguarin200	`instrfifo_rd : in std_logic;`
39	158	jguarin200	`resultfifo_wr: in std_logic_vector(8-1 downto 0);`
40	147	jguarin200	`instrfifo_empty: out std_logic;`
41	138	jguarin200	`ext_rd,ext_wr: in std_logic;`
42	158	jguarin200	`ext_wr_add : in std_logic_vector(4+widthadmemblock-1 downto 0);`
43	157	jguarin200	`ext_rd_add : in std_logic_vector(2 downto 0);`
44	152	jguarin200	`ext_d: in std_logic_vector(floatwidth-1 downto 0);`
45	150	jguarin200	`resultfifo_full : out std_logic_vector(3 downto 0);`
46	158	jguarin200	`int_d : in vectorblock08;`
47	152	jguarin200
48			`--!Python`
49	153	jguarin200	`ext_q,instrfifo_q : out std_logic_vector(floatwidth-1 downto 0);`
50	158	jguarin200	`int_q : out vectorblock12;`
51	130	jguarin200	`int_rd_add : in std_logic_vector(2*widthadmemblock-1 downto 0);`
52	152	jguarin200	`dpfifo_d : in std_logic_vector(floatwidth*2-1 downto 0);`
53			`normfifo_d : in std_logic_vector(floatwidth*3-1 downto 0);`
54			`dpfifo_q : out std_logic_vector(floatwidth*2-1 downto 0);`
55			`normfifo_q : out std_logic_vector(floatwidth*3-1 downto 0)`
56	128	jguarin200	`);`
57	153	jguarin200	`end entity;`
58	128	jguarin200
59			`architecture memblock_arch of memblock is`
60
61	129	jguarin200
62
63	147	jguarin200
64	151	jguarin200
65	152	jguarin200	`--!TBXSTART:MEMBLOCK_EXTERNAL_WRITE`
66	158	jguarin200	`signal s0ext_wr_add_one_hot : std_logic_vector(12-1+1 downto 0); --! La señal extra es para la escritura de la cola de instrucciones.`
67			`signal s0ext_wr_add : std_logic_vector(4+widthadmemblock-1 downto 0);`
68	152	jguarin200	`signal s0ext_wr : std_logic;`
69			`signal s0ext_d : std_logic_vector(floatwidth-1 downto 0);`
70			`--!TBXEND`
71	157	jguarin200	`--! Señal de soporte`
72			`signal s0ext_wr_add_choice : std_logic_vector(3 downto 0);`
73	152	jguarin200
74			`--!TBXSTART:MEMBLOCK_EXTERNAL_READ`
75	157	jguarin200	`signal s0ext_rd_add : std_logic_vector(2 downto 0);`
76	152	jguarin200	`signal s0ext_rd : std_logic;`
77	158	jguarin200	`signal s0ext_rd_ack : std_logic_vector(8-1 downto 0);`
78	152	jguarin200	`signal s0ext_q : vectorblock08;`
79			`--!TBXEND`
80	157	jguarin200	`--! Señal de soporte`
81			`signal s0ext_rd_add_choice : std_logic_vector(3 downto 0);`
82	152	jguarin200
83	157	jguarin200
84	152	jguarin200	`--!TBXSTART:MEMBLOCK_INTERNAL_READ`
85	129	jguarin200	`signal s0int_rd_add : std_logic_vector(widthadmemblock-1 downto 0);`
86	152	jguarin200	`signal sint_rd_add : vectorblockadd02;`
87	138	jguarin200	`signal s1int_q : vectorblock12;`
88	152	jguarin200	`--!TBXEND`
89
90			`--!TBXSTART:MEMBLOCK_INTERNAL_WRITE`
91			`signal sint_d : vectorblock08;`
92	150	jguarin200	`signal sresultfifo_full : std_logic_vector(7 downto 0);`
93	152	jguarin200	`--!TBXEND`
94	130	jguarin200
95	128	jguarin200	`begin`
96
97	152	jguarin200	`--! Cola interna de producto cccccpunto, ubicada entre el pipe line aritméco.`
98	140	jguarin200	`q0q1 : scfifo --! Debe ir registrada la salida.`
99	147	jguarin200	`generic map (`
100			`add_ram_output_register => "OFF",`
101	159	jguarin200	`allow_rwcycle_when_full => "OFF",`
102	147	jguarin200	`intended_device_family => "CycloneIII",`
103			`lpm_hint => "RAM_BLOCK_TYPE=M9K",`
104			`almost_full_value => 8,`
105			`lpm_numwords => 8,`
106			`lpm_showahead => "ON",`
107			`lpm_type => "SCIFIFO",`
108			`lpm_width => 64,`
109			`lpm_widthu => 3,`
110			`overflow_checking => "ON",`
111			`underflow_checking => "ON",`
112			`use_eab => "ON"`
113			`)`
114			`port map (`
115			`rdreq => dpfifo_rd,`
116			`aclr => '0',`
117			`empty => open,`
118			`clock => clk,`
119			`q => dpfifo_q,`
120			`wrreq => dpfifo_wr,`
121			`data => dpfifo_d`
122			`);`
123	140	jguarin200
124	152	jguarin200	`--! Cola interna de normalización de vectores, ubicada entre el pipeline aritmético`
125	140	jguarin200	`qxqyqz : scfifo`
126	147	jguarin200	`generic map (`
127			`add_ram_output_register => "OFF",`
128	159	jguarin200	`allow_rwcycle_when_full => "OFF",`
129	147	jguarin200	`intended_device_family => "Cyclone III",`
130			`lpm_hint => "RAM_BLOCK_TYPE=M9K",`
131			`almost_full_value => 32,`
132			`lpm_numwords => 32,`
133			`lpm_showahead => "ON",`
134			`lpm_type => "SCFIFO",`
135			`lpm_width => 96,`
136			`lpm_widthu => 5,`
137			`overflow_checking => "ON",`
138			`underflow_checking => "ON",`
139			`use_eab => "ON"`
140			`)`
141			`port map (`
142			`rdreq => normfifo_rd,`
143			`aclr => '0',`
144			`empty => open,`
145			`clock => clk,`
146			`q => normfifo_q,`
147			`wrreq => normfifo_wr,`
148			`data => normfifo_d,`
149			`almost_full => open,`
150			`full => open`
151			`);`
152	140	jguarin200
153			`--! Cola de instrucciones`
154			`qi : scfifo`
155	147	jguarin200	`generic map (`
156			`add_ram_output_register => "OFF",`
157	159	jguarin200	`allow_rwcycle_when_full => "OFF",`
158	147	jguarin200	`intended_device_family => "Cyclone III",`
159			`lpm_hint => "RAM_BLOCK_TYPE=M9K",`
160			`almost_full_value => 32,`
161			`lpm_numwords => 32,`
162			`lpm_showahead => "OFF",`
163			`lpm_type => "SCIFIFO",`
164			`lpm_width => 32,`
165			`lpm_widthu => 5,`
166			`overflow_checking => "ON",`
167			`underflow_checking => "ON",`
168			`use_eab => "ON"`
169			`)`
170			`port map (`
171			`rdreq => instrfifo_rd,`
172			`aclr => '0',`
173			`empty => instrfifo_empty,`
174			`clock => clk,`
175			`q => instrfifo_q,`
176	150	jguarin200	`wrreq => s0ext_wr_add_one_hot(12),`
177			`data => s0ext_d,`
178	147	jguarin200	`almost_full => open`
179			`);`
180	128	jguarin200
181	140	jguarin200	`--! Conectar los registros de lectura interna del bloque de operandos a los arreglos > abstracci&oacute:n de código, no influye en la sintesis del circuito.`
182	130	jguarin200	`sint_rd_add (0)<= int_rd_add(widthadmemblock-1 downto 0);`
183			`sint_rd_add (1)<= int_rd_add(2*widthadmemblock-1 downto widthadmemblock);`
184
185	147	jguarin200	`--! Instanciación de la cola de resultados de salida.`
186	158	jguarin200	`int_q <= s1int_q;`
187	147	jguarin200	`operands_blocks:`
188			`for i in 11 downto 0 generate`
189	158	jguarin200	`--!int_q((i+1)floatwidth-1 downto floatwidthi) <= s1int_q(i);`
190	147	jguarin200	`operandsblock : altsyncram`
191			`generic map (`
192			`address_aclr_b => "NONE",`
193			`address_reg_b => "CLOCK0",`
194			`clock_enable_input_a => "BYPASS",`
195			`clock_enable_input_b => "BYPASS",`
196			`clock_enable_output_b => "BYPASS",`
197			`intended_device_family => "Cyclone III",`
198			`lpm_type => "altsyncram",`
199			`numwords_a => 2**widthadmemblock,`
200			`numwords_b => 2**widthadmemblock,`
201			`operation_mode => "DUAL_PORT",`
202			`outdata_aclr_b => "NONE",`
203			`outdata_reg_b => "CLOCK0",`
204			`power_up_uninitialized => "FALSE",`
205			`ram_block_type => "M9K",`
206			`rdcontrol_reg_b => "CLOCK0",`
207			`read_during_write_mode_mixed_ports => "OLD_DATA",`
208			`widthad_a => widthadmemblock,`
209			`widthad_b => widthadmemblock,`
210	152	jguarin200	`width_a => floatwidth,`
211			`width_b => floatwidth,`
212	147	jguarin200	`width_byteena_a => 1`
213			`)`
214			`port map (`
215			`wren_a => s0ext_wr_add_one_hot(i),`
216			`clock0 => clk,`
217			`address_a => s0ext_wr_add(widthadmemblock-1 downto 0),`
218			`address_b => sint_rd_add((i/3) mod 2),`
219			`rden_b => '1',`
220			`q_b => s1int_q(i),`
221			`data_a => s0ext_d`
222			`);`
223			`end generate operands_blocks;`
224
225	140	jguarin200	`--! Instanciación de la cola de resultados.`
226	150	jguarin200	`resultfifo_full(3) <= sresultfifo_full(7) or sresultfifo_full(6) or sresultfifo_full(5);`
227			`resultfifo_full(2) <= sresultfifo_full(4) or sresultfifo_full(2);`
228			`resultfifo_full(1) <= sresultfifo_full(3) or sresultfifo_full(2) or sresultfifo_full(1);`
229			`resultfifo_full(0) <= sresultfifo_full(0);`
230	158	jguarin200	`sint_d <= int_d;`
231	130	jguarin200	`results_blocks:`
232			`for i in 7 downto 0 generate`
233	138	jguarin200	`resultsfifo : scfifo`
234	147	jguarin200	`generic map (`
235			`add_ram_output_register => "OFF",`
236			`almost_full_value => 480,`
237	159	jguarin200	`allow_rwcycle_when_full => "OFF",`
238	147	jguarin200	`intended_device_family => "Cyclone III",`
239			`lpm_hint => "RAM_BLOCK_TYPE=M9K",`
240			`lpm_numwords => 512,`
241			`lpm_showahead => "ON",`
242			`lpm_type => "SCIFIFO",`
243			`lpm_width => 32,`
244			`lpm_widthu => 9,`
245			`overflow_checking => "ON",`
246			`underflow_checking => "ON",`
247			`use_eab => "ON"`
248			`)`
249			`port map (`
250			`rdreq => s0ext_rd_ack(i),`
251			`aclr => '0',`
252	150	jguarin200	`empty => open,`
253	147	jguarin200	`clock => clk,`
254			`q => s0ext_q(i),`
255	150	jguarin200	`wrreq => resultfifo_wr(i),`
256	147	jguarin200	`data => sint_d(i),`
257	150	jguarin200	`almost_full => sresultfifo_full(i),`
258	147	jguarin200	`full => open`
259			`);`
260	130	jguarin200	`end generate results_blocks;`
261
262	140	jguarin200	`--! Escritura en registros de operandos de entrada.`
263	147	jguarin200	`operands_block_proc: process (clk,rst)`
264	129	jguarin200	`begin`
265	147	jguarin200	`if rst=rstMasterValue then`
266			`s0ext_wr_add <= (others => '0');`
267			`s0ext_wr <= '0';`
268			`s0ext_d <= (others => '0');`
269			`elsif clk'event and clk='1' then`
270			`--! Registro de entrada`
271			`s0ext_wr_add <= ext_wr_add;`
272			`s0ext_wr <= ext_wr;`
273			`s0ext_d <= ext_d;`
274	129	jguarin200	`end if;`
275			`end process;`
276	140	jguarin200
277			`--! Decodificación de señal escritura x bloque de memoria, selecciona la memoria en la que se va a escribir a partir de la dirección de entrada.`
278	158	jguarin200	`s0ext_wr_add_choice <= s0ext_wr_add(4+widthadmemblock-1 downto widthadmemblock);`
279	157	jguarin200	`operands_block_comb: process (s0ext_wr_add_choice,s0ext_wr)`
280	130	jguarin200	`begin`
281	138	jguarin200
282	140	jguarin200	`--! Etapa 0: Decodificacion de las se&ntilde:ales de escritura.Revisar el capitulo de bloques de memoria para chequear como está el pool de direcciones por bloques de vectores.`
283	141	jguarin200	`--! Las direcciones de bloque 3,7,11,15 corresponden a la cola de instrucciones.`
284	157	jguarin200	`case s0ext_wr_add_choice is`
285			`when "0000" =>`
286			`s0ext_wr_add_one_hot <= '0'&x"00"&"000"&s0ext_wr;`
287			`when x"1" =>`
288			`s0ext_wr_add_one_hot <= '0'&x"00"&"00"&s0ext_wr&'0';`
289			`when x"2" =>`
290			`s0ext_wr_add_one_hot <= '0'&x"00"&'0'&s0ext_wr&"00";`
291			`when x"4" =>`
292			`s0ext_wr_add_one_hot <= '0'&x"00"&s0ext_wr&"000";`
293			`when x"5" =>`
294			`s0ext_wr_add_one_hot <= '0'&x"0"&"000"&s0ext_wr&x"0";`
295			`when x"6" =>`
296			`s0ext_wr_add_one_hot <= '0'&x"0"&"00"&s0ext_wr&'0'&x"0";`
297			`when x"8" =>`
298			`s0ext_wr_add_one_hot <= '0'&x"0"&'0'&s0ext_wr&"00"&x"0";`
299			`when x"9" =>`
300			`s0ext_wr_add_one_hot <= '0'&x"0"&s0ext_wr&"000"&x"0";`
301			`when x"A" =>`
302			`s0ext_wr_add_one_hot <= '0'&"000"&s0ext_wr&x"00";`
303			`when x"C" =>`
304			`s0ext_wr_add_one_hot <= '0'&"00"&s0ext_wr&'0'&x"00";`
305			`when x"D" =>`
306			`s0ext_wr_add_one_hot <= '0'&'0'&s0ext_wr&"00"&x"00";`
307			`when x"E" =>`
308			`s0ext_wr_add_one_hot <= '0'&s0ext_wr&"000"&x"00";`
309			`when others =>`
310			`s0ext_wr_add_one_hot <= s0ext_wr&x"000";`
311	138	jguarin200	`end case;`
312
313			`end process;`
314	140	jguarin200
315			`--! Decodificación para seleccionar que cola de resultados se conectar´ a la salida del RayTrac.`
316	157	jguarin200	`s0ext_rd_add_choice <= '0'&s0ext_rd_add;`
317	147	jguarin200	`results_block_proc: process(clk,rst)`
318	138	jguarin200	`begin`
319	147	jguarin200	`if rst=rstMasterValue then`
320			`s0ext_rd_add <= (others => '0');`
321			`s0ext_rd <= '0';`
322			`elsif clk'event and clk='1' then`
323	130	jguarin200	`--!Registrar entrada`
324	138	jguarin200	`s0ext_rd_add <= ext_rd_add;`
325			`s0ext_rd <= ext_rd;`
326			`--!Etapa 0: Decodificar la cola que se va a mover (rdack! fifo showahead mode) y por ende leer ese dato.`
327	157	jguarin200	`case s0ext_rd_add_choice is`
328	138	jguarin200	`when x"0" => ext_q <= s0ext_q(0);`
329			`when x"1" => ext_q <= s0ext_q(1);`
330			`when x"2" => ext_q <= s0ext_q(2);`
331			`when x"3" => ext_q <= s0ext_q(3);`
332			`when x"4" => ext_q <= s0ext_q(4);`
333			`when x"5" => ext_q <= s0ext_q(5);`
334			`when x"6" => ext_q <= s0ext_q(6);`
335			`when others => ext_q <= s0ext_q(7);`
336	130	jguarin200	`end case;`
337			`end if;`
338			`end process;`
339	140	jguarin200
340			`--! rdack decoder para las colas de resultados de salida.`
341	157	jguarin200	`results_block_proc_combinatorial_stage: process(s0ext_rd,s0ext_rd_add_choice)`
342	138	jguarin200	`begin`
343	157	jguarin200	`case s0ext_rd_add_choice is`
344	138	jguarin200	`when x"0" => s0ext_rd_ack <= x"0"&"000"&s0ext_rd;`
345			`when x"1" => s0ext_rd_ack <= x"0"&"00"&s0ext_rd&'0';`
346			`when x"2" => s0ext_rd_ack <= x"0"&"0"&s0ext_rd&"00";`
347			`when x"3" => s0ext_rd_ack <= x"0"&s0ext_rd&"000";`
348			`when x"4" => s0ext_rd_ack <= "000"&s0ext_rd&x"0";`
349			`when x"5" => s0ext_rd_ack <= "00"&s0ext_rd&'0'&x"0";`
350			`when x"6" => s0ext_rd_ack <= "0"&s0ext_rd&"00"&x"0";`
351			`when others => s0ext_rd_ack <= s0ext_rd&"000"&x"0";`
352			`end case;`
353			`end process;`
354	153	jguarin200	`end architecture;`
355	128	jguarin200

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