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--! @file raytrac.vhd
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--! @brief Archivo con el RTL que describe al RayTrac en su totalidad.
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--! @author Julián Andrés Guarín Reyes
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--------------------------------------------------------------
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-- RAYTRAC
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-- Author Julian Andres Guarin
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-- Rytrac.vhd
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-- This file is part of raytrac.
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-- 
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--     raytrac is free software: you can redistribute it and/or modify
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--     it under the terms of the GNU General Public License as published by
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--     the Free Software Foundation, either version 3 of the License, or
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--     (at your option) any later version.
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-- 
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--     raytrac is distributed in the hope that it will be useful,
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--     but WITHOUT ANY WARRANTY; without even the implied warranty of
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--     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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--     GNU General Public License for more details.
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-- 
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--     You should have received a copy of the GNU General Public License
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--     along with raytrac.  If not, see <http://www.gnu.org/licenses/>.
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library ieee;
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use ieee.std_logic_1164.all;
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use work.arithpack.all;
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entity raytrac is
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        port (
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                clk : in std_logic;
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                rst : in std_logic;
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                --! Se&ntilde;al de lectura de alguna de las colas de resultados.
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                rd      : in std_logic;
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                --! Se&ntilde;al de escritura en alguno de los bloques de memoria de operandos o en la cola de instrucciones.
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                wr      : in std_logic;
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                --! Direccion de escritura o lectura
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                add : in std_logic_vector (12 downto 0);
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                --! datos de entrada
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                d       : in std_logic_vector (31 downto 0);
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                --! Interrupciones
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                irq : out std_logic;
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                --! Salidas
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                q : out std_logic_vector (31 downto 0)
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        );
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end entity;
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architecture raytrac_arch of raytrac is
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        --! Se&ntilde;ales de State Machine -> Memblock
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        --!TBXSTART:SM
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        signal s_int_rd_add             : std_logic_vector (17 downto 0);
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        signal s_adda                   : std_logic_vector (8 downto 0);
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        signal s_addb                   : std_logic_vector (8 downto 0);
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        signal s_iq_rd_ack              : std_logic;
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        --! Se&ntilde;ales de State Machine -> DataPathControl
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        signal s_sync_chain_0   : std_logic;
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        signal s_dpc_uca                : std_logic_vector(2 downto 0);
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        signal s_eoi                    : std_logic;
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        signal s_sign                   : std_logic;
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        --!TBXEND
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        --! Se&ntilde;ales de State Machine -> Testbench
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        signal s_smState                : macState;
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        --!TBXSTART:MBLK
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        --! Se&ntilde;ales de Memblock -> State Machine
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        signal s_iq_empty               : std_logic;
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        signal s_iq                             : std_logic_vector (31 downto 0);
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        --! Se&ntilde;ales de Memblock -> Interruption Machine
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        signal s_rfull_events   : std_logic_vector (3 downto 0); --Estas se&ntilde;ales tambien entran a DPC.
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        --! Se&ntilde;ales de Memblock -> DPC.
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        signal s_q                              : vectorblock12;
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        signal s_normfifo_q             : std_logic_vector (3*32-1 downto 0);
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        signal s_dpfifo_q               : std_logic_vector (2*32-1 downto 0);
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        --!TBXEND
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        --!TXBXSTART:SQR32
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        --!Se&ntilde;ales de Bloque de Ra&iacute;z Cuadrada a DPC
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        signal s_sq32                   : std_logic_vector (31 downto 0);
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        --!TBXEND
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        --!TXBXSTART:INV32
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        --!Se&ntilde;ales del bloque inversor a DPC.
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        signal s_qout32                 : std_logic_vector (31 downto 0);
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        --!TBXEND
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        --!TXBXSTART:DPC
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        --! Se&ntilde;ales de DataPathControl -> State Machine
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        signal s_full_r                 : std_logic;
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        --! Se&ntilde;ales de DPC a sqrt32.
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        signal s_rd32                   : std_logic_vector (31 downto 0);
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        --! Se&ntilde;ales de DPC a inv32.
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        signal s_dvd32                  : std_logic_vector (31 downto 0);
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        --! Se&ntilde;ales de DPC  a invr32.
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        --! Se&ntilde que va desde DPC -> Memblock
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        signal s_resultfifo_wr  : std_logic_vector (7 downto 0);
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        signal s_dpfifo_w               : std_logic;
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        signal s_dpfifo_r               : std_logic;
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        signal s_dpfifo_d               : std_logic_vector (2*32-1 downto 0);
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        signal s_normfifo_w             : std_logic;
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        signal s_normfifo_r             : std_logic;
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        signal s_results_d              : vectorblock08;
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        signal s_normfifo_d             : std_logic_vector (3*32-1 downto 0);
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        --!Se&ntilde;ales de DPC a Interruption Machine
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        signal s_eoi_events             : std_logic_vector (3 downto 0);
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        --! Se&ntilde;ales de DPC a ArithBlock
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        signal s_f                              : vectorblock12;
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        signal s_a                              : vectorblock08;
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        --! Parcialmente las se&ntilde;ales de salida de los sumadores van al data path control.
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        signal s_s                              : vectorblock04;
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        signal s_p                              : vectorblock06;
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        --!TBXEND
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        signal s_resultsfifo_w  : std_logic_vector (4 downto 0);
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        --!TBXSTART:IM
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        --! Se&ntilde;ales de Interruption Machine al testbench
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        signal s_iCtrlState             : iCtrlState;
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        signal s_int                    : std_logic;
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        --!TBXEND       
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begin
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        --! Sacar las interrupciones
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        irq <= s_int;
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        --! Signo de los bloques de suma
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        s_sign <= not(s_dpc_uca(2)) and s_dpc_uca(1);
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        --! Instanciar el bloque de memorias MEMBLOCK
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        s_resultfifo_wr <= s_resultsfifo_w(4)&s_resultsfifo_w(4)&s_resultsfifo_w(4)&s_resultsfifo_w(3)&s_resultsfifo_w(2)&s_resultsfifo_w(1)&s_resultsfifo_w(2)&s_resultsfifo_w(0);
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        s_int_rd_add  <= s_addb&s_adda;
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        --!TBXINSTANCESTART
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        MemoryBlock : memblock
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        port map (
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                clk                                     => clk,
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                rst                                     => rst,
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                dpfifo_rd                       => s_dpfifo_r,
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                normfifo_rd                     => s_normfifo_r,
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                dpfifo_wr                       => s_dpfifo_w,
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                normfifo_wr                     => s_normfifo_w,
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                instrfifo_rd            => s_iq_rd_ack,
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                resultfifo_wr           => s_resultfifo_wr,
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                instrfifo_empty         => s_iq_empty,
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                ext_rd                          => rd,
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                ext_wr                          => wr,
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                ext_wr_add                      => add,
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                ext_rd_add                      => add(12 downto 9),
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                ext_d                           => d,
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                resultfifo_full         => s_rfull_events,
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                int_d                           => s_results_d,
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                status_register         => s_eoi_events,
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                ext_q                           => q,
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                instrfifo_q                     => s_iq,
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                int_q                           => s_q,
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                int_rd_add                      => s_int_rd_add,
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                dpfifo_d                        => s_dpfifo_d,
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                normfifo_d                      => s_normfifo_d,
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                dpfifo_q                        => s_dpfifo_q,
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                normfifo_q                      => s_normfifo_q
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        );
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        --!TBXINSTANCEEND
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        --! Instanciar el bloque DPC
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        --!TBXINSTANCESTART
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        DataPathControl_And_Syncronization_Block: dpc
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        port map (
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                clk                             => clk,
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                rst                             => rst,
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                paraminput              => s_q,
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                prd32blko               => s_p,
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                add32blko               => s_s,
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                sqr32blko               => s_sq32,
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                inv32blko               => s_qout32,
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                fifo32x23_q             => s_normfifo_q,
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                fifo32x09_q             => s_dpfifo_q,
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                unary                   => s_dpc_uca(2),
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                crossprod               => s_dpc_uca(1),
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                addsub                  => s_dpc_uca(0),
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                sync_chain_0    => s_sync_chain_0,
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                eoi_int                 => s_eoi,
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                eoi_demuxed_int => s_eoi_events,
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                sqr32blki               => s_rd32,
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                inv32blki               => s_dvd32,
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                fifo32x26_d             => s_normfifo_d,
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                fifo32x09_d             => s_dpfifo_d,
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                prd32blki               => s_f,
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                add32blki               => s_a,
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                resw                    => s_resultsfifo_w,
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                fifo32x09_w             => s_dpfifo_w,
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                fifo32x23_w             => s_normfifo_w,
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                fifo32x09_r             => s_dpfifo_r,
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                fifo32x23_r             => s_normfifo_r,
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                resf_vector             => s_rfull_events,
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                resf_event              => s_full_r,
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                resultoutput    => s_results_d
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        );
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        --!TBXINSTANCEEND
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        --! Instanciar el bloque de inversion
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        --!TBXINSTANCESTART
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        inversion_block : invr32
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        port map (
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                clk             => clk,
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                dvd32   => s_dvd32,
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                qout32  => s_qout32
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        );
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        --!TBXINSTANCEEND
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        --! Instanciar el bloque de ra&iacute;z cuadrada.
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        --!TBXINSTANCESTART
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        square_root : sqrt32
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        port map (
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                clk     => clk,
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                rd32    => s_rd32,
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                sq32    => s_sq32
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        );
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        --!TBXINSTANCEEND
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        --! Instanciar el bloque aritm&eacute;tico.
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        --!TBXINSTANCESTART
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        arithmetic_block : arithblock
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        port map (
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                clk => clk,
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                rst => rst,
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                dpc => s_sign,
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                f       => s_f,
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                a       => s_a,
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                s       => s_s,
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                p       => s_p
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        );
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        --!TBXINSTANCEEND
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        --! Instanciar la maquina de interrupciones
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        --!TBXINSTANCESTART
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        interruption_machine : im
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        generic map (
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                num_events              => 4,
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                cycles_to_wait  => 1023
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        )
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        port map (
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                clk                             => clk,
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                rst                             => rst,
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                rfull_event             => s_full_r,
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                eoi_event               => s_eoi,
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                int                             => s_int,
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                state                   => s_iCtrlState
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        );
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        --!TBXINSTANCEEND
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        --!Instanciar la maquina de estados
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        --!TBXINSTANCESTART
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        state_machine : sm
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        port map (
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                clk                     => clk,
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                rst                     => rst,
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                instrQq                 => s_iq,
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                instrQ_empty    => s_iq_empty,
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                adda                    => s_adda,
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                addb                    => s_addb,
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                sync_chain_0    => s_sync_chain_0,
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                instrRdAckd             => s_iq_rd_ack,
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                full_r                  => s_full_r,
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                eoi                             => s_eoi,
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                dpc_uca                 => s_dpc_uca,
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                state                   => s_smState
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        );
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        --!TBXINSTANCEEND
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end architecture;

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