OpenCores
URL https://opencores.org/ocsvn/raytrac/raytrac/trunk

Subversion Repositories raytrac

[/] [raytrac/] [branches/] [fp/] [sm.vhd] - Blame information for rev 134

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 134 jguarin200
--! @file sm.vhd
2
--! @brief Maquina de Estados. Controla la operación interna y genera los mecanismos de sincronización con el exterior (interrupciones). 
3
--! @author Julián Andrés Guarín Reyes
4
--------------------------------------------------------------
5
-- RAYTRAC
6
-- Author Julian Andres Guarin
7
-- sm.vhd
8
-- This file is part of raytrac.
9
-- 
10
--     raytrac is free software: you can redistribute it and/or modify
11
--     it under the terms of the GNU General Public License as published by
12
--     the Free Software Foundation, either version 3 of the License, or
13
--     (at your option) any later version.
14
-- 
15
--     raytrac is distributed in the hope that it will be useful,
16
--     but WITHOUT ANY WARRANTY; without even the implied warranty of
17
--     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18
--     GNU General Public License for more details.
19
-- 
20
--     You should have received a copy of the GNU General Public License
21
--     along with raytrac.  If not, see <http://www.gnu.org/licenses/>.
22
 
23
 
24
library ieee;
25
use ieee.std_logic_1164.all;
26
 
27
 
28
 
29
entity sm is
30
        generic (
31
                width :integer:= 32;
32
                widthadmemblock : integer := 9
33
        );
34
        port (
35
 
36
                clk,rst: in std_logic;
37
                add_rd,add_wr:out std_logic_vector(widthadmemblock-1 downto 0);
38
                iempty,ifull:in std_logic_vector;
39
                rd,wr:out std_logic;
40
                irq:out std_logic
41
        );
42
end entity;
43
architecture sm_arch of arch is
44
begin
45
 
46
 
47
 
48
 
49
end architecture;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.