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--! @file arithblock.vhd
--! @brief Bloque Aritmético de 4 sumadores y 6 multiplicadores. 
--! @author Juli&aacute;n Andr&eacute;s Guar&iacute;n Reyes
--------------------------------------------------------------
-- RAYTRAC
-- Author Julian Andres Guarin
-- memblock.vhd
-- This file is part of raytrac.
-- 
--     raytrac is free software: you can redistribute it and/or modify
--     it under the terms of the GNU General Public License as published by
--     the Free Software Foundation, either version 3 of the License, or
--     (at your option) any later version.
-- 
--     raytrac is distributed in the hope that it will be useful,
--     but WITHOUT ANY WARRANTY; without even the implied warranty of
--     MERCHANTABILITY or FITNESS FOR a PARTICULAR PURPOSE.  See the
--     GNU General Public License for more details.
-- 
--     You should have received a copy of the GNU General Public License
--     along with raytrac.  If not, see <http://www.gnu.org/licenses/>.
 
 
library ieee;
use ieee.std_logic_1164.all;
use work.arithpack.all;
 
entity arithblock is
        port (
 
                clk     : in std_logic;
                rst : in std_logic;
 
                sign : in std_logic;
                sign_switch     : in std_logic;
 
                factor0         : in std_logic_vector(31 downto 0);
                factor1         : in std_logic_vector(31 downto 0);
                factor2         : in std_logic_vector(31 downto 0);
                factor3         : in std_logic_vector(31 downto 0);
                factor4         : in std_logic_vector(31 downto 0);
                factor5         : in std_logic_vector(31 downto 0);
                factor6         : in std_logic_vector(31 downto 0);
                factor7         : in std_logic_vector(31 downto 0);
                factor8         : in std_logic_vector(31 downto 0);
                factor9         : in std_logic_vector(31 downto 0);
                factor10        : in std_logic_vector(31 downto 0);
                factor11        : in std_logic_vector(31 downto 0);
                --factor        : in vectorblock06;
 
                sumando0        : in std_logic_vector(31 downto 0);
                sumando1        : in std_logic_vector(31 downto 0);
                sumando2        : in std_logic_vector(31 downto 0);
                sumando3        : in std_logic_vector(31 downto 0);
                sumando4        : in std_logic_vector(31 downto 0);
                sumando5        : in std_logic_vector(31 downto 0);
                --add32blki     : in vectorblock06;
 
                a0                      : out std_logic_vector(31 downto 0);
                a1                      : out std_logic_vector(31 downto 0);
                a2                      : out std_logic_vector(31 downto 0);
                --add32blko     : out vectorblock03;
 
                p0                      : out std_logic_vector(31 downto 0);
                p1                      : out std_logic_vector(31 downto 0);
                p2                      : out std_logic_vector(31 downto 0);
                p3                      : out std_logic_vector(31 downto 0);
                p4                      : out std_logic_vector(31 downto 0);
                p5                      : out std_logic_vector(31 downto 0);
                --p     : out vectorblock06;
 
                sq32o           : out std_logic_vector(31 downto 0);
                inv32o          : out std_logic_vector(31 downto 0)
 
 
 
        );
end entity;
 
architecture arithblock_arch of arithblock is
 
        signal sadd32blko_01 : std_logic_vector(31 downto 0);
        signal ssq32o : std_logic_vector(31 downto 0);
        signal ssigna1 : std_logic;
 
        --! Componentes Aritm&eacute;ticos
        component fadd32long
        port (
                clk : in std_logic;
                dpc : in std_logic;
                a32 : in std_logic_vector(31 downto 0);
                b32 : in std_logic_vector(31 downto 0);
                c32 : out std_logic_vector(31 downto 0)
        );
        end component;
        component fmul32
        port (
                clk : in std_logic;
                a32 : in std_logic_vector(31 downto 0);
                b32 : in std_logic_vector(31 downto 0);
                p32 : out std_logic_vector(31 downto 0)
        );
        end component;
        --! Bloque de Raiz Cuadrada
        component sqrt32
        port (
 
                clk     : in std_logic;
                rd32: in std_logic_vector(31 downto 0);
                sq32: out std_logic_vector(31 downto 0)
        );
        end component;
        --! Bloque de Inversores.
        component invr32
        port (
 
                clk             : in std_logic;
                dvd32   : in std_logic_vector(31 downto 0);
                qout32  : out std_logic_vector(31 downto 0)
        );
        end component;
 
 
begin
 
        sq32o <= ssq32o;
        a1 <= sadd32blko_01;
        ssigna1 <= sign_switch or sign;
 
        --!TBXINSTANCESTART
        adder_i_0 : fadd32long
        port map (
                clk => clk,
                dpc => sign,
                a32 => sumando0,
                b32 => sumando1,
                c32 => a0
        );
        --!TBXINSTANCESTART
        adder_i_1 : fadd32long
        port map (
                clk => clk,
                dpc => ssigna1,
                a32 => sumando2,
                b32 => sumando3,
                c32 => sadd32blko_01
        );
        --!TBXINSTANCESTART
        adder_i_2 : fadd32long
        port map (
                clk => clk,
                dpc => sign,
                a32 => sumando4,
                b32 => sumando5,
                c32 => a2
        );
        --!TBXINSTANCESTART
        mul_i_0 : fmul32
        port map (
                clk => clk,
                a32 => factor0,
                b32 => factor1,
                p32 => p0
        );
        --!TBXINSTANCESTART
        mul_i_1 : fmul32
        port map (
                clk => clk,
                a32 => factor2,
                b32 => factor3,
                p32 => p1
        );
        --!TBXINSTANCESTART
        mul_i_2 : fmul32
        port map (
                clk => clk,
                a32 => factor4,
                b32 => factor5,
                p32 => p2
        );
        --!TBXINSTANCESTART
        mul_i_3 : fmul32
        port map (
                clk => clk,
                a32 => factor6,
                b32 => factor7,
                p32 => p3
        );
        --!TBXINSTANCESTART
        mul_i_4 : fmul32
        port map (
                clk => clk,
                a32 => factor8,
                b32 => factor9,
                p32 => p4
        );
        --!TBXINSTANCESTART
        mul_i_5 : fmul32
        port map (
                clk => clk,
                a32 => factor10,
                b32 => factor11,
                p32 => p5
        );
        --!TBXINSTANCESTART
        square_root : sqrt32
        port map (
                clk     => clk,
                rd32    => sadd32blko_01,
                sq32    => ssq32o
        );
        --!TBXINSTANCESTART
        inversion_block : invr32
        port map (
                clk             => clk,
                dvd32   => ssq32o,
                qout32  => inv32o
        );
 
 
 
 
 
end architecture;
 
 
 

Line No.	Rev	Author	Line
1	150	jguarin200	`--! @file arithblock.vhd`
2			`--! @brief Bloque Aritmético de 4 sumadores y 6 multiplicadores.`
3			`--! @author Julián Andrés Guarín Reyes`
4			`--------------------------------------------------------------`
5			`-- RAYTRAC`
6			`-- Author Julian Andres Guarin`
7			`-- memblock.vhd`
8			`-- This file is part of raytrac.`
9			`--`
10			`-- raytrac is free software: you can redistribute it and/or modify`
11			`-- it under the terms of the GNU General Public License as published by`
12			`-- the Free Software Foundation, either version 3 of the License, or`
13			`-- (at your option) any later version.`
14			`--`
15			`-- raytrac is distributed in the hope that it will be useful,`
16			`-- but WITHOUT ANY WARRANTY; without even the implied warranty of`
17	206	jguarin200	`-- MERCHANTABILITY or FITNESS FOR a PARTICULAR PURPOSE. See the`
18	150	jguarin200	`-- GNU General Public License for more details.`
19			`--`
20			`-- You should have received a copy of the GNU General Public License`
21			`-- along with raytrac. If not, see <http://www.gnu.org/licenses/>.`
22
23
24			`library ieee;`
25			`use ieee.std_logic_1164.all;`
26	152	jguarin200	`use work.arithpack.all;`
27	150	jguarin200
28			`entity arithblock is`
29			`port (`
30
31			`clk : in std_logic;`
32			`rst : in std_logic;`
33
34	206	jguarin200	`sign : in std_logic;`
35	256	jguarin200	`sign_switch : in std_logic;`
36	150	jguarin200
37	229	jguarin200	`factor0 : in std_logic_vector(31 downto 0);`
38			`factor1 : in std_logic_vector(31 downto 0);`
39			`factor2 : in std_logic_vector(31 downto 0);`
40			`factor3 : in std_logic_vector(31 downto 0);`
41			`factor4 : in std_logic_vector(31 downto 0);`
42			`factor5 : in std_logic_vector(31 downto 0);`
43			`factor6 : in std_logic_vector(31 downto 0);`
44			`factor7 : in std_logic_vector(31 downto 0);`
45			`factor8 : in std_logic_vector(31 downto 0);`
46			`factor9 : in std_logic_vector(31 downto 0);`
47			`factor10 : in std_logic_vector(31 downto 0);`
48			`factor11 : in std_logic_vector(31 downto 0);`
49			`--factor : in vectorblock06;`
50
51			`sumando0 : in std_logic_vector(31 downto 0);`
52			`sumando1 : in std_logic_vector(31 downto 0);`
53			`sumando2 : in std_logic_vector(31 downto 0);`
54			`sumando3 : in std_logic_vector(31 downto 0);`
55			`sumando4 : in std_logic_vector(31 downto 0);`
56			`sumando5 : in std_logic_vector(31 downto 0);`
57			`--add32blki : in vectorblock06;`
58	150	jguarin200
59	229	jguarin200	`a0 : out std_logic_vector(31 downto 0);`
60			`a1 : out std_logic_vector(31 downto 0);`
61			`a2 : out std_logic_vector(31 downto 0);`
62			`--add32blko : out vectorblock03;`
63	206	jguarin200
64	229	jguarin200	`p0 : out std_logic_vector(31 downto 0);`
65			`p1 : out std_logic_vector(31 downto 0);`
66			`p2 : out std_logic_vector(31 downto 0);`
67			`p3 : out std_logic_vector(31 downto 0);`
68			`p4 : out std_logic_vector(31 downto 0);`
69			`p5 : out std_logic_vector(31 downto 0);`
70			`--p : out vectorblock06;`
71	206	jguarin200
72	229	jguarin200	`sq32o : out std_logic_vector(31 downto 0);`
73			`inv32o : out std_logic_vector(31 downto 0)`
74	206	jguarin200
75	229	jguarin200
76	150	jguarin200
77			`);`
78			`end entity;`
79
80			`architecture arithblock_arch of arithblock is`
81	152	jguarin200
82	229	jguarin200	`signal sadd32blko_01 : std_logic_vector(31 downto 0);`
83			`signal ssq32o : std_logic_vector(31 downto 0);`
84	256	jguarin200	`signal ssigna1 : std_logic;`
85	206	jguarin200
86	219	jguarin200	`--! Componentes Aritméticos`
87	228	jguarin200	`component fadd32long`
88	219	jguarin200	`port (`
89			`clk : in std_logic;`
90			`dpc : in std_logic;`
91	229	jguarin200	`a32 : in std_logic_vector(31 downto 0);`
92			`b32 : in std_logic_vector(31 downto 0);`
93			`c32 : out std_logic_vector(31 downto 0)`
94	219	jguarin200	`);`
95			`end component;`
96			`component fmul32`
97			`port (`
98			`clk : in std_logic;`
99	229	jguarin200	`a32 : in std_logic_vector(31 downto 0);`
100			`b32 : in std_logic_vector(31 downto 0);`
101			`p32 : out std_logic_vector(31 downto 0)`
102	219	jguarin200	`);`
103			`end component;`
104			`--! Bloque de Raiz Cuadrada`
105			`component sqrt32`
106			`port (`
107
108			`clk : in std_logic;`
109	229	jguarin200	`rd32: in std_logic_vector(31 downto 0);`
110			`sq32: out std_logic_vector(31 downto 0)`
111	219	jguarin200	`);`
112			`end component;`
113			`--! Bloque de Inversores.`
114			`component invr32`
115			`port (`
116
117			`clk : in std_logic;`
118	229	jguarin200	`dvd32 : in std_logic_vector(31 downto 0);`
119			`qout32 : out std_logic_vector(31 downto 0)`
120	219	jguarin200	`);`
121			`end component;`
122	152	jguarin200
123
124	150	jguarin200	`begin`
125	206	jguarin200
126			`sq32o <= ssq32o;`
127	229	jguarin200	`a1 <= sadd32blko_01;`
128	256	jguarin200	`ssigna1 <= sign_switch or sign;`
129	206	jguarin200
130	152	jguarin200	`--!TBXINSTANCESTART`
131	228	jguarin200	`adder_i_0 : fadd32long`
132	152	jguarin200	`port map (`
133			`clk => clk,`
134	206	jguarin200	`dpc => sign,`
135	229	jguarin200	`a32 => sumando0,`
136			`b32 => sumando1,`
137			`c32 => a0`
138	152	jguarin200	`);`
139			`--!TBXINSTANCESTART`
140	228	jguarin200	`adder_i_1 : fadd32long`
141	152	jguarin200	`port map (`
142			`clk => clk,`
143	256	jguarin200	`dpc => ssigna1,`
144	229	jguarin200	`a32 => sumando2,`
145			`b32 => sumando3,`
146	219	jguarin200	`c32 => sadd32blko_01`
147	152	jguarin200	`);`
148			`--!TBXINSTANCESTART`
149	228	jguarin200	`adder_i_2 : fadd32long`
150	152	jguarin200	`port map (`
151			`clk => clk,`
152	206	jguarin200	`dpc => sign,`
153	229	jguarin200	`a32 => sumando4,`
154			`b32 => sumando5,`
155			`c32 => a2`
156	152	jguarin200	`);`
157			`--!TBXINSTANCESTART`
158			`mul_i_0 : fmul32`
159			`port map (`
160			`clk => clk,`
161	229	jguarin200	`a32 => factor0,`
162			`b32 => factor1,`
163			`p32 => p0`
164	152	jguarin200	`);`
165			`--!TBXINSTANCESTART`
166			`mul_i_1 : fmul32`
167			`port map (`
168			`clk => clk,`
169	229	jguarin200	`a32 => factor2,`
170			`b32 => factor3,`
171			`p32 => p1`
172	152	jguarin200	`);`
173			`--!TBXINSTANCESTART`
174			`mul_i_2 : fmul32`
175			`port map (`
176			`clk => clk,`
177	229	jguarin200	`a32 => factor4,`
178			`b32 => factor5,`
179			`p32 => p2`
180	152	jguarin200	`);`
181			`--!TBXINSTANCESTART`
182			`mul_i_3 : fmul32`
183			`port map (`
184			`clk => clk,`
185	229	jguarin200	`a32 => factor6,`
186			`b32 => factor7,`
187			`p32 => p3`
188	152	jguarin200	`);`
189			`--!TBXINSTANCESTART`
190			`mul_i_4 : fmul32`
191			`port map (`
192			`clk => clk,`
193	229	jguarin200	`a32 => factor8,`
194			`b32 => factor9,`
195			`p32 => p4`
196	152	jguarin200	`);`
197			`--!TBXINSTANCESTART`
198			`mul_i_5 : fmul32`
199			`port map (`
200			`clk => clk,`
201	229	jguarin200	`a32 => factor10,`
202			`b32 => factor11,`
203			`p32 => p5`
204	152	jguarin200	`);`
205	206	jguarin200	`--!TBXINSTANCESTART`
206			`square_root : sqrt32`
207			`port map (`
208			`clk => clk,`
209			`rd32 => sadd32blko_01,`
210			`sq32 => ssq32o`
211			`);`
212			`--!TBXINSTANCESTART`
213			`inversion_block : invr32`
214			`port map (`
215			`clk => clk,`
216			`dvd32 => ssq32o,`
217			`qout32 => inv32o`
218			`);`
219	152	jguarin200
220
221
222	206	jguarin200
223
224	150	jguarin200	`end architecture;`
225
226
227

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[/] [raytrac/] [branches/] [fp_sgdma/] [arith/] [single/] [arithblock.vhd] - Blame information for rev 256