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--! @file arithblock.vhd
--! @brief Bloque Aritmético de 4 sumadores y 6 multiplicadores. 
--! @author Juli&aacute;n Andr&eacute;s Guar&iacute;n Reyes
--------------------------------------------------------------
-- RAYTRAC
-- Author Julian Andres Guarin
-- memblock.vhd
-- This file is part of raytrac.
-- 
--     raytrac is free software: you can redistribute it and/or modify
--     it under the terms of the GNU General Public License as published by
--     the Free Software Foundation, either version 3 of the License, or
--     (at your option) any later version.
-- 
--     raytrac is distributed in the hope that it will be useful,
--     but WITHOUT ANY WARRANTY; without even the implied warranty of
--     MERCHANTABILITY or FITNESS FOR a PARTICULAR PURPOSE.  See the
--     GNU General Public License for more details.
-- 
--     You should have received a copy of the GNU General Public License
--     along with raytrac.  If not, see <http://www.gnu.org/licenses/>.
 
 
library ieee;
use ieee.std_logic_1164.all;
use work.arithpack.all;
 
entity arithblock is
        port (
 
                clk     : in std_logic;
                rst : in std_logic;
 
                sign : in std_logic;
 
                factor0         : in std_logic_vector(31 downto 0);
                factor1         : in std_logic_vector(31 downto 0);
                factor2         : in std_logic_vector(31 downto 0);
                factor3         : in std_logic_vector(31 downto 0);
                factor4         : in std_logic_vector(31 downto 0);
                factor5         : in std_logic_vector(31 downto 0);
                factor6         : in std_logic_vector(31 downto 0);
                factor7         : in std_logic_vector(31 downto 0);
                factor8         : in std_logic_vector(31 downto 0);
                factor9         : in std_logic_vector(31 downto 0);
                factor10        : in std_logic_vector(31 downto 0);
                factor11        : in std_logic_vector(31 downto 0);
                --factor        : in vectorblock06;
 
                sumando0        : in std_logic_vector(31 downto 0);
                sumando1        : in std_logic_vector(31 downto 0);
                sumando2        : in std_logic_vector(31 downto 0);
                sumando3        : in std_logic_vector(31 downto 0);
                sumando4        : in std_logic_vector(31 downto 0);
                sumando5        : in std_logic_vector(31 downto 0);
                --add32blki     : in vectorblock06;
 
                a0                      : out std_logic_vector(31 downto 0);
                a1                      : out std_logic_vector(31 downto 0);
                a2                      : out std_logic_vector(31 downto 0);
                --add32blko     : out vectorblock03;
 
                p0                      : out std_logic_vector(31 downto 0);
                p1                      : out std_logic_vector(31 downto 0);
                p2                      : out std_logic_vector(31 downto 0);
                p3                      : out std_logic_vector(31 downto 0);
                p4                      : out std_logic_vector(31 downto 0);
                p5                      : out std_logic_vector(31 downto 0);
                --p     : out vectorblock06;
 
                sq32o           : out std_logic_vector(31 downto 0);
                inv32o          : out std_logic_vector(31 downto 0)
 
 
 
        );
end entity;
 
architecture arithblock_arch of arithblock is
 
        --! Altera Compiler Directive, to avoid m9k autoinferring thanks to the guys at http://www.alteraforum.com/forum/archive/index.php/t-30784.html .... 
        attribute altera_attribute : string;
        attribute altera_attribute of arithblock_arch : architecture is "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF";
 
 
        signal sadd32blko_01 : std_logic_vector(31 downto 0);
        signal ssq32o : std_logic_vector(31 downto 0);
 
        --! Componentes Aritm&eacute;ticos
        component fadd32long
        port (
                clk : in std_logic;
                dpc : in std_logic;
                a32 : in std_logic_vector(31 downto 0);
                b32 : in std_logic_vector(31 downto 0);
                c32 : out std_logic_vector(31 downto 0)
        );
        end component;
        component fmul32
        port (
                clk : std_logic;
                factor0 : in std_logic_vector(31 downto 0);
                factor1 : in std_logic_vector(31 downto 0);
                factor2 : in std_logic_vector(31 downto 0);
                factor3 : in std_logic_vector(31 downto 0);
                factor4 : in std_logic_vector(31 downto 0);
                factor5 : in std_logic_vector(31 downto 0);
                factor6 : in std_logic_vector(31 downto 0);
                factor7 : in std_logic_vector(31 downto 0);
                factor8 : in std_logic_vector(31 downto 0);
                factor9 : in std_logic_vector(31 downto 0);
                factor10: in std_logic_vector(31 downto 0);
                factor11: in std_logic_vector(31 downto 0);
                p0: out std_logic_vector(31 downto 0);
                p1: out std_logic_vector(31 downto 0);
                p2: out std_logic_vector(31 downto 0);
                p3: out std_logic_vector(31 downto 0);
                p4: out std_logic_vector(31 downto 0);
                p5: out std_logic_vector(31 downto 0)
 
        );
        end component;
        --! Bloque de Raiz Cuadrada
        component sqrt32
        port (
 
                clk     : in std_logic;
                rd32: in std_logic_vector(31 downto 0);
                sq32: out std_logic_vector(31 downto 0)
        );
        end component;
        --! Bloque de Inversores.
        component invr32
        port (
 
                clk             : in std_logic;
                dvd32   : in std_logic_vector(31 downto 0);
                qout32  : out std_logic_vector(31 downto 0)
        );
        end component;
 
 
begin
 
        sq32o <= ssq32o;
        a1 <= sadd32blko_01;
 
        --!TBXINSTANCESTART
        adder_i_0 : fadd32long
        port map (
                clk => clk,
                dpc => sign,
                a32 => sumando0,
                b32 => sumando1,
                c32 => a0
        );
        --!TBXINSTANCESTART
        adder_i_1 : fadd32long
        port map (
                clk => clk,
                dpc => sign,
                a32 => sumando2,
                b32 => sumando3,
                c32 => sadd32blko_01
        );
        --!TBXINSTANCESTART
        adder_i_2 : fadd32long
        port map (
                clk => clk,
                dpc => sign,
                a32 => sumando4,
                b32 => sumando5,
                c32 => a2
        );
        --!TBXINSTANCESTART
        mul_i_0 : fmul32
        port map (
                clk => clk,
                factor0 => factor0,
                factor1 => factor1,
                factor2 => factor2,
                factor3 => factor3,
                factor4 => factor4,
                factor5 => factor5,
                factor6 => factor6,
                factor7 => factor7,
                factor8 => factor8,
                factor9 => factor9,
                factor10 => factor10,
                factor11 => factor11,
                p0 => p0,
                p1 => p1,
                p2 => p2,
                p3 => p3,
                p4 => p4,
                p5 => p5
        );
        --!TBXINSTANCESTART
        square_root : sqrt32
        port map (
                clk     => clk,
                rd32    => sadd32blko_01,
                sq32    => ssq32o
        );
        --!TBXINSTANCESTART
        inversion_block : invr32
        port map (
                clk             => clk,
                dvd32   => ssq32o,
                qout32  => inv32o
        );
 
 
 
 
 
end architecture;
 
 
 

Line No.	Rev	Author	Line
1	150	jguarin200	`--! @file arithblock.vhd`
2			`--! @brief Bloque Aritmético de 4 sumadores y 6 multiplicadores.`
3			`--! @author Julián Andrés Guarín Reyes`
4			`--------------------------------------------------------------`
5			`-- RAYTRAC`
6			`-- Author Julian Andres Guarin`
7			`-- memblock.vhd`
8			`-- This file is part of raytrac.`
9			`--`
10			`-- raytrac is free software: you can redistribute it and/or modify`
11			`-- it under the terms of the GNU General Public License as published by`
12			`-- the Free Software Foundation, either version 3 of the License, or`
13			`-- (at your option) any later version.`
14			`--`
15			`-- raytrac is distributed in the hope that it will be useful,`
16			`-- but WITHOUT ANY WARRANTY; without even the implied warranty of`
17	206	jguarin200	`-- MERCHANTABILITY or FITNESS FOR a PARTICULAR PURPOSE. See the`
18	150	jguarin200	`-- GNU General Public License for more details.`
19			`--`
20			`-- You should have received a copy of the GNU General Public License`
21			`-- along with raytrac. If not, see <http://www.gnu.org/licenses/>.`
22
23
24			`library ieee;`
25			`use ieee.std_logic_1164.all;`
26	152	jguarin200	`use work.arithpack.all;`
27	150	jguarin200
28			`entity arithblock is`
29			`port (`
30
31			`clk : in std_logic;`
32			`rst : in std_logic;`
33
34	206	jguarin200	`sign : in std_logic;`
35	150	jguarin200
36	229	jguarin200	`factor0 : in std_logic_vector(31 downto 0);`
37			`factor1 : in std_logic_vector(31 downto 0);`
38			`factor2 : in std_logic_vector(31 downto 0);`
39			`factor3 : in std_logic_vector(31 downto 0);`
40			`factor4 : in std_logic_vector(31 downto 0);`
41			`factor5 : in std_logic_vector(31 downto 0);`
42			`factor6 : in std_logic_vector(31 downto 0);`
43			`factor7 : in std_logic_vector(31 downto 0);`
44			`factor8 : in std_logic_vector(31 downto 0);`
45			`factor9 : in std_logic_vector(31 downto 0);`
46			`factor10 : in std_logic_vector(31 downto 0);`
47			`factor11 : in std_logic_vector(31 downto 0);`
48			`--factor : in vectorblock06;`
49
50			`sumando0 : in std_logic_vector(31 downto 0);`
51			`sumando1 : in std_logic_vector(31 downto 0);`
52			`sumando2 : in std_logic_vector(31 downto 0);`
53			`sumando3 : in std_logic_vector(31 downto 0);`
54			`sumando4 : in std_logic_vector(31 downto 0);`
55			`sumando5 : in std_logic_vector(31 downto 0);`
56			`--add32blki : in vectorblock06;`
57	150	jguarin200
58	229	jguarin200	`a0 : out std_logic_vector(31 downto 0);`
59			`a1 : out std_logic_vector(31 downto 0);`
60			`a2 : out std_logic_vector(31 downto 0);`
61			`--add32blko : out vectorblock03;`
62	206	jguarin200
63	229	jguarin200	`p0 : out std_logic_vector(31 downto 0);`
64			`p1 : out std_logic_vector(31 downto 0);`
65			`p2 : out std_logic_vector(31 downto 0);`
66			`p3 : out std_logic_vector(31 downto 0);`
67			`p4 : out std_logic_vector(31 downto 0);`
68			`p5 : out std_logic_vector(31 downto 0);`
69			`--p : out vectorblock06;`
70	206	jguarin200
71	229	jguarin200	`sq32o : out std_logic_vector(31 downto 0);`
72			`inv32o : out std_logic_vector(31 downto 0)`
73	206	jguarin200
74	229	jguarin200
75	150	jguarin200
76			`);`
77			`end entity;`
78
79			`architecture arithblock_arch of arithblock is`
80	152	jguarin200
81	238	jguarin200	`--! Altera Compiler Directive, to avoid m9k autoinferring thanks to the guys at http://www.alteraforum.com/forum/archive/index.php/t-30784.html ....`
82			`attribute altera_attribute : string;`
83			`attribute altera_attribute of arithblock_arch : architecture is "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF";`
84
85
86	229	jguarin200	`signal sadd32blko_01 : std_logic_vector(31 downto 0);`
87			`signal ssq32o : std_logic_vector(31 downto 0);`
88	206	jguarin200
89	219	jguarin200	`--! Componentes Aritméticos`
90	228	jguarin200	`component fadd32long`
91	219	jguarin200	`port (`
92			`clk : in std_logic;`
93			`dpc : in std_logic;`
94	229	jguarin200	`a32 : in std_logic_vector(31 downto 0);`
95			`b32 : in std_logic_vector(31 downto 0);`
96			`c32 : out std_logic_vector(31 downto 0)`
97	219	jguarin200	`);`
98			`end component;`
99			`component fmul32`
100			`port (`
101	239	jguarin200	`clk : std_logic;`
102	238	jguarin200	`factor0 : in std_logic_vector(31 downto 0);`
103			`factor1 : in std_logic_vector(31 downto 0);`
104			`factor2 : in std_logic_vector(31 downto 0);`
105			`factor3 : in std_logic_vector(31 downto 0);`
106			`factor4 : in std_logic_vector(31 downto 0);`
107			`factor5 : in std_logic_vector(31 downto 0);`
108			`factor6 : in std_logic_vector(31 downto 0);`
109			`factor7 : in std_logic_vector(31 downto 0);`
110			`factor8 : in std_logic_vector(31 downto 0);`
111			`factor9 : in std_logic_vector(31 downto 0);`
112			`factor10: in std_logic_vector(31 downto 0);`
113			`factor11: in std_logic_vector(31 downto 0);`
114			`p0: out std_logic_vector(31 downto 0);`
115			`p1: out std_logic_vector(31 downto 0);`
116			`p2: out std_logic_vector(31 downto 0);`
117			`p3: out std_logic_vector(31 downto 0);`
118			`p4: out std_logic_vector(31 downto 0);`
119	239	jguarin200	`p5: out std_logic_vector(31 downto 0)`
120	238	jguarin200
121	219	jguarin200	`);`
122			`end component;`
123			`--! Bloque de Raiz Cuadrada`
124			`component sqrt32`
125			`port (`
126
127			`clk : in std_logic;`
128	229	jguarin200	`rd32: in std_logic_vector(31 downto 0);`
129			`sq32: out std_logic_vector(31 downto 0)`
130	219	jguarin200	`);`
131			`end component;`
132			`--! Bloque de Inversores.`
133			`component invr32`
134			`port (`
135
136			`clk : in std_logic;`
137	229	jguarin200	`dvd32 : in std_logic_vector(31 downto 0);`
138			`qout32 : out std_logic_vector(31 downto 0)`
139	219	jguarin200	`);`
140			`end component;`
141	152	jguarin200
142
143	150	jguarin200	`begin`
144	206	jguarin200
145			`sq32o <= ssq32o;`
146	229	jguarin200	`a1 <= sadd32blko_01;`
147	206	jguarin200
148	152	jguarin200	`--!TBXINSTANCESTART`
149	228	jguarin200	`adder_i_0 : fadd32long`
150	152	jguarin200	`port map (`
151			`clk => clk,`
152	206	jguarin200	`dpc => sign,`
153	229	jguarin200	`a32 => sumando0,`
154			`b32 => sumando1,`
155			`c32 => a0`
156	152	jguarin200	`);`
157			`--!TBXINSTANCESTART`
158	228	jguarin200	`adder_i_1 : fadd32long`
159	152	jguarin200	`port map (`
160			`clk => clk,`
161	206	jguarin200	`dpc => sign,`
162	229	jguarin200	`a32 => sumando2,`
163			`b32 => sumando3,`
164	219	jguarin200	`c32 => sadd32blko_01`
165	152	jguarin200	`);`
166			`--!TBXINSTANCESTART`
167	228	jguarin200	`adder_i_2 : fadd32long`
168	152	jguarin200	`port map (`
169			`clk => clk,`
170	206	jguarin200	`dpc => sign,`
171	229	jguarin200	`a32 => sumando4,`
172			`b32 => sumando5,`
173			`c32 => a2`
174	152	jguarin200	`);`
175			`--!TBXINSTANCESTART`
176			`mul_i_0 : fmul32`
177			`port map (`
178			`clk => clk,`
179	238	jguarin200	`factor0 => factor0,`
180			`factor1 => factor1,`
181			`factor2 => factor2,`
182			`factor3 => factor3,`
183			`factor4 => factor4,`
184			`factor5 => factor5,`
185			`factor6 => factor6,`
186			`factor7 => factor7,`
187			`factor8 => factor8,`
188			`factor9 => factor9,`
189			`factor10 => factor10,`
190			`factor11 => factor11,`
191			`p0 => p0,`
192			`p1 => p1,`
193			`p2 => p2,`
194			`p3 => p3,`
195			`p4 => p4,`
196			`p5 => p5`
197	152	jguarin200	`);`
198			`--!TBXINSTANCESTART`
199	206	jguarin200	`square_root : sqrt32`
200			`port map (`
201			`clk => clk,`
202			`rd32 => sadd32blko_01,`
203			`sq32 => ssq32o`
204			`);`
205			`--!TBXINSTANCESTART`
206			`inversion_block : invr32`
207			`port map (`
208			`clk => clk,`
209			`dvd32 => ssq32o,`
210			`qout32 => inv32o`
211			`);`
212	152	jguarin200
213
214
215	206	jguarin200
216
217	150	jguarin200	`end architecture;`
218
219
220

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[/] [raytrac/] [branches/] [fp_sgdma/] [arith/] [wide/] [arithblock.vhd] - Blame information for rev 250