URL https://opencores.org/ocsvn/raytrac/raytrac/trunk

Subversion Repositories raytrac

[/] [raytrac/] [branches/] [fp_sgdma/] [arithpack.vhd] - Blame information for rev 203

Go to most recent revision | Details | Compare with Previous | View Log


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.math_real.all;
 
library std;
use std.textio.all;
 
 
 
--! Memory Compiler Library
library altera_mf;
use altera_mf.all;
library lpm;
use lpm.all;
 
 
 
package arithpack is
 
        --!Constantes usadas por los RTLs
        constant qz : integer := 00;constant qy : integer := 01;constant qx : integer := 02;
        constant az : integer := 00;constant ay : integer := 01;constant ax : integer := 02;constant bz : integer := 03;constant by : integer := 04;constant bx : integer := 05;
        constant f0     : integer := 00;constant f1 : integer := 01;constant f2 : integer := 02;constant f3 : integer := 03;constant f4 : integer := 04;constant f5 : integer := 05;
        constant f6     : integer := 06;constant f7 : integer := 07;constant f8 : integer := 08;constant f9 : integer := 09;constant f10: integer := 10;constant f11: integer := 11;
        constant s0     : integer := 00;constant s1 : integer := 01;constant s2 : integer := 02;constant s3 : integer := 03;constant s4 : integer := 04;constant s5 : integer := 05;
        constant a0     : integer := 00;constant a1 : integer := 01;constant a2 : integer := 02;
        constant p0     : integer := 00;constant p1 : integer := 01;constant p2 : integer := 02;constant p3 : integer := 03;constant p4 : integer := 04;constant p5 : integer := 05;
 
        constant index_control_register : integer := 00;
        constant index_start_address_r  : integer := 01;
        constant index_end_address_r    : integer := 02;
        constant index_start_address_w  : integer := 03;
        constant index_end_address_w    : integer := 04;
        constant index_scratch_register : integer := 05;
 
        --! M&aacute;quina de estados.
 
 
        --! Control de tama&ntilde;os de memoria.
        constant widthadmemblock : integer := 9;
 
        subtype xfloat32 is std_logic_vector(31 downto 0);
        type    v3f     is array(02 downto 0) of xfloat32;
 
        --! Constantes para definir bloques de valores de 32 bits single float
        type    vectorblock12 is array (11 downto 0) of xfloat32;
        type    vectorblock08 is array (07 downto 0) of xfloat32;
        type    vectorblock06 is array (05 downto 0) of xfl      oat32;
        type    vectorblock04 is array (03 downto 0) of xfloat32;
        type    vectorblock03 is array (02 downto 0) of xfloat32;
        type    vectorblock02 is array (01 downto 0) of xfloat32;
 
        --! Constante de reseteo
        constant rstMasterValue : std_logic :='0';
 
        --! Constantes periodicas.
        constant tclk   : time := 20 ns;
        constant tclk_2 : time := tclk/2;
        constant tclk_4 : time := tclk/4;
 
 
        component raytrac
        port (
 
                clk : in std_logic;
                rst : in std_logic;
                --! Interface Avalon Master
                address_master  : out   std_logic_vector(31 downto 0);
                begintransfer   : out   std_logic;
                read_master             : out   std_logic;
                readdata_master : in    std_logic_vector (31 downto 0);
                write_master    : out   std_logic;
                writedata_master: out   std_logic_vector (31 downto 0);
                waitrequest             : in    std_logic_vector;
                readdatavalid_m : in    std_logic_vector;
                --! Interface Avalon Slave
                address_slave   : in    std_logic_vector(3 downto 0);
                read_slave              : in    std_logic;
                readdata_slave  : in    std_logic_vector(31 downto 0);
                write_slave             : in    std_logic;
                writedata_slave : in    std_logic_vector(31 downto 0);
                readdatavalid_s : out   std_logic;
                --! Interface Interrupt Sender
                irq     : out std_logic
        );
        end component;
 
        component raytrac_control
        port (
 
                --! Se&ntilde;ales normales de secuencia.
                clk:                    in std_logic;
                rst:                    in std_logic;
 
                --! Interface Avalon Master
                begintransfer   : out   std_logic;
                address_master  : out   std_logic_vector(31 downto 0);
                read_master             : out   std_logic;
                write_master    : out   std_logic;
                waitrequest             : in    std_logic;
                readdatavalid_m : in    std_logic;
 
                --! Interface Avalon Slave
                address_slave   : in    std_logic_vector(3 downto 0);
                read_slave              : in    std_logic;
                readdata_slave  : out   std_logic_vector(31 downto 0);
                write_slave             : in    std_logic;
                writedata_slave : in    std_logic_vector(31 downto 0);
                readdatavalid_s : out   std_logic;
 
                --! Interface Interrupt Sender
                irq     : out std_logic;
 
                --! Se&ntilde;ales de Control (Memblock)
                go                      : out std_logic;
                comb            : out std_logic;
                load            : out std_logic;
                load_chain      : out std_logic_vector(1 downto 0);
                qparams_e       : in std_logic;
                qresult_e       : in std_logic_vector(3 downto 0);
 
                --! Se&ntilde;les de Control de Datapath (DPC)
                qparams_q       : in  xfloat32;
                d                       : out std_logic;
                c                       : out std_logic;
                s                       : out std_logic;
                qresult_sel     : out std_logic_vector(1 downto 0)
        );
        end component;
 
        --! Bloque de memorias
        component memblock
        port (
 
                --!Entradas de Control
                clk             : in std_logic;
                rst             : in std_logic;
                go                      : in std_logic;
                comb            : in std_logic;
                load            : in std_logic;
                load_chain      : in std_logic_vector(1 downto 0);
 
 
                --! Cola de par&aacute;metros 
                readdatavalid   : in std_logic;
                readdata_master : in xfloat32;
                qparams_r               : in std_logic;
                qparams_e               : out std_logic;
 
                --! Cola de resultados          
                qresult_d       : in vectorblock04;
                qresult_q       : out vectorblock04;
 
                --! Registro de par&aacute;metros
                paraminput      : out vectorblock06;
 
                --! Cadena de sincronización
                sync_chain_0    : out std_logic;
 
                --! se&ntilde;ales de colas vacias
                qresult_e       : out std_logic_vector(3 downto 0);
 
 
 
                --! Colas de resultados
                qresult_w               : in std_logic_vector(3 downto 0);
                qresult_rdec    : in std_logic_vector(3 downto 0)
 
        );
        end component;
        --! Bloque decodificacion DataPath Control.
        component dpc
        port (
                clk                                             : in    std_logic;
                rst                                             : in    std_logic;
 
                paraminput                              : in    vectorblock06;  --! Vectores A,B
 
                prd32blko                               : in    vectorblock06;  --! Salidas de los 6 multiplicadores.
                add32blko                               : in    vectorblock03;  --! Salidas de los 3 sumadores.
                inv32blko                               : in    xfloat32;               --! Salidas de la raiz cuadradas y el inversor.
                sqr32blko                               : in    xfloat32;               --! Salidas de la raiz cuadradas y el inversor.
 
 
                d,c,s                                   : in    std_logic;              --! Bit con el identificador del bloque AB vs CD e identificador del sub bloque (A/B) o (C/D). 
 
                sync_chain_0                    : in    std_logic;              --! Se&ntilde;al de dato valido que se va por toda la cadena de sincronizacion.
 
                qresult_q                               : in    vectorblock04;  --! Salida de las colas de resultados
                qresult_sel                             : in    std_logic_vector (1 downto 0); --! Direccion con el resultado de la
                qresult_rdec                    : out   std_logic_vector (3 downto 0); --!Se&ntilde;ales de escritura decodificadas
                qresult_w                               : out   std_logic_vector (3 downto 0);                           --! Salidas de escritura y lectura en las colas de resultados.
                qresult_d                               : out   vectorblock04; --! 4 salidas de resultados, pues lo m&aacute;ximo que podr&aacute; calcularse por cada clock son 2 vectores. 
 
                dataread                                : in    std_logic;
 
 
                prd32blki                               : out   vectorblock12;  --! Entrada de los 12 factores en el bloque de multiplicaci&oacute;n respectivamente.
                add32blki                               : out   vectorblock06;  --! Entrada de los 6 sumandos del bloque de 3 sumadores.  
 
                dataout                                 : out   xfloat32
 
        );
        end component;
        --! Bloque Aritmetico de Sumadores y Multiplicadores (madd)
        component arithblock
        port (
 
                clk     : in std_logic;
                rst : in std_logic;
 
                sign            : in std_logic;
 
                prd32blki       : in vectorblock12;
                add32blki       : in vectorblock06;
 
                add32blko       : out vectorblock03;
                prd32blko       : out vectorblock06;
 
                sq32o           : out xfloat32;
                inv32o          : out xfloat32
 
        );
        end component;
        --! Componentes Aritm&eacute;ticos
        component fadd32
        port (
                clk : in std_logic;
                dpc : in std_logic;
                a32 : in xfloat32;
                b32 : in xfloat32;
                c32 : out xfloat32
        );
        end component;
        component fmul32
        port (
                clk : in std_logic;
                a32 : in xfloat32;
                b32 : in xfloat32;
                p32 : out xfloat32
        );
        end component;
        --! Bloque de Raiz Cuadrada
        component sqrt32
        port (
 
                clk     : in std_logic;
                rd32: in xfloat32;
                sq32: out xfloat32
        );
        end component;
        --! Bloque de Inversores.
        component invr32
        port (
 
                clk             : in std_logic;
                dvd32   : in xfloat32;
                qout32  : out xfloat32
        );
        end component;
        --! Contadores para la m&aacute;quina de estados.
 
        component customCounter
        port (
                clk                             : in std_logic;
                rst                             : in std_logic;
                stateTrans                      : in std_logic;
                waitrequest_n   : in std_logic;
                endaddress              : in std_logic_vector (31 downto 2); --! Los 5 bits de arriba.
                startaddress    : in std_logic_vector(31 downto 0);
                endaddressfetch : out std_logic;
                address_master  : out std_logic_vector (31 downto 0)
        );
        end component;
 
        --! LPM_MULTIPLIER
        component lpm_mult
        generic (
                lpm_hint                        : string;
                lpm_pipeline            : natural;
                lpm_representation      : string;
                lpm_type                        : string;
                lpm_widtha                      : natural;
                lpm_widthb                      : natural;
                lpm_widthp                      : natural
        );
        port (
                dataa   : in std_logic_vector ( lpm_widtha-1 downto 0 );
                datab   : in std_logic_vector ( lpm_widthb-1 downto 0 );
                result  : out std_logic_vector( lpm_widthp-1 downto 0 )
        );
        end component;
        --! LPM Memory Compiler.
        component scfifo
        generic (
                add_ram_output_register :string;
                allow_rwcycle_when_full :string;
                intended_device_family  :string;
                lpm_hint                                :string;
                lpm_numwords                    :natural;
                lpm_showahead                   :string;
                lpm_type                                :string;
                lpm_width                               :natural;
                overflow_checking               :string;
                underflow_checking              :string;
                use_eab                                 :string
        );
        port(
                rdreq           : in std_logic;
                aclr            : in std_logic;
                empty           : out std_logic;
                clock           : in std_logic;
                q                       : out std_logic_vector(lpm_width-1 downto 0);
                wrreq           : in std_logic;
                data            : in std_logic_vector(lpm_width-1 downto 0);
                almost_full : out std_logic;
                full            : out std_logic
        );
        end component;
 
 
 
 
 
 
 
 
 
        type apCamera is record
                resx,resy : integer;
                width,height : real;
                dist : real;
        end record;
 
        --! Funci&oacute;n que convierte un std_logic_vector en un numero entero
        function ap_slv2int(sl:std_logic_vector) return integer;
 
        --! Funci&oacute;n que convierte un n&uacute;mero flotante IEE754 single float, en un n&uacute;mero std_logic_vector.
        function ap_fp2slv (f:real) return std_logic_vector;
 
        --! Funci&oacute;n que convierte un n&uacute;mero std_logic_vector en un ieee754 single float.
        function ap_slv2fp (sl:std_logic_vector) return real;
 
        --! Funci&oacute;n que devuelve un vector en punto flotante IEEE754 a trav&eacute;s de un   
        function ap_slv_calc_xyvec (x,y:integer; cam:apCamera) return v3f;
 
        --! Funci&oacute;n que devuelve una cadena con el n&uacute;mero flotante IEEE 754 &oacute; a una cadena de cifras hexadecimales.
        procedure ap_slvf2string(l:inout line;sl:std_logic_vector);
        procedure ap_slv2hex (l:inout line;h:in std_logic_vector) ;
 
 
 
        --! Funci&oacute;n que devuelve una cadena con los componentes de un vector R3 en punto flotante IEEE754        
        procedure ap_v3f2string(l:inout line;v:in v3f);
        procedure ap_xfp032string(l:inout line;vb03:in vectorblock03);
 
        --! Funci&oacute;n que formatea una instrucci&oacute;n
        function ap_format_instruction(i:string;ac_o,ac_f,bd_o,bd_f:std_logic_vector;comb:std_logic) return std_logic_vector;
 
        --! Funci&oacute;n que devuelve una cadena de caracteres de un solo caracter con el valor de un bit std_logic
        procedure ap_sl2string(l:inout line;s:std_logic);
 
        --! Procedimiento para mostrar vectores en forma de arreglos de flotantes
        procedure ap_xfp122string(l:inout line;vb12:in vectorblock12);
        procedure ap_xfp082string(l:inout line;vb08:in vectorblock08);
        procedure ap_xfp062string(l:inout line;vb06:in vectorblock06);
        procedure ap_xfp042string(l:inout line;vb04:in vectorblock04);
        procedure ap_xfp022string(l:inout line;vb02:in vectorblock02);
 
 
end package;
 
 
package body arithpack is
 
        procedure ap_xfp022string(l:inout line; vb02:in vectorblock02) is
        begin
                for i in 01 downto 0 loop
                        write(l,string'(" ["&integer'image(i)&"]"));
                        write(l,string'(" "));
                        ap_slvf2string(l,vb02(i));
                end loop;
 
        end procedure;
        procedure ap_xfp122string(l:inout line; vb12:in vectorblock12) is
 
        begin
                for i in 11 downto 0 loop
                        write(l,string'(" ["&integer'image(i)&"]"));
                        write(l,string'(" "));
                        ap_slvf2string(l,vb12(i));
                end loop;
        end procedure;
 
        procedure ap_xfp082string(l:inout line; vb08:in vectorblock08) is
 
        begin
                for i in 07 downto 0 loop
                        write(l,string'(" ["&integer'image(i)&"]"));
                        write(l,string'(" "));
                        ap_slvf2string(l,vb08(i));
                end loop;
        end procedure;
 
        procedure ap_xfp062string(l:inout line; vb06:in vectorblock06) is
 
        begin
                for i in 05 downto 0 loop
                        write(l,string'(" ["&integer'image(i)&"]"));
                        write(l,string'(" "));
                        ap_slvf2string(l,vb06(i));
                end loop;
        end procedure;
 
        procedure ap_xfp042string(l:inout line; vb04:in vectorblock04) is
 
        begin
                for i in 03 downto 0 loop
                        write(l,string'(" ["&integer'image(i)&"]"));
                        write(l,string'(" "));
                        ap_slvf2string(l,vb04(i));
                end loop;
        end procedure;
 
 
        procedure ap_sl2string(l:inout line; s:in std_logic)is
                variable tmp:string(1 to 1);
        begin
 
                case s is
                        when '1' =>
                                tmp:="1";
                        when '0' =>
                                tmp:="0";
                        when 'U' =>
                                tmp:="U";
                        when 'X' =>
                                tmp:="X";
                        when 'Z' =>
                                tmp:="Z";
                        when 'W' =>
                                tmp:="W";
                        when 'L' =>
                                tmp:="L";
                        when 'H' =>
                                tmp:="H";
                        when others =>
                                tmp:="-"; -- Don't care
                end case;
                write(l,string'(" "));
                write(l,string'(tmp));
                write(l,string'(" "));
 
 
 
        end procedure;
 
        function ap_format_instruction(i:string;ac_o,ac_f,bd_o,bd_f:std_logic_vector;comb:std_logic) return std_logic_vector is
 
                alias aco : std_logic_vector (4 downto 0) is ac_o;
                alias acf : std_logic_vector (4 downto 0) is ac_f;
                alias bdo : std_logic_vector (4 downto 0) is bd_o;
                alias bdf : std_logic_vector (4 downto 0) is bd_f;
                variable ins : std_logic_vector (31 downto 0);
                alias it : string (1 to 3) is i;
        begin
 
                case it is
                        when "mag" =>
                                ins(31 downto 29) := "100";
                                ins(04 downto 00) := '1'&x"8";
                        when "nrm" =>
                                ins(31 downto 29) := "110";
                                ins(04 downto 00) := '1'&x"d";
                        when "add" =>
                                ins(31 downto 29) := "001";
                                ins(04 downto 00) := '0'&x"a";
                        when "sub" =>
                                ins(31 downto 29) := "011";
                                ins(04 downto 00) := '0'&x"a";
                        when "dot" =>
                                ins(31 downto 29) := "000";
                                ins(04 downto 00) := '1'&x"7";
                        when "crs" =>
                                ins(31 downto 29) := "010";
                                ins(04 downto 00) := '0'&x"e";
                        when others =>
                                ins(31 downto 29) := "111";
                                ins(04 downto 00) := '0'&x"5";
                end case;
                ins(28 downto 24) := aco;
                ins(23 downto 19) := acf;
                ins(18 downto 14) := bdo;
                ins(13 downto 09) := bdf;
                ins(08) := comb;
                ins(07 downto 05) := "000";
                return ins;
 
 
        end function;
 
 
 
        procedure ap_v3f2string(l:inout line;v:in v3f) is
        begin
                write(l,string'("[X]"));
                write(l,string'(" "));
                ap_slvf2string(l,v(2));
                write(l,string'("[Y]"));
                write(l,string'(" "));
                ap_slvf2string(l,v(1));
                write(l,string'("[Z]"));
                write(l,string'(" "));
                ap_slvf2string(l,v(0));
        end procedure;
        procedure ap_xfp032string(l:inout line;vb03:in vectorblock03) is
        begin
                write(l,string'("[X]"));
                write(l,string'(" "));
                ap_slvf2string(l,vb03(2));
                write(l,string'("[Y]"));
                write(l,string'(" "));
                ap_slvf2string(l,vb03(1));
                write(l,string'("[Z]"));
                write(l,string'(" "));
                ap_slvf2string(l,vb03(0));
        end procedure;
 
        constant hexchars : string (1 to 16) := "0123456789ABCDEF";
        procedure ap_slv2hex (l:inout line;h:in std_logic_vector) is
                variable index_high,index_low,highone,nc : integer;
        begin
                highone := h'high-h'low;
                nc:=0;
                for i in h'high downto h'low loop
                        if h(i)/='0' and h(i)/='1' then
                                nc:=1;
                        end if;
                end loop;
 
                if nc=1 then
                        for i in h'high downto h'low loop
                                ap_sl2string(l,h(i));
                        end loop;
                else
                        for i in (highone)/4 downto 0 loop
                                index_low:=i*4;
                                if (index_low+3)>highone then
                                        index_high := highone;
                                else
                                        index_high := i*4+3;
                                end if;
                                write(l,hexchars(1+ieee.std_logic_unsigned.conv_integer(h(index_high+h'low downto index_low+h'low))));
                        end loop;
                end if;
        end procedure;
 
        function ap_slv2int (sl:std_logic_vector) return integer is
                alias s : std_logic_vector (sl'high downto sl'low) is sl;
                variable i : integer;
        begin
                i:=0;
                for index in s'high downto s'low loop
                        if s(index)='1' then
                                i:=i*2+1;
                        else
                                i:=i*2;
                        end if;
                end loop;
                return i;
 
        end function;
        function ap_fp2slv (f:real) return std_logic_vector is
                variable faux : real;
                variable sef : std_logic_vector (31 downto 0);
        begin
                --! Signo
                if (f<0.0) then
                        sef(31) := '1';
                        faux:=f*(-1.0);
                else
                        sef(31) := '0';
                        faux:=f;
                end if;
 
                --! Exponente
                sef(30 downto 23) := conv_std_logic_vector(127+integer(floor(log(faux,2.0))),8);
 
                --! Fraction
                faux :=faux/(2.0**real(floor(log(faux,2.0))));
                faux := faux - 1.0;
 
                sef(22 downto 0)  := conv_std_logic_vector(integer(faux*(2.0**23.0)),23);
 
                return sef;
 
        end function;
 
        function ap_slv2fp(sl:std_logic_vector) return real is
                variable frc:integer;
                alias s: std_logic_vector(31 downto 0) is sl;
                variable f,expo: real;
 
        begin
 
 
                expo:=real(ap_slv2int(s(30 downto 23)) - 127);
                expo:=(2.0)**(expo);
                frc:=ap_slv2int('1'&s(22 downto 0));
                f:=real(frc)*(2.0**(-23.0));
                f:=f*real(expo);
 
                if s(31)='1' then
                        return -f;
                else
                        return f;
                end if;
 
 
 
 
        end function;
 
        function ap_slv_calc_xyvec (x,y:integer; cam:apCamera) return v3f is
 
 
                variable dx,dy : real;
                variable v : v3f;
        begin
 
                dx := cam.width/real(cam.resx);
                dy := cam.height/real(cam.resy);
 
                --! Eje Z: Tomando el dedo &iacute;ndice de la mano derecha, este eje queda apuntando en la direcci&on en la que mira la c&aacute;mara u observador siempre.
                v(0):=ap_fp2slv(cam.dist);
 
                --! Eje X: Tomando el dedo coraz&oacute;n de la mano derecha, este eje queda apuntando a la izquierda del observador, desde el observador.
                v(2):=ap_fp2slv(dx*real(cam.resx)*0.5-real(x)*dx-dx*0.5);
 
                --! Eje Y: Tomando el dedo pulgar de la mano derecha, este eje queda apuntando hacia arriba del observador, desde el observador.
                v(1):=ap_fp2slv(dy*real(cam.resy)*0.5-real(y)*dy-dy*0.5);
 
                return v;
 
        end function;
 
        procedure ap_slvf2string(l:inout line;sl:std_logic_vector) is
                alias f: std_logic_vector(31 downto 0) is sl;
                variable r: real;
 
        begin
 
                r:=ap_slv2fp(f);
                write(l,string'(real'image(r)));
                write(l,string'(" [ s:"));
                ap_slv2hex(l,f(31 downto 31));
                write(l,string'(" f: "));
                ap_slv2hex(l,f(30 downto 23));
                write(l,string'(" m: "));
                ap_slv2hex(l,f(22 downto 00));
                write(l,string'(" ]"));
 
        end procedure;
 
 
 
 
end package body;

Line No.	Rev	Author	Line
1	151	jguarin200	`library ieee;`
2			`use ieee.std_logic_1164.all;`
3	153	jguarin200	`use ieee.std_logic_arith.all;`
4			`use ieee.math_real.all;`
5	151	jguarin200
6	153	jguarin200	`library std;`
7			`use std.textio.all;`
8
9	159	jguarin200
10
11	151	jguarin200	`--! Memory Compiler Library`
12	159	jguarin200	`library altera_mf;`
13			`use altera_mf.all;`
14	151	jguarin200	`library lpm;`
15			`use lpm.all;`
16
17
18
19			`package arithpack is`
20	152	jguarin200
21	203	jguarin200	`--!Constantes usadas por los RTLs`
22			`constant qz : integer := 00;constant qy : integer := 01;constant qx : integer := 02;`
23			`constant az : integer := 00;constant ay : integer := 01;constant ax : integer := 02;constant bz : integer := 03;constant by : integer := 04;constant bx : integer := 05;`
24			`constant f0 : integer := 00;constant f1 : integer := 01;constant f2 : integer := 02;constant f3 : integer := 03;constant f4 : integer := 04;constant f5 : integer := 05;`
25			`constant f6 : integer := 06;constant f7 : integer := 07;constant f8 : integer := 08;constant f9 : integer := 09;constant f10: integer := 10;constant f11: integer := 11;`
26			`constant s0 : integer := 00;constant s1 : integer := 01;constant s2 : integer := 02;constant s3 : integer := 03;constant s4 : integer := 04;constant s5 : integer := 05;`
27			`constant a0 : integer := 00;constant a1 : integer := 01;constant a2 : integer := 02;`
28			`constant p0 : integer := 00;constant p1 : integer := 01;constant p2 : integer := 02;constant p3 : integer := 03;constant p4 : integer := 04;constant p5 : integer := 05;`
29	189	jguarin200
30	203	jguarin200	`constant index_control_register : integer := 00;`
31			`constant index_start_address_r : integer := 01;`
32			`constant index_end_address_r : integer := 02;`
33			`constant index_start_address_w : integer := 03;`
34			`constant index_end_address_w : integer := 04;`
35			`constant index_scratch_register : integer := 05;`
36
37			`--! Máquina de estados.`
38
39
40	189	jguarin200	`--! Control de tamaños de memoria.`
41	152	jguarin200	`constant widthadmemblock : integer := 9;`
42
43	156	jguarin200	`subtype xfloat32 is std_logic_vector(31 downto 0);`
44			`type v3f is array(02 downto 0) of xfloat32;`
45
46	203	jguarin200	`--! Constantes para definir bloques de valores de 32 bits single float`
47	156	jguarin200	`type vectorblock12 is array (11 downto 0) of xfloat32;`
48			`type vectorblock08 is array (07 downto 0) of xfloat32;`
49	203	jguarin200	`type vectorblock06 is array (05 downto 0) of xfl oat32;`
50			`type vectorblock04 is array (03 downto 0) of xfloat32;`
51			`type vectorblock03 is array (02 downto 0) of xfloat32;`
52			`type vectorblock02 is array (01 downto 0) of xfloat32;`
53	152	jguarin200
54	151	jguarin200	`--! Constante de reseteo`
55			`constant rstMasterValue : std_logic :='0';`
56	168	jguarin200
57	151	jguarin200	`--! Constantes periodicas.`
58			`constant tclk : time := 20 ns;`
59			`constant tclk_2 : time := tclk/2;`
60			`constant tclk_4 : time := tclk/4;`
61
62	152	jguarin200
63			`component raytrac`
64			`port (`
65
66			`clk : in std_logic;`
67			`rst : in std_logic;`
68	203	jguarin200	`--! Interface Avalon Master`
69			`address_master : out std_logic_vector(31 downto 0);`
70			`begintransfer : out std_logic;`
71			`read_master : out std_logic;`
72			`readdata_master : in std_logic_vector (31 downto 0);`
73			`write_master : out std_logic;`
74			`writedata_master: out std_logic_vector (31 downto 0);`
75			`waitrequest : in std_logic_vector;`
76			`readdatavalid_m : in std_logic_vector;`
77			`--! Interface Avalon Slave`
78			`address_slave : in std_logic_vector(3 downto 0);`
79			`read_slave : in std_logic;`
80			`readdata_slave : in std_logic_vector(31 downto 0);`
81			`write_slave : in std_logic;`
82			`writedata_slave : in std_logic_vector(31 downto 0);`
83			`readdatavalid_s : out std_logic;`
84			`--! Interface Interrupt Sender`
85			`irq : out std_logic`
86			`);`
87			`end component;`
88
89			`component raytrac_control`
90			`port (`
91	152	jguarin200
92	203	jguarin200	`--! Señales normales de secuencia.`
93			`clk: in std_logic;`
94			`rst: in std_logic;`
95	152	jguarin200
96	203	jguarin200	`--! Interface Avalon Master`
97			`begintransfer : out std_logic;`
98			`address_master : out std_logic_vector(31 downto 0);`
99			`read_master : out std_logic;`
100			`write_master : out std_logic;`
101			`waitrequest : in std_logic;`
102			`readdatavalid_m : in std_logic;`
103
104			`--! Interface Avalon Slave`
105			`address_slave : in std_logic_vector(3 downto 0);`
106			`read_slave : in std_logic;`
107			`readdata_slave : out std_logic_vector(31 downto 0);`
108			`write_slave : in std_logic;`
109			`writedata_slave : in std_logic_vector(31 downto 0);`
110			`readdatavalid_s : out std_logic;`
111
112			`--! Interface Interrupt Sender`
113			`irq : out std_logic;`
114	152	jguarin200
115	203	jguarin200	`--! Señales de Control (Memblock)`
116			`go : out std_logic;`
117			`comb : out std_logic;`
118			`load : out std_logic;`
119			`load_chain : out std_logic_vector(1 downto 0);`
120			`qparams_e : in std_logic;`
121			`qresult_e : in std_logic_vector(3 downto 0);`
122	152	jguarin200
123	203	jguarin200	`--! Señles de Control de Datapath (DPC)`
124			`qparams_q : in xfloat32;`
125			`d : out std_logic;`
126			`c : out std_logic;`
127			`s : out std_logic;`
128			`qresult_sel : out std_logic_vector(1 downto 0)`
129			`);`
130			`end component;`
131
132			`--! Bloque de memorias`
133			`component memblock`
134			`port (`
135	152	jguarin200
136	203	jguarin200	`--!Entradas de Control`
137			`clk : in std_logic;`
138			`rst : in std_logic;`
139			`go : in std_logic;`
140			`comb : in std_logic;`
141			`load : in std_logic;`
142			`load_chain : in std_logic_vector(1 downto 0);`
143
144	152	jguarin200
145	203	jguarin200	`--! Cola de parámetros`
146			`readdatavalid : in std_logic;`
147			`readdata_master : in xfloat32;`
148			`qparams_r : in std_logic;`
149			`qparams_e : out std_logic;`
150	152	jguarin200
151	203	jguarin200	`--! Cola de resultados`
152			`qresult_d : in vectorblock04;`
153			`qresult_q : out vectorblock04;`
154
155			`--! Registro de parámetros`
156			`paraminput : out vectorblock06;`
157	152	jguarin200
158	203	jguarin200	`--! Cadena de sincronización`
159			`sync_chain_0 : out std_logic;`
160
161			`--! señales de colas vacias`
162			`qresult_e : out std_logic_vector(3 downto 0);`
163
164
165
166			`--! Colas de resultados`
167			`qresult_w : in std_logic_vector(3 downto 0);`
168			`qresult_rdec : in std_logic_vector(3 downto 0)`
169
170			`);`
171			`end component;`
172			`--! Bloque decodificacion DataPath Control.`
173			`component dpc`
174			`port (`
175			`clk : in std_logic;`
176			`rst : in std_logic;`
177
178			`paraminput : in vectorblock06; --! Vectores A,B`
179
180			`prd32blko : in vectorblock06; --! Salidas de los 6 multiplicadores.`
181			`add32blko : in vectorblock03; --! Salidas de los 3 sumadores.`
182			`inv32blko : in xfloat32; --! Salidas de la raiz cuadradas y el inversor.`
183			`sqr32blko : in xfloat32; --! Salidas de la raiz cuadradas y el inversor.`
184
185
186			`d,c,s : in std_logic; --! Bit con el identificador del bloque AB vs CD e identificador del sub bloque (A/B) o (C/D).`
187
188			`sync_chain_0 : in std_logic; --! Señal de dato valido que se va por toda la cadena de sincronizacion.`
189
190			`qresult_q : in vectorblock04; --! Salida de las colas de resultados`
191			`qresult_sel : in std_logic_vector (1 downto 0); --! Direccion con el resultado de la`
192			`qresult_rdec : out std_logic_vector (3 downto 0); --!Señales de escritura decodificadas`
193			`qresult_w : out std_logic_vector (3 downto 0); --! Salidas de escritura y lectura en las colas de resultados.`
194			`qresult_d : out vectorblock04; --! 4 salidas de resultados, pues lo máximo que podrá calcularse por cada clock son 2 vectores.`
195
196			`dataread : in std_logic;`
197
198
199			`prd32blki : out vectorblock12; --! Entrada de los 12 factores en el bloque de multiplicación respectivamente.`
200			`add32blki : out vectorblock06; --! Entrada de los 6 sumandos del bloque de 3 sumadores.`
201
202			`dataout : out xfloat32`
203
204	152	jguarin200	`);`
205			`end component;`
206	203	jguarin200	`--! Bloque Aritmetico de Sumadores y Multiplicadores (madd)`
207			`component arithblock`
208			`port (`
209
210			`clk : in std_logic;`
211			`rst : in std_logic;`
212	152	jguarin200
213	203	jguarin200	`sign : in std_logic;`
214
215			`prd32blki : in vectorblock12;`
216			`add32blki : in vectorblock06;`
217
218			`add32blko : out vectorblock03;`
219			`prd32blko : out vectorblock06;`
220
221			`sq32o : out xfloat32;`
222			`inv32o : out xfloat32`
223
224			`);`
225			`end component;`
226	152	jguarin200	`--! Componentes Aritméticos`
227			`component fadd32`
228			`port (`
229			`clk : in std_logic;`
230			`dpc : in std_logic;`
231	158	jguarin200	`a32 : in xfloat32;`
232			`b32 : in xfloat32;`
233			`c32 : out xfloat32`
234	152	jguarin200	`);`
235			`end component;`
236			`component fmul32`
237			`port (`
238			`clk : in std_logic;`
239	158	jguarin200	`a32 : in xfloat32;`
240			`b32 : in xfloat32;`
241			`p32 : out xfloat32`
242	152	jguarin200	`);`
243			`end component;`
244	203	jguarin200	`--! Bloque de Raiz Cuadrada`
245			`component sqrt32`
246			`port (`
247
248			`clk : in std_logic;`
249			`rd32: in xfloat32;`
250			`sq32: out xfloat32`
251			`);`
252			`end component;`
253			`--! Bloque de Inversores.`
254			`component invr32`
255			`port (`
256
257			`clk : in std_logic;`
258			`dvd32 : in xfloat32;`
259			`qout32 : out xfloat32`
260			`);`
261			`end component;`
262	152	jguarin200	`--! Contadores para la máquina de estados.`
263
264	151	jguarin200	`component customCounter`
265			`port (`
266	203	jguarin200	`clk : in std_logic;`
267			`rst : in std_logic;`
268			`stateTrans : in std_logic;`
269			`waitrequest_n : in std_logic;`
270			`endaddress : in std_logic_vector (31 downto 2); --! Los 5 bits de arriba.`
271			`startaddress : in std_logic_vector(31 downto 0);`
272			`endaddressfetch : out std_logic;`
273			`address_master : out std_logic_vector (31 downto 0)`
274	151	jguarin200	`);`
275			`end component;`
276
277	155	jguarin200	`--! LPM_MULTIPLIER`
278			`component lpm_mult`
279			`generic (`
280			`lpm_hint : string;`
281			`lpm_pipeline : natural;`
282			`lpm_representation : string;`
283			`lpm_type : string;`
284			`lpm_widtha : natural;`
285			`lpm_widthb : natural;`
286			`lpm_widthp : natural`
287			`);`
288			`port (`
289			`dataa : in std_logic_vector ( lpm_widtha-1 downto 0 );`
290			`datab : in std_logic_vector ( lpm_widthb-1 downto 0 );`
291			`result : out std_logic_vector( lpm_widthp-1 downto 0 )`
292			`);`
293			`end component;`
294	151	jguarin200	`--! LPM Memory Compiler.`
295			`component scfifo`
296			`generic (`
297			`add_ram_output_register :string;`
298	159	jguarin200	`allow_rwcycle_when_full :string;`
299	151	jguarin200	`intended_device_family :string;`
300			`lpm_hint :string;`
301			`lpm_numwords :natural;`
302			`lpm_showahead :string;`
303			`lpm_type :string;`
304			`lpm_width :natural;`
305			`overflow_checking :string;`
306			`underflow_checking :string;`
307			`use_eab :string`
308			`);`
309			`port(`
310			`rdreq : in std_logic;`
311			`aclr : in std_logic;`
312			`empty : out std_logic;`
313			`clock : in std_logic;`
314			`q : out std_logic_vector(lpm_width-1 downto 0);`
315			`wrreq : in std_logic;`
316			`data : in std_logic_vector(lpm_width-1 downto 0);`
317			`almost_full : out std_logic;`
318			`full : out std_logic`
319			`);`
320			`end component;`
321
322
323
324	152	jguarin200
325	151	jguarin200
326
327	153	jguarin200
328
329
330			`type apCamera is record`
331			`resx,resy : integer;`
332			`width,height : real;`
333			`dist : real;`
334			`end record;`
335
336			`--! Función que convierte un std_logic_vector en un numero entero`
337			`function ap_slv2int(sl:std_logic_vector) return integer;`
338
339			`--! Función que convierte un número flotante IEE754 single float, en un número std_logic_vector.`
340			`function ap_fp2slv (f:real) return std_logic_vector;`
341
342			`--! Función que convierte un número std_logic_vector en un ieee754 single float.`
343			`function ap_slv2fp (sl:std_logic_vector) return real;`
344
345			`--! Función que devuelve un vector en punto flotante IEEE754 a través de un`
346			`function ap_slv_calc_xyvec (x,y:integer; cam:apCamera) return v3f;`
347
348	156	jguarin200	`--! Función que devuelve una cadena con el número flotante IEEE 754 ó a una cadena de cifras hexadecimales.`
349	160	jguarin200	`procedure ap_slvf2string(l:inout line;sl:std_logic_vector);`
350			`procedure ap_slv2hex (l:inout line;h:in std_logic_vector) ;`
351	153	jguarin200
352
353	156	jguarin200
354			`--! Función que devuelve una cadena con los componentes de un vector R3 en punto flotante IEEE754`
355	160	jguarin200	`procedure ap_v3f2string(l:inout line;v:in v3f);`
356	173	jguarin200	`procedure ap_xfp032string(l:inout line;vb03:in vectorblock03);`
357	157	jguarin200
358			`--! Función que formatea una instrucción`
359	161	jguarin200	`function ap_format_instruction(i:string;ac_o,ac_f,bd_o,bd_f:std_logic_vector;comb:std_logic) return std_logic_vector;`
360	157	jguarin200
361			`--! Función que devuelve una cadena de caracteres de un solo caracter con el valor de un bit std_logic`
362	160	jguarin200	`procedure ap_sl2string(l:inout line;s:std_logic);`
363
364	168	jguarin200	`--! Procedimiento para mostrar vectores en forma de arreglos de flotantes`
365	160	jguarin200	`procedure ap_xfp122string(l:inout line;vb12:in vectorblock12);`
366			`procedure ap_xfp082string(l:inout line;vb08:in vectorblock08);`
367			`procedure ap_xfp062string(l:inout line;vb06:in vectorblock06);`
368			`procedure ap_xfp042string(l:inout line;vb04:in vectorblock04);`
369	168	jguarin200	`procedure ap_xfp022string(l:inout line;vb02:in vectorblock02);`
370
371	156	jguarin200
372	151	jguarin200	`end package;`
373	153	jguarin200
374
375			`package body arithpack is`
376	160	jguarin200
377	168	jguarin200	`procedure ap_xfp022string(l:inout line; vb02:in vectorblock02) is`
378			`begin`
379			`for i in 01 downto 0 loop`
380			`write(l,string'(" ["&integer'image(i)&"]"));`
381			`write(l,string'(" "));`
382			`ap_slvf2string(l,vb02(i));`
383			`end loop;`
384
385			`end procedure;`
386	160	jguarin200	`procedure ap_xfp122string(l:inout line; vb12:in vectorblock12) is`
387	153	jguarin200
388	160	jguarin200	`begin`
389			`for i in 11 downto 0 loop`
390	168	jguarin200	`write(l,string'(" ["&integer'image(i)&"]"));`
391	160	jguarin200	`write(l,string'(" "));`
392			`ap_slvf2string(l,vb12(i));`
393			`end loop;`
394			`end procedure;`
395
396			`procedure ap_xfp082string(l:inout line; vb08:in vectorblock08) is`
397
398			`begin`
399			`for i in 07 downto 0 loop`
400			`write(l,string'(" ["&integer'image(i)&"]"));`
401			`write(l,string'(" "));`
402			`ap_slvf2string(l,vb08(i));`
403			`end loop;`
404			`end procedure;`
405
406			`procedure ap_xfp062string(l:inout line; vb06:in vectorblock06) is`
407
408			`begin`
409			`for i in 05 downto 0 loop`
410	168	jguarin200	`write(l,string'(" ["&integer'image(i)&"]"));`
411	160	jguarin200	`write(l,string'(" "));`
412			`ap_slvf2string(l,vb06(i));`
413			`end loop;`
414			`end procedure;`
415
416			`procedure ap_xfp042string(l:inout line; vb04:in vectorblock04) is`
417
418			`begin`
419			`for i in 03 downto 0 loop`
420	168	jguarin200	`write(l,string'(" ["&integer'image(i)&"]"));`
421	160	jguarin200	`write(l,string'(" "));`
422			`ap_slvf2string(l,vb04(i));`
423			`end loop;`
424			`end procedure;`
425
426
427			`procedure ap_sl2string(l:inout line; s:in std_logic)is`
428	157	jguarin200	`variable tmp:string(1 to 1);`
429			`begin`
430
431			`case s is`
432			`when '1' =>`
433			`tmp:="1";`
434			`when '0' =>`
435			`tmp:="0";`
436			`when 'U' =>`
437			`tmp:="U";`
438			`when 'X' =>`
439			`tmp:="X";`
440			`when 'Z' =>`
441			`tmp:="Z";`
442			`when 'W' =>`
443			`tmp:="W";`
444			`when 'L' =>`
445			`tmp:="L";`
446			`when 'H' =>`
447			`tmp:="H";`
448			`when others =>`
449			`tmp:="-"; -- Don't care`
450			`end case;`
451	168	jguarin200	`write(l,string'(" "));`
452	160	jguarin200	`write(l,string'(tmp));`
453	168	jguarin200	`write(l,string'(" "));`
454	157	jguarin200
455	160	jguarin200
456
457			`end procedure;`
458	157	jguarin200
459	161	jguarin200	`function ap_format_instruction(i:string;ac_o,ac_f,bd_o,bd_f:std_logic_vector;comb:std_logic) return std_logic_vector is`
460	157	jguarin200
461			`alias aco : std_logic_vector (4 downto 0) is ac_o;`
462			`alias acf : std_logic_vector (4 downto 0) is ac_f;`
463			`alias bdo : std_logic_vector (4 downto 0) is bd_o;`
464			`alias bdf : std_logic_vector (4 downto 0) is bd_f;`
465			`variable ins : std_logic_vector (31 downto 0);`
466			`alias it : string (1 to 3) is i;`
467			`begin`
468
469			`case it is`
470			`when "mag" =>`
471			`ins(31 downto 29) := "100";`
472	160	jguarin200	`ins(04 downto 00) := '1'&x"8";`
473	157	jguarin200	`when "nrm" =>`
474	163	jguarin200	`ins(31 downto 29) := "110";`
475	160	jguarin200	`ins(04 downto 00) := '1'&x"d";`
476	157	jguarin200	`when "add" =>`
477			`ins(31 downto 29) := "001";`
478	160	jguarin200	`ins(04 downto 00) := '0'&x"a";`
479	157	jguarin200	`when "sub" =>`
480			`ins(31 downto 29) := "011";`
481	160	jguarin200	`ins(04 downto 00) := '0'&x"a";`
482	157	jguarin200	`when "dot" =>`
483			`ins(31 downto 29) := "000";`
484	160	jguarin200	`ins(04 downto 00) := '1'&x"7";`
485	157	jguarin200	`when "crs" =>`
486			`ins(31 downto 29) := "010";`
487	160	jguarin200	`ins(04 downto 00) := '0'&x"e";`
488	157	jguarin200	`when others =>`
489			`ins(31 downto 29) := "111";`
490	160	jguarin200	`ins(04 downto 00) := '0'&x"5";`
491	157	jguarin200	`end case;`
492			`ins(28 downto 24) := aco;`
493			`ins(23 downto 19) := acf;`
494			`ins(18 downto 14) := bdo;`
495			`ins(13 downto 09) := bdf;`
496			`ins(08) := comb;`
497			`ins(07 downto 05) := "000";`
498			`return ins;`
499
500

Browse

Tools

Subversion Repositories raytrac

[/] [raytrac/] [branches/] [fp_sgdma/] [arithpack.vhd] - Blame information for rev 203