Subversion Repositories raytrac

# TCL File Generated by Component Editor 11.0

# Thu Aug 30 11:19:35 COT 2012

# DO NOT MODIFY

# +-----------------------------------

# | 

# | raytrac "raytrac" v1.0

# | null 2012.08.30.11:19:35

# | 

# | 

# | J:/code/hworkspace/raytrac/fp_sgdma/raytrac.vhd

# | 

# |    ./raytrac.vhd syn

# |    ./arithpack.vhd syn

# | 

# +-----------------------------------

# +-----------------------------------

# | request TCL package from ACDS 11.0

# | 

package require -exact sopc 11.0

# | 

# +-----------------------------------

# +-----------------------------------

# | module raytrac

# | 

set_module_property NAME raytrac

set_module_property VERSION 1.0

set_module_property INTERNAL false

set_module_property OPAQUE_ADDRESS_MAP true

set_module_property DISPLAY_NAME raytrac

set_module_property TOP_LEVEL_HDL_FILE raytrac.vhd

set_module_property TOP_LEVEL_HDL_MODULE raytrac

set_module_property INSTANTIATE_IN_SYSTEM_MODULE true

set_module_property EDITABLE true

set_module_property ANALYZE_HDL TRUE

set_module_property STATIC_TOP_LEVEL_MODULE_NAME ""

set_module_property FIX_110_VIP_PATH false

# | 

# +-----------------------------------

# +-----------------------------------

# | files

# | 

add_file raytrac.vhd SYNTHESIS

add_file arithpack.vhd SYNTHESIS

# | 

# +-----------------------------------

# +-----------------------------------

# | parameters

# | 

add_parameter wd INTEGER 32

set_parameter_property wd DEFAULT_VALUE 32

set_parameter_property wd DISPLAY_NAME wd

set_parameter_property wd TYPE INTEGER

set_parameter_property wd UNITS None

set_parameter_property wd AFFECTS_GENERATION false

set_parameter_property wd HDL_PARAMETER true

add_parameter fd INTEGER 8

set_parameter_property fd DEFAULT_VALUE 8

set_parameter_property fd DISPLAY_NAME fd

set_parameter_property fd TYPE INTEGER

set_parameter_property fd UNITS None

set_parameter_property fd AFFECTS_GENERATION false

set_parameter_property fd HDL_PARAMETER true

add_parameter mb INTEGER 4

set_parameter_property mb DEFAULT_VALUE 4

set_parameter_property mb DISPLAY_NAME mb

set_parameter_property mb TYPE INTEGER

set_parameter_property mb UNITS None

set_parameter_property mb AFFECTS_GENERATION false

set_parameter_property mb HDL_PARAMETER true

# | 

# +-----------------------------------

# +-----------------------------------

# | display items

# | 

# | 

# +-----------------------------------

# +-----------------------------------

# | connection point clock

# | 

add_interface clock clock end

set_interface_property clock clockRate 0

set_interface_property clock ENABLED true

add_interface_port clock clk clk Input 1

# | 

# +-----------------------------------

# +-----------------------------------

# | connection point rtSlave

# | 

add_interface rtSlave avalon end

set_interface_property rtSlave addressAlignment DYNAMIC

set_interface_property rtSlave addressUnits WORDS

set_interface_property rtSlave associatedClock clock

set_interface_property rtSlave associatedReset reset_sink

set_interface_property rtSlave burstOnBurstBoundariesOnly false

set_interface_property rtSlave explicitAddressSpan 0

set_interface_property rtSlave holdTime 0

set_interface_property rtSlave isMemoryDevice false

set_interface_property rtSlave isNonVolatileStorage false

set_interface_property rtSlave linewrapBursts false

set_interface_property rtSlave maximumPendingReadTransactions 0

set_interface_property rtSlave printableDevice false

set_interface_property rtSlave readLatency 2

set_interface_property rtSlave readWaitStates 0

set_interface_property rtSlave readWaitTime 0

set_interface_property rtSlave setupTime 0

set_interface_property rtSlave timingUnits Cycles

set_interface_property rtSlave writeWaitTime 0

set_interface_property rtSlave ENABLED true

add_interface_port rtSlave slave_address address Input 4

add_interface_port rtSlave slave_read read Input 1

add_interface_port rtSlave slave_write write Input 1

add_interface_port rtSlave slave_readdata readdata Output 32

add_interface_port rtSlave slave_writedata writedata Input 32

# | 

# +-----------------------------------

# +-----------------------------------

# | connection point rtMaster

# | 

add_interface rtMaster avalon start

set_interface_property rtMaster addressUnits SYMBOLS

set_interface_property rtMaster associatedClock clock

set_interface_property rtMaster associatedReset reset_sink

set_interface_property rtMaster burstOnBurstBoundariesOnly false

set_interface_property rtMaster doStreamReads false

set_interface_property rtMaster doStreamWrites false

set_interface_property rtMaster linewrapBursts false

set_interface_property rtMaster readLatency 0

set_interface_property rtMaster ENABLED true

add_interface_port rtMaster master_address address Output 32

add_interface_port rtMaster master_waitrequest waitrequest Input 1

add_interface_port rtMaster master_burstcount burstcount Output 5

add_interface_port rtMaster master_read read Output 1

add_interface_port rtMaster master_readdata readdata Input 32

add_interface_port rtMaster master_readdatavalid readdatavalid Input 1

add_interface_port rtMaster master_write write Output 1

add_interface_port rtMaster master_writedata writedata Output 32

# | 

# +-----------------------------------

# +-----------------------------------

# | connection point interrupt_sender

# | 

add_interface interrupt_sender interrupt end

set_interface_property interrupt_sender associatedAddressablePoint rtSlave

set_interface_property interrupt_sender associatedClock clock

set_interface_property interrupt_sender associatedReset reset_sink

set_interface_property interrupt_sender ENABLED true

add_interface_port interrupt_sender irq irq Output 1

# | 

# +-----------------------------------

# +-----------------------------------

# | connection point reset_sink

# | 

add_interface reset_sink reset end

set_interface_property reset_sink associatedClock clock

set_interface_property reset_sink synchronousEdges BOTH

set_interface_property reset_sink ENABLED true

add_interface_port reset_sink rst reset_n Input 1

# | 

# +-----------------------------------