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[/] [raytrac/] [trunk/] [adder.vhd] - Blame information for rev 251

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-- RAYTRAC
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-- Author Julian Andres Guarin
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-- adder.vhd
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-- This file is part of raytrac.
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-- 
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--     raytrac is free software: you can redistribute it and/or modify
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--     it under the terms of the GNU General Public License as published by
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--     the Free Software Foundation, either version 3 of the License, or
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--     (at your option) any later version.
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-- 
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--     raytrac is distributed in the hope that it will be useful,
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--     but WITHOUT ANY WARRANTY; without even the implied warranty of
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--     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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--     GNU General Public License for more details.
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-- 
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--     You should have received a copy of the GNU General Public License
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--     along with raytrac.  If not, see <http://www.gnu.org/licenses/>.
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--! Libreria de definici&oacute;n de segnales y tipos estandares, comportamiento de operadores aritmeticos y logicos.\n 
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library ieee;
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--! Paquete de definicion estandard de logica. 
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use ieee.std_logic_1164.all;
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--! Se usaran en esta descripcion los componentes del package arithpack.vhd. 
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use work.arithpack.all;
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entity adder is
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        generic (
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                width : integer := 4;
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                carry_logic : string := "CLA";
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                substractor_selector : string := "YES"
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        );
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        port (
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                a,b     : in std_logic_vector(width-1 downto 0);
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                s,ci    : in std_logic;
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                result  : out std_logic_vector(width-1 downto 0);
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                cout    : out std_logic
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        );
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end adder;
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--! @brief      Arquitectura del sumador
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architecture adder_arch of adder is
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        signal sa,p,g:  std_logic_vector(width-1 downto 0);
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        signal sCarry:  std_logic_vector(width downto 1);
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begin
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        -- Usual Structural Model / wether or not CLA/RCA is used and wether or not add/sub selector is used, this port is always instanced --
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        result(0)<= a(0) xor b(0) xor ci;
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        wide_adder:
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        if (width>1) generate
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                wide_adder_generate_loop:
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                for i in 1 to width-1 generate
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                        result(i) <= a(i) xor b(i) xor sCarry(i);
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                end generate wide_adder_generate_loop;
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        end generate wide_adder;
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        cout <= sCarry(width);
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        g<= sa and b;
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        p<= sa or b;
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        --! Si se configura una se&ntilde;al para seleccionar entre suma y resta, se generar&aacute; el circuito a continuaci&oacute;n.
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        adder_sub_logic :       -- adder substractor logic
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        if substractor_selector = "YES" generate
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                a_xor_s:
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                for i in 0 to width-1 generate
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                        sa(i) <= a(i) xor s;
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                end generate a_xor_s;
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        end generate adder_sub_Logic;
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        add_logic:      --!Si no se configura una se&ntilde;al de selecci&oacute;n entonces sencillamente se conecta a a sa.
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        if substractor_selector = "NO" generate
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                sa <= a;
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        end generate add_logic;
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        -- Conditional Instantiation / RCA/CLA Logical Blocks Generation --
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        --! Si se selecciona un ripple carry adder se instancia el siguiente circuito
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        rca_logic_block_instancing:     -- Ripple Carry Adder
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        if carry_logic="RCA" generate
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                rca_x: rca_logic_block
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                generic map (width=>width)
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                port map (
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                        p=>p,
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                        g=>g,
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                        cin=>ci,
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                        c=>sCarry
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                );
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        end generate rca_logic_block_instancing;
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        --! Si se selecciona un Carry Lookahead adder se instancia el siguiente circuito
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        cla_logic_block_instancing:     -- Carry Lookahead Adder
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        if carry_logic="CLA" generate
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                cla_x: cla_logic_block
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                generic map (width=>width)
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                port map (
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                        p=>p,
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                        g=>g,
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                        cin=>ci,
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                        c=>sCarry
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                );
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        end generate cla_logic_block_instancing;
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end adder_arch;
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