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[/] [raytrac/] [trunk/] [sqrtdiv/] [shift.vhd] - Blame information for rev 134

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------------------------------------------------
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--! @file shift.vhd
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--! @brief RayTrac TestBench
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--! @author Julián Andrés Guarín Reyes
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--------------------------------------------------
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-- RAYTRAC
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-- Author Julian Andres Guarin
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-- shift.vhd
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-- This file is part of raytrac.
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-- 
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--     raytrac is free software: you can redistribute it and/or modify
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--     it under the terms of the GNU General Public License as published by
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--     the Free Software Foundation, either version 3 of the License, or
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--     (at your option) any later version.
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-- 
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--     raytrac is distributed in the hope that it will be useful,
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--     but WITHOUT ANY WARRANTY; without even the implied warranty of
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--     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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--     GNU General Public License for more details.
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-- 
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--     You should have received a copy of the GNU General Public License
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--     along with raytrac.  If not, see <http://www.gnu.org/licenses/>
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_signed.all;
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use ieee.math_real.all;
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--! \brief Dado que cualquier n&uacute;mero entero A, se puede escribir 2^n * f, es importante obtener una representaci&oacute;n del valor de f en base 2. Una vez hallado este valor y evaluado en una funci&oacute;n bastara con realizar un corrimiento a la izquierda n bits del resultado, para calcular funciones como A^-1 o A^0.5.
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entity shifter is
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        generic (
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                address_width   : integer       := 9;
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                width                   : integer       := 32;
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                --! Cuando even shifter es "YES" se hara la busqueda del primer bit con valor 1, de izquierda a derecha, pero NO de uno en uno.
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                even_shifter    : string        := "YES"
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        );
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        port (
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                data                    : in std_logic_vector(width - 1 downto 0);
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                exp                             : out std_logic_vector(integer(ceil(log(real(width),2.0)))-1 downto 0);
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                address                 : out std_logic_vector (address_width-1 downto 0);
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                zero                    : out std_logic
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        );
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end shifter;
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architecture shifter_arch of shifter is
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begin
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        sanityLost:
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        process (data)
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                variable index: integer range-1 to width+address_width-1:=width+address_width-1;
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        begin
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                address<=(others=>'0');
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                exp<=(others=>'0');
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                zero<=data(0);
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                if even_shifter="YES" then
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                        index:=width-1;
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                else
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                        index:=width-2;
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                end if;
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                while index>=1 loop
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                        if data(index)='1' then
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                                zero<='0';
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                                exp<=CONV_STD_LOGIC_VECTOR(index, exp'high+1);
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                                if index>=address_width then
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                                        address <= data (index-1 downto index-address_width);
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                                else
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                                        address(address_width-1 downto address_width-index) <= data (index-1 downto 0);
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                                        address(address_width-index-1 downto 0) <= (others =>'0');
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                                end if;
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                                exit;
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                        end if;
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                        index:=index-2; --Boost
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                end loop;
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        end process sanityLost;
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end shifter_arch;
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