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------------------------------------------------
--! @file tb.vhd
--! @brief RayTrac TestBench
--! @author Juli&aacute;n Andr&eacute;s Guar&iacute;n Reyes
--------------------------------------------------
 
 
-- RAYTRAC
-- Author Julian Andres Guarin
-- tb.vhd
-- This file is part of raytrac.
-- 
--     raytrac is free software: you can redistribute it and/or modify
--     it under the terms of the GNU General Public License as published by
--     the Free Software Foundation, either version 3 of the License, or
--     (at your option) any later version.
-- 
--     raytrac is distributed in the hope that it will be useful,
--     but WITHOUT ANY WARRANTY; without even the implied warranty of
--     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--     GNU General Public License for more details.
-- 
--     You should have received a copy of the GNU General Public License
--     along with raytrac.  If not, see <http://www.gnu.org/licenses/>
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
use std.textio.all;
use work.arithpack.all;
 
 
entity tb is
 
end tb;
 
 
architecture tb_arch of tb is
 
        signal qa       : std_logic_vector (53 downto 0);
        signal qb       : std_logic_vector (53 downto 0);
        signal qc       : std_logic_vector (53 downto 0);
        signal qd       : std_logic_vector (53 downto 0);
        signal clock,rst,ena: std_logic;
        signal opcode,addcode:std_logic;
        signal dp0,dp1,cpx,cpy,cpz : std_logic_vector(31 downto 0);
        signal address: std_logic_vector (8 downto 0);
        signal opadd : std_logic_vector(1 downto 0);
 
begin
 
        --! Generador de clock.
        clk_inst: clock_gen
        port map (clock,rst); -- Instanciacion simple.
 
        --! Device Under Test
        dude: raytrac
        generic map ("YES","YES")       -- Test bench y Entrada registrada, pues la ROM no tiene salida registrada.
        port map(qa,qb,qc,qd,opadd(1),opadd(0),clock,rst,ena,cpx,cpy,cpz,dp0,dp1);
 
        --! Procedimiento para escribir los resultados del testbench
        sampleproc: process
                variable buff : line;
                file rombuff : text open write_mode is "TRACE_rom_content.csv";
                variable stop : integer := 0;
        begin
 
                write(buff,string'("#ROM memories test benching"));
                writeline(rombuff, buff);
                write(buff,string'("#{Time} {AddressR} {Opc Adc} {Ax,Ay,Az} {Bx,By,Bz} {Cx,Cy,Cz} {Dx,Dy,Dz}"));
                writeline(rombuff, buff);
 
                wait for 5 ns;
                wait until rst=not(rstMasterValue);
                wait until clock='1';
                wait for tclk2+tclk4; --! Garantizar la estabilidad de los datos que se van a observar en la salida.
                displayRom:
                loop
                        write (buff,string'("{"));
                        write (buff,now,unit =>ns);
                        write (buff,string'("}{"));
                        hexwrite_0 (buff,address(8 downto 0));
                        write (buff,string'("}{"));
                        hexwrite_0 (buff,opadd);
                        write (buff,string'("} { "));
                        hexwrite_0 (buff,qa(17 downto 0));
                        write (buff,string'(","));
                        hexwrite_0 (buff,qa(35 downto 18));
                        write (buff,string'(","));
                        hexwrite_0 (buff,qa(53 downto 36));
                        write (buff,string'(" } "));
                        write (buff,string'(" { "));
                        hexwrite_0 (buff,qb(17 downto 0));
                        write (buff,string'(","));
                        hexwrite_0 (buff,qb(35 downto 18));
                        write (buff,string'(","));
                        hexwrite_0 (buff,qb(53 downto 36));
                        write (buff,string'(" } "));
                        write (buff,string'(" { "));
                        hexwrite_0 (buff,qc(17 downto 0));
                        write (buff,string'(","));
                        hexwrite_0 (buff,qc(35 downto 18));
                        write (buff,string'(","));
                        hexwrite_0 (buff,qc(53 downto 36));
                        write (buff,string'(" } "));
                        write (buff,string'(" { "));
                        hexwrite_0 (buff,qd(17 downto 0));
                        write (buff,string'(","));
                        hexwrite_0 (buff,qd(35 downto 18));
                        write (buff,string'(","));
                        hexwrite_0 (buff,qd(53 downto 36));
                        write (buff,string'(" } "));
                        writeline(rombuff,buff);
                        wait for tclk;
 
 
                        -- STOP FORREST!
                        if opadd=X"2" and address=X"00"  then
                                if stop=1 then
                                        wait;
                                else
                                        stop:=1;
                                end if;
                        end if;
 
                end loop displayRom;
 
        end process sampleproc;
 
 
 
        --! Descripcion del test: 512 x (2/clock) productos punto y 1024 x (1/clock) productos cruz.
        thetest:
        process (clock,rst)
                variable buff : line;
                file rombuff : text open write_mode is "TRACE_state_content";
                variable tbs : tbState;
        begin
 
                if rst=rstMasterValue then
 
                        opcode  <= '0';
                        addcode <= '1';
                        tbs := abcd;
                        ena <= '1';
                        address <= (others => '0');
                elsif clock'event and clock = '1' then
 
                        opadd <= opcode & addcode;
 
                        case tbs is
                                when abcd  =>
                                        if address = X"1FF" then
                                                write (buff,now,unit => ns);
                                                write (buff,string'(" S: abcd => axb"));
                                                writeline (rombuff,buff);
                                                tbs := axb;
                                                opcode <= '1';
                                                addcode <= not(addcode);
                                        end if;
                                        address <= address + 1;
 
                                when axb =>
                                        write (buff,now,unit => ns);
                                        write (buff,string'(" S: axb => cxd"));
                                        writeline (rombuff,buff);
 
                                        tbs := cxd;
                                        addcode <= not(addcode);
                                when cxd =>
 
                                        addcode <= not(addcode);
                                        if address=X"1FF" then
                                                write (buff,now,unit => ns);
                                                write (buff,string'(" S: cxd => stop"));
                                                writeline (rombuff,buff);
                                                tbs := stop;
                                        else
                                                write (buff,now,unit => ns);
                                                write (buff,string'(" S: cxd => axb"));
                                                writeline (rombuff,buff);
 
                                                tbs := axb;
                                        end if;
                                        address  <= address + 1;
                                when others =>
                                        null;
                        end case;
 
                end if;
        end process thetest;
 
        --! 512x18 rom con los componentes ax.
        AX : altsyncram
        generic map (
                address_aclr_a => "NONE",
                clock_enable_input_a => "BYPASS",
                clock_enable_output_a => "BYPASS",
                init_file => "memax.mif",
                intended_device_family => "Cyclone III",
                lpm_hint => "ENABLE_RUNTIME_MOD=NO",
                lpm_type => "altsyncram",
                numwords_a => 512,
                operation_mode => "ROM",
                outdata_aclr_a => "NONE",
                outdata_reg_a => "UNREGISTERED",
                ram_block_type => "M9K",
                widthad_a => 9,
                width_a => 18,
                width_byteena_a => 1
        )
        port map (
                clock0 => clock,
                address_a => address,
                q_a => qa (17 downto 0)
        );
 
        --! 512x18 rom con los componentes ay.
        AY : altsyncram
        generic map (
                address_aclr_a => "NONE",
                clock_enable_input_a => "BYPASS",
                clock_enable_output_a => "BYPASS",
                init_file => ".\memay.mif",
                intended_device_family => "Cyclone III",
                lpm_hint => "ENABLE_RUNTIME_MOD=NO",
                lpm_type => "altsyncram",
                numwords_a => 512,
                operation_mode => "ROM",
                outdata_aclr_a => "NONE",
                outdata_reg_a => "UNREGISTERED",
                ram_block_type => "M9K",
                widthad_a => 9,
                width_a => 18,
                width_byteena_a => 1
        )
        port map (
                clock0 => clock,
                address_a => address,
                q_a => qa (35 downto 18)
        );
 
        --! 512x18 rom con los componentes az.
        AZ : altsyncram
        generic map (
                address_aclr_a => "NONE",
                clock_enable_input_a => "BYPASS",
                clock_enable_output_a => "BYPASS",
                init_file => ".\memaz.mif",
                intended_device_family => "Cyclone III",
                lpm_hint => "ENABLE_RUNTIME_MOD=NO",
                lpm_type => "altsyncram",
                numwords_a => 512,
                operation_mode => "ROM",
                outdata_aclr_a => "NONE",
                outdata_reg_a => "UNREGISTERED",
                ram_block_type => "M9K",
                widthad_a => 9,
                width_a => 18,
                width_byteena_a => 1
        )
        port map (
                clock0 => clock,
                address_a => address,
                q_a => qa (53 downto 36)
        );
 
        --! 512x18 rom con los componentes bx.
        BX : altsyncram
        generic map (
                address_aclr_a => "NONE",
                clock_enable_input_a => "BYPASS",
                clock_enable_output_a => "BYPASS",
                init_file => ".\membx.mif",
                intended_device_family => "Cyclone III",
                lpm_hint => "ENABLE_RUNTIME_MOD=NO",
                lpm_type => "altsyncram",
                numwords_a => 512,
                operation_mode => "ROM",
                outdata_aclr_a => "NONE",
                outdata_reg_a => "UNREGISTERED",
                ram_block_type => "M9K",
                widthad_a => 9,
                width_a => 18,
                width_byteena_a => 1
        )
        port map (
                clock0 => clock,
                address_a => address,
                q_a => qb (17 downto 0)
        );
 
        --! 512x18 rom con los componentes by.
        BY : altsyncram
        generic map (
                address_aclr_a => "NONE",
                clock_enable_input_a => "BYPASS",
                clock_enable_output_a => "BYPASS",
                init_file => ".\memby.mif",
                intended_device_family => "Cyclone III",
                lpm_hint => "ENABLE_RUNTIME_MOD=NO",
                lpm_type => "altsyncram",
                numwords_a => 512,
                operation_mode => "ROM",
                outdata_aclr_a => "NONE",
                outdata_reg_a => "UNREGISTERED",
                ram_block_type => "M9K",
                widthad_a => 9,
                width_a => 18,
                width_byteena_a => 1
        )
        port map (
                clock0 => clock,
                address_a => address,
                q_a => qb (35 downto 18)
        );
 
        --! 512x18 rom con los componentes bz.
        BZ : altsyncram
        generic map (
                address_aclr_a => "NONE",
                clock_enable_input_a => "BYPASS",
                clock_enable_output_a => "BYPASS",
                init_file => ".\membz.mif",
                intended_device_family => "Cyclone III",
                lpm_hint => "ENABLE_RUNTIME_MOD=NO",
                lpm_type => "altsyncram",
                numwords_a => 512,
                operation_mode => "ROM",
                outdata_aclr_a => "NONE",
                outdata_reg_a => "UNREGISTERED",
                ram_block_type => "M9K",
                widthad_a => 9,
                width_a => 18,
                width_byteena_a => 1
        )
        port map (
                clock0 => clock,
                address_a => address,
                q_a => qb (53 downto 36)
        );
 
        --! 512x18 rom con los componentes cx.
        CX : altsyncram
        generic map (
                address_aclr_a => "NONE",
                clock_enable_input_a => "BYPASS",
                clock_enable_output_a => "BYPASS",
                init_file => ".\memcx.mif",
                intended_device_family => "Cyclone III",
                lpm_hint => "ENABLE_RUNTIME_MOD=NO",
                lpm_type => "altsyncram",
                numwords_a => 512,
                operation_mode => "ROM",
                outdata_aclr_a => "NONE",
                outdata_reg_a => "UNREGISTERED",
                ram_block_type => "M9K",
                widthad_a => 9,
                width_a => 18,
                width_byteena_a => 1
        )
        port map (
                clock0 => clock,
                address_a => address,
                q_a => qc (17 downto 0)
        );
 
        --! 512x18 rom con los componentes cy.
        CY : altsyncram
        generic map (
                address_aclr_a => "NONE",
                clock_enable_input_a => "BYPASS",
                clock_enable_output_a => "BYPASS",
                init_file => ".\memcy.mif",
                intended_device_family => "Cyclone III",
                lpm_hint => "ENABLE_RUNTIME_MOD=NO",
                lpm_type => "altsyncram",
                numwords_a => 512,
                operation_mode => "ROM",
                outdata_aclr_a => "NONE",
                outdata_reg_a => "UNREGISTERED",
                ram_block_type => "M9K",
                widthad_a => 9,
                width_a => 18,
                width_byteena_a => 1
        )
        port map (
                clock0 => clock,
                address_a => address,
                q_a => qc (35 downto 18)
        );
 
        --! 512x18 rom con los componentes cz.
        CZ : altsyncram
        generic map (
                address_aclr_a => "NONE",
                clock_enable_input_a => "BYPASS",
                clock_enable_output_a => "BYPASS",
                init_file => ".\memcz.mif",
                intended_device_family => "Cyclone III",
                lpm_hint => "ENABLE_RUNTIME_MOD=NO",
                lpm_type => "altsyncram",
                numwords_a => 512,
                operation_mode => "ROM",
                outdata_aclr_a => "NONE",
                outdata_reg_a => "UNREGISTERED",
                ram_block_type => "M9K",
                widthad_a => 9,
                width_a => 18,
                width_byteena_a => 1
        )
        port map (
                clock0 => clock,
                address_a => address,
                q_a => qc (53 downto 36)
        );
 
        --! 512x18 rom con los componentes dx.
        DX : altsyncram
        generic map (
                address_aclr_a => "NONE",
                clock_enable_input_a => "BYPASS",
                clock_enable_output_a => "BYPASS",
                init_file => ".\memdx.mif",
                intended_device_family => "Cyclone III",
                lpm_hint => "ENABLE_RUNTIME_MOD=NO",
                lpm_type => "altsyncram",
                numwords_a => 512,
                operation_mode => "ROM",
                outdata_aclr_a => "NONE",
                outdata_reg_a => "UNREGISTERED",
                ram_block_type => "M9K",
                widthad_a => 9,
                width_a => 18,
                width_byteena_a => 1
        )
        port map (
                clock0 => clock,
                address_a => address,
                q_a => qd (17 downto 0)
        );
 
        --! 512x18 rom con los componentes dy.
        DY : altsyncram
        generic map (
                address_aclr_a => "NONE",
                clock_enable_input_a => "BYPASS",
                clock_enable_output_a => "BYPASS",
                init_file => ".\memdy.mif",
                intended_device_family => "Cyclone III",
                lpm_hint => "ENABLE_RUNTIME_MOD=NO",
                lpm_type => "altsyncram",
                numwords_a => 512,
                operation_mode => "ROM",
                outdata_aclr_a => "NONE",
                outdata_reg_a => "UNREGISTERED",
                ram_block_type => "M9K",
                widthad_a => 9,
                width_a => 18,
                width_byteena_a => 1
        )
        port map (
                clock0 => clock,
                address_a => address,
                q_a => qd (35 downto 18)
        );
 
        --! 512x18 rom con los componentes dz.
        DZ : altsyncram
        generic map (
                address_aclr_a => "NONE",
                clock_enable_input_a => "BYPASS",
                clock_enable_output_a => "BYPASS",
                init_file => ".\memdz.mif",
                intended_device_family => "Cyclone III",
                lpm_hint => "ENABLE_RUNTIME_MOD=NO",
                lpm_type => "altsyncram",
                numwords_a => 512,
                operation_mode => "ROM",
                outdata_aclr_a => "NONE",
                outdata_reg_a => "UNREGISTERED",
                ram_block_type => "M9K",
                widthad_a => 9,
                width_a => 18,
                width_byteena_a => 1
        )
        port map (
                clock0 => clock,
                address_a => address,
                q_a => qd (53 downto 36)
        );
 
end tb_arch;
 

Line No.	Rev	Author	Line
1	49	jguarin200	`------------------------------------------------`
2			`--! @file tb.vhd`
3			`--! @brief RayTrac TestBench`
4	52	jguarin200	`--! @author Julián Andrés Guarín Reyes`
5	49	jguarin200	`--------------------------------------------------`
6
7
8			`-- RAYTRAC`
9			`-- Author Julian Andres Guarin`
10			`-- tb.vhd`
11			`-- This file is part of raytrac.`
12			`--`
13			`-- raytrac is free software: you can redistribute it and/or modify`
14			`-- it under the terms of the GNU General Public License as published by`
15			`-- the Free Software Foundation, either version 3 of the License, or`
16			`-- (at your option) any later version.`
17			`--`
18			`-- raytrac is distributed in the hope that it will be useful,`
19			`-- but WITHOUT ANY WARRANTY; without even the implied warranty of`
20			`-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
21			`-- GNU General Public License for more details.`
22			`--`
23			`-- You should have received a copy of the GNU General Public License`
24			`-- along with raytrac. If not, see <http://www.gnu.org/licenses/>`
25
26			`library ieee;`
27			`use ieee.std_logic_1164.all;`
28			`use ieee.std_logic_unsigned.all;`
29
30			`use std.textio.all;`
31			`use work.arithpack.all;`
32
33
34			`entity tb is`
35
36			`end tb;`
37
38
39			`architecture tb_arch of tb is`
40
41			`signal qa : std_logic_vector (53 downto 0);`
42			`signal qb : std_logic_vector (53 downto 0);`
43			`signal qc : std_logic_vector (53 downto 0);`
44			`signal qd : std_logic_vector (53 downto 0);`
45			`signal clock,rst,ena: std_logic;`
46			`signal opcode,addcode:std_logic;`
47			`signal dp0,dp1,cpx,cpy,cpz : std_logic_vector(31 downto 0);`
48			`signal address: std_logic_vector (8 downto 0);`
49	51	jguarin200	`signal opadd : std_logic_vector(1 downto 0);`
50	49	jguarin200
51			`begin`
52	51	jguarin200
53	49	jguarin200	`--! Generador de clock.`
54			`clk_inst: clock_gen`
55			`port map (clock,rst); -- Instanciacion simple.`
56
57			`--! Device Under Test`
58			`dude: raytrac`
59	50	jguarin200	`generic map ("YES","YES") -- Test bench y Entrada registrada, pues la ROM no tiene salida registrada.`
60	51	jguarin200	`port map(qa,qb,qc,qd,opadd(1),opadd(0),clock,rst,ena,cpx,cpy,cpz,dp0,dp1);`
61	49	jguarin200
62			`--! Procedimiento para escribir los resultados del testbench`
63			`sampleproc: process`
64			`variable buff : line;`
65	52	jguarin200	`file rombuff : text open write_mode is "TRACE_rom_content.csv";`
66	53	jguarin200	`variable stop : integer := 0;`
67	49	jguarin200	`begin`
68	51	jguarin200
69	53	jguarin200	`write(buff,string'("#ROM memories test benching"));`
70	49	jguarin200	`writeline(rombuff, buff);`
71	53	jguarin200	`write(buff,string'("#{Time} {AddressR} {Opc Adc} {Ax,Ay,Az} {Bx,By,Bz} {Cx,Cy,Cz} {Dx,Dy,Dz}"));`
72			`writeline(rombuff, buff);`
73
74	49	jguarin200	`wait for 5 ns;`
75			`wait until rst=not(rstMasterValue);`
76			`wait until clock='1';`
77			`wait for tclk2+tclk4; --! Garantizar la estabilidad de los datos que se van a observar en la salida.`
78			`displayRom:`
79			`loop`
80	53	jguarin200	`write (buff,string'("{"));`
81	49	jguarin200	`write (buff,now,unit =>ns);`
82	53	jguarin200	`write (buff,string'("}{"));`
83	51	jguarin200	`hexwrite_0 (buff,address(8 downto 0));`
84	53	jguarin200	`write (buff,string'("}{"));`
85	51	jguarin200	`hexwrite_0 (buff,opadd);`
86	53	jguarin200	`write (buff,string'("} { "));`
87	50	jguarin200	`hexwrite_0 (buff,qa(17 downto 0));`
88	52	jguarin200	`write (buff,string'(","));`
89	50	jguarin200	`hexwrite_0 (buff,qa(35 downto 18));`
90	52	jguarin200	`write (buff,string'(","));`
91	50	jguarin200	`hexwrite_0 (buff,qa(53 downto 36));`
92	52	jguarin200	`write (buff,string'(" } "));`
93			`write (buff,string'(" { "));`
94	50	jguarin200	`hexwrite_0 (buff,qb(17 downto 0));`
95	52	jguarin200	`write (buff,string'(","));`
96	50	jguarin200	`hexwrite_0 (buff,qb(35 downto 18));`
97	52	jguarin200	`write (buff,string'(","));`
98	50	jguarin200	`hexwrite_0 (buff,qb(53 downto 36));`
99	52	jguarin200	`write (buff,string'(" } "));`
100			`write (buff,string'(" { "));`
101	50	jguarin200	`hexwrite_0 (buff,qc(17 downto 0));`
102	52	jguarin200	`write (buff,string'(","));`
103	50	jguarin200	`hexwrite_0 (buff,qc(35 downto 18));`
104	52	jguarin200	`write (buff,string'(","));`
105	50	jguarin200	`hexwrite_0 (buff,qc(53 downto 36));`
106	52	jguarin200	`write (buff,string'(" } "));`
107			`write (buff,string'(" { "));`
108	50	jguarin200	`hexwrite_0 (buff,qd(17 downto 0));`
109	52	jguarin200	`write (buff,string'(","));`
110	50	jguarin200	`hexwrite_0 (buff,qd(35 downto 18));`
111	52	jguarin200	`write (buff,string'(","));`
112	50	jguarin200	`hexwrite_0 (buff,qd(53 downto 36));`
113	52	jguarin200	`write (buff,string'(" } "));`
114	49	jguarin200	`writeline(rombuff,buff);`
115			`wait for tclk;`
116	53	jguarin200
117
118			`-- STOP FORREST!`
119			`if opadd=X"2" and address=X"00" then`
120			`if stop=1 then`
121			`wait;`
122			`else`
123			`stop:=1;`
124			`end if;`
125			`end if;`
126
127	49	jguarin200	`end loop displayRom;`
128
129			`end process sampleproc;`
130
131
132	50	jguarin200
133	49	jguarin200	`--! Descripcion del test: 512 x (2/clock) productos punto y 1024 x (1/clock) productos cruz.`
134			`thetest:`
135			`process (clock,rst)`
136	51	jguarin200	`variable buff : line;`
137			`file rombuff : text open write_mode is "TRACE_state_content";`
138	49	jguarin200	`variable tbs : tbState;`
139			`begin`
140
141			`if rst=rstMasterValue then`
142	51	jguarin200
143	49	jguarin200	`opcode <= '0';`
144			`addcode <= '1';`
145			`tbs := abcd;`
146			`ena <= '1';`
147			`address <= (others => '0');`
148			`elsif clock'event and clock = '1' then`
149
150	51	jguarin200	`opadd <= opcode & addcode;`
151
152	49	jguarin200	`case tbs is`
153			`when abcd =>`
154			`if address = X"1FF" then`
155	51	jguarin200	`write (buff,now,unit => ns);`
156			`write (buff,string'(" S: abcd => axb"));`
157			`writeline (rombuff,buff);`
158	49	jguarin200	`tbs := axb;`
159			`opcode <= '1';`
160			`addcode <= not(addcode);`
161			`end if;`
162			`address <= address + 1;`
163
164	51	jguarin200	`when axb =>`
165			`write (buff,now,unit => ns);`
166			`write (buff,string'(" S: axb => cxd"));`
167			`writeline (rombuff,buff);`
168
169	49	jguarin200	`tbs := cxd;`
170			`addcode <= not(addcode);`
171			`when cxd =>`
172	51	jguarin200
173	49	jguarin200	`addcode <= not(addcode);`
174	51	jguarin200	`if address=X"1FF" then`
175			`write (buff,now,unit => ns);`
176			`write (buff,string'(" S: cxd => stop"));`
177			`writeline (rombuff,buff);`
178			`tbs := stop;`
179			`else`
180			`write (buff,now,unit => ns);`
181			`write (buff,string'(" S: cxd => axb"));`
182			`writeline (rombuff,buff);`
183
184			`tbs := axb;`
185	49	jguarin200	`end if;`
186	51	jguarin200	`address <= address + 1;`
187	49	jguarin200	`when others =>`
188			`null;`
189			`end case;`
190
191			`end if;`
192			`end process thetest;`
193
194			`--! 512x18 rom con los componentes ax.`
195			`AX : altsyncram`
196			`generic map (`
197			`address_aclr_a => "NONE",`
198			`clock_enable_input_a => "BYPASS",`
199			`clock_enable_output_a => "BYPASS",`
200			`init_file => "memax.mif",`
201			`intended_device_family => "Cyclone III",`
202			`lpm_hint => "ENABLE_RUNTIME_MOD=NO",`
203			`lpm_type => "altsyncram",`
204			`numwords_a => 512,`
205			`operation_mode => "ROM",`
206			`outdata_aclr_a => "NONE",`
207			`outdata_reg_a => "UNREGISTERED",`
208			`ram_block_type => "M9K",`
209			`widthad_a => 9,`
210			`width_a => 18,`
211			`width_byteena_a => 1`
212			`)`
213			`port map (`
214			`clock0 => clock,`
215			`address_a => address,`
216			`q_a => qa (17 downto 0)`
217			`);`
218
219			`--! 512x18 rom con los componentes ay.`
220			`AY : altsyncram`
221			`generic map (`
222			`address_aclr_a => "NONE",`
223			`clock_enable_input_a => "BYPASS",`
224			`clock_enable_output_a => "BYPASS",`
225			`init_file => ".\memay.mif",`
226			`intended_device_family => "Cyclone III",`
227			`lpm_hint => "ENABLE_RUNTIME_MOD=NO",`
228			`lpm_type => "altsyncram",`
229			`numwords_a => 512,`
230			`operation_mode => "ROM",`
231			`outdata_aclr_a => "NONE",`
232	50	jguarin200	`outdata_reg_a => "UNREGISTERED",`
233	49	jguarin200	`ram_block_type => "M9K",`
234			`widthad_a => 9,`
235			`width_a => 18,`
236			`width_byteena_a => 1`
237			`)`
238			`port map (`
239			`clock0 => clock,`
240			`address_a => address,`
241			`q_a => qa (35 downto 18)`
242			`);`
243
244			`--! 512x18 rom con los componentes az.`
245			`AZ : altsyncram`
246			`generic map (`
247			`address_aclr_a => "NONE",`
248			`clock_enable_input_a => "BYPASS",`
249			`clock_enable_output_a => "BYPASS",`
250			`init_file => ".\memaz.mif",`
251			`intended_device_family => "Cyclone III",`
252			`lpm_hint => "ENABLE_RUNTIME_MOD=NO",`
253			`lpm_type => "altsyncram",`
254			`numwords_a => 512,`
255			`operation_mode => "ROM",`
256			`outdata_aclr_a => "NONE",`
257	50	jguarin200	`outdata_reg_a => "UNREGISTERED",`
258	49	jguarin200	`ram_block_type => "M9K",`
259			`widthad_a => 9,`
260			`width_a => 18,`
261			`width_byteena_a => 1`
262			`)`
263			`port map (`
264			`clock0 => clock,`
265			`address_a => address,`
266			`q_a => qa (53 downto 36)`
267			`);`
268
269			`--! 512x18 rom con los componentes bx.`
270			`BX : altsyncram`
271			`generic map (`
272			`address_aclr_a => "NONE",`
273			`clock_enable_input_a => "BYPASS",`
274			`clock_enable_output_a => "BYPASS",`
275			`init_file => ".\membx.mif",`
276			`intended_device_family => "Cyclone III",`
277			`lpm_hint => "ENABLE_RUNTIME_MOD=NO",`
278			`lpm_type => "altsyncram",`
279			`numwords_a => 512,`
280			`operation_mode => "ROM",`
281			`outdata_aclr_a => "NONE",`
282	50	jguarin200	`outdata_reg_a => "UNREGISTERED",`
283	49	jguarin200	`ram_block_type => "M9K",`
284			`widthad_a => 9,`
285			`width_a => 18,`
286			`width_byteena_a => 1`
287			`)`
288			`port map (`
289			`clock0 => clock,`
290			`address_a => address,`
291			`q_a => qb (17 downto 0)`
292			`);`
293
294			`--! 512x18 rom con los componentes by.`
295			`BY : altsyncram`
296			`generic map (`
297			`address_aclr_a => "NONE",`
298			`clock_enable_input_a => "BYPASS",`
299			`clock_enable_output_a => "BYPASS",`
300			`init_file => ".\memby.mif",`
301			`intended_device_family => "Cyclone III",`
302			`lpm_hint => "ENABLE_RUNTIME_MOD=NO",`
303			`lpm_type => "altsyncram",`
304			`numwords_a => 512,`
305			`operation_mode => "ROM",`
306			`outdata_aclr_a => "NONE",`
307	50	jguarin200	`outdata_reg_a => "UNREGISTERED",`
308	49	jguarin200	`ram_block_type => "M9K",`
309			`widthad_a => 9,`
310			`width_a => 18,`
311			`width_byteena_a => 1`
312			`)`
313			`port map (`
314			`clock0 => clock,`
315			`address_a => address,`
316			`q_a => qb (35 downto 18)`
317			`);`
318
319			`--! 512x18 rom con los componentes bz.`
320			`BZ : altsyncram`
321			`generic map (`
322			`address_aclr_a => "NONE",`
323			`clock_enable_input_a => "BYPASS",`
324			`clock_enable_output_a => "BYPASS",`
325			`init_file => ".\membz.mif",`
326			`intended_device_family => "Cyclone III",`
327			`lpm_hint => "ENABLE_RUNTIME_MOD=NO",`
328			`lpm_type => "altsyncram",`
329			`numwords_a => 512,`
330			`operation_mode => "ROM",`
331			`outdata_aclr_a => "NONE",`
332	50	jguarin200	`outdata_reg_a => "UNREGISTERED",`
333	49	jguarin200	`ram_block_type => "M9K",`
334			`widthad_a => 9,`
335			`width_a => 18,`
336			`width_byteena_a => 1`
337			`)`
338			`port map (`
339			`clock0 => clock,`
340			`address_a => address,`
341			`q_a => qb (53 downto 36)`
342			`);`
343
344			`--! 512x18 rom con los componentes cx.`
345			`CX : altsyncram`
346			`generic map (`
347			`address_aclr_a => "NONE",`
348			`clock_enable_input_a => "BYPASS",`
349			`clock_enable_output_a => "BYPASS",`
350			`init_file => ".\memcx.mif",`
351			`intended_device_family => "Cyclone III",`
352			`lpm_hint => "ENABLE_RUNTIME_MOD=NO",`
353			`lpm_type => "altsyncram",`
354			`numwords_a => 512,`
355			`operation_mode => "ROM",`
356			`outdata_aclr_a => "NONE",`
357			`outdata_reg_a => "UNREGISTERED",`
358			`ram_block_type => "M9K",`
359			`widthad_a => 9,`
360			`width_a => 18,`
361			`width_byteena_a => 1`
362			`)`
363			`port map (`
364			`clock0 => clock,`
365			`address_a => address,`
366			`q_a => qc (17 downto 0)`
367			`);`
368
369			`--! 512x18 rom con los componentes cy.`
370			`CY : altsyncram`
371			`generic map (`
372			`address_aclr_a => "NONE",`
373			`clock_enable_input_a => "BYPASS",`
374			`clock_enable_output_a => "BYPASS",`
375			`init_file => ".\memcy.mif",`
376			`intended_device_family => "Cyclone III",`
377			`lpm_hint => "ENABLE_RUNTIME_MOD=NO",`
378			`lpm_type => "altsyncram",`
379			`numwords_a => 512,`
380			`operation_mode => "ROM",`
381			`outdata_aclr_a => "NONE",`
382	50	jguarin200	`outdata_reg_a => "UNREGISTERED",`
383	49	jguarin200	`ram_block_type => "M9K",`
384			`widthad_a => 9,`
385			`width_a => 18,`
386			`width_byteena_a => 1`
387			`)`
388			`port map (`
389			`clock0 => clock,`
390			`address_a => address,`
391			`q_a => qc (35 downto 18)`
392			`);`
393
394			`--! 512x18 rom con los componentes cz.`
395			`CZ : altsyncram`
396			`generic map (`
397			`address_aclr_a => "NONE",`
398			`clock_enable_input_a => "BYPASS",`
399			`clock_enable_output_a => "BYPASS",`
400			`init_file => ".\memcz.mif",`
401			`intended_device_family => "Cyclone III",`
402			`lpm_hint => "ENABLE_RUNTIME_MOD=NO",`
403			`lpm_type => "altsyncram",`
404			`numwords_a => 512,`
405			`operation_mode => "ROM",`
406			`outdata_aclr_a => "NONE",`
407	50	jguarin200	`outdata_reg_a => "UNREGISTERED",`
408	49	jguarin200	`ram_block_type => "M9K",`
409			`widthad_a => 9,`
410			`width_a => 18,`
411			`width_byteena_a => 1`
412			`)`
413			`port map (`
414			`clock0 => clock,`
415			`address_a => address,`
416			`q_a => qc (53 downto 36)`
417			`);`
418
419			`--! 512x18 rom con los componentes dx.`
420			`DX : altsyncram`
421			`generic map (`
422			`address_aclr_a => "NONE",`
423			`clock_enable_input_a => "BYPASS",`
424			`clock_enable_output_a => "BYPASS",`
425			`init_file => ".\memdx.mif",`
426			`intended_device_family => "Cyclone III",`
427			`lpm_hint => "ENABLE_RUNTIME_MOD=NO",`
428			`lpm_type => "altsyncram",`
429			`numwords_a => 512,`
430			`operation_mode => "ROM",`
431			`outdata_aclr_a => "NONE",`
432	50	jguarin200	`outdata_reg_a => "UNREGISTERED",`
433	49	jguarin200	`ram_block_type => "M9K",`
434			`widthad_a => 9,`
435			`width_a => 18,`
436			`width_byteena_a => 1`
437			`)`
438			`port map (`
439			`clock0 => clock,`
440			`address_a => address,`
441			`q_a => qd (17 downto 0)`
442			`);`
443
444			`--! 512x18 rom con los componentes dy.`
445			`DY : altsyncram`
446			`generic map (`
447			`address_aclr_a => "NONE",`
448			`clock_enable_input_a => "BYPASS",`
449			`clock_enable_output_a => "BYPASS",`
450			`init_file => ".\memdy.mif",`
451			`intended_device_family => "Cyclone III",`
452			`lpm_hint => "ENABLE_RUNTIME_MOD=NO",`
453			`lpm_type => "altsyncram",`
454			`numwords_a => 512,`
455			`operation_mode => "ROM",`
456			`outdata_aclr_a => "NONE",`
457	50	jguarin200	`outdata_reg_a => "UNREGISTERED",`
458	49	jguarin200	`ram_block_type => "M9K",`
459			`widthad_a => 9,`
460			`width_a => 18,`
461			`width_byteena_a => 1`
462			`)`
463			`port map (`
464			`clock0 => clock,`
465			`address_a => address,`
466			`q_a => qd (35 downto 18)`
467			`);`
468
469			`--! 512x18 rom con los componentes dz.`
470			`DZ : altsyncram`
471			`generic map (`
472			`address_aclr_a => "NONE",`
473			`clock_enable_input_a => "BYPASS",`
474			`clock_enable_output_a => "BYPASS",`
475			`init_file => ".\memdz.mif",`
476			`intended_device_family => "Cyclone III",`
477			`lpm_hint => "ENABLE_RUNTIME_MOD=NO",`
478			`lpm_type => "altsyncram",`
479			`numwords_a => 512,`
480			`operation_mode => "ROM",`
481			`outdata_aclr_a => "NONE",`
482	50	jguarin200	`outdata_reg_a => "UNREGISTERED",`
483	49	jguarin200	`ram_block_type => "M9K",`
484			`widthad_a => 9,`
485			`width_a => 18,`
486			`width_byteena_a => 1`
487			`)`
488			`port map (`
489			`clock0 => clock,`
490			`address_a => address,`
491			`q_a => qd (53 downto 36)`
492			`);`
493
494			`end tb_arch;`
495

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