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-- RAYTRAC
-- Author Julian Andres Guarin
-- uf.vhd
-- This file is part of raytrac.
-- 
--     raytrac is free software: you can redistribute it and/or modify
--     it under the terms of the GNU General Public License as published by
--     the Free Software Foundation, either version 3 of the License, or
--     (at your option) any later version.
-- 
--     raytrac is distributed in the hope that it will be useful,
--     but WITHOUT ANY WARRANTY; without even the implied warranty of
--     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--     GNU General Public License for more details.
-- 
--     You should have received a copy of the GNU General Public License
--     along with raytrac.  If not, see <http://www.gnu.org/licenses/>.
 
library ieee;
use ieee.std_logic_1164.all;
use work.arithpack.all;
 
entity uf is
        port (
                opcode          : in std_logic;
                m0f0,m0f1,m1f0,m1f1,m2f0,m2f1,m3f0,m3f1,m4f0,m4f1,m5f0,m5f1 : in std_logic_vector(17 downto 0);
                cpx,cpy,cpz,dp0,dp1 : out std_logic_vector(31 downto 0);
                clk,rst         : in std_logic
        );
end uf;
 
architecture uf_arch of uf is
 
        -- Stage 0 signals
 
        signal stage0mf00,stage0mf01,stage0mf10,stage0mf11,stage0mf20,stage0mf21,stage0mf30,stage0mf31,stage0mf40,stage0mf41,stage0mf50,stage0mf51 : std_logic_vector(17 downto 0);
        signal stage0p0,stage0p1, stage0p2, stage0p3, stage0p4, stage0p5 : std_logic_vector(31 downto 0);
        signal stage0opcode : std_logic;
 
        --Stage 1 signals 
 
        signal stage1p0, stage1p1, stage1p2, stage1p3, stage1p4, stage1p5 : std_logic_vector (31 downto 0);
        signal stage1a0, stage1a1, stage1a2 : std_logic_vector (31 downto 0);
        signal stage1opcode : std_logic;
 
        -- Some support signals
        signal stage1_internalCarry     : std_logic_vector(2 downto 0);
        signal stage2_internalCarry : std_logic_vector(1 downto 0);
 
        --Stage 2 signals
 
        signal stage2a0, stage2a2, stage2a3, stage2a4, stage2p2, stage2p3 : std_logic_vector (31 downto 0);
 
 
 
begin
 
        -- Multiplicator Instantiation (StAgE 0)
 
        m0 : r_a18_b18_smul_c32_r
        port map (
                aclr    => rst,
                clock   => clk,
                dataa   => stage0mf00,
                datab   => stage0mf01,
                result  => stage0p0
        );
        m1 : r_a18_b18_smul_c32_r
        port map (
                aclr    => rst,
                clock   => clk,
                dataa   => stage0mf10,
                datab   => stage0mf11,
                result  => stage0p1
        );
        m2 : r_a18_b18_smul_c32_r
        port map (
                aclr    => rst,
                clock   => clk,
                dataa   => stage0mf20,
                datab   => stage0mf21,
                result  => stage0p2
        );
        m3 : r_a18_b18_smul_c32_r
        port map (
                aclr    => rst,
                clock   => clk,
                dataa   => stage0mf30,
                datab   => stage0mf31,
                result  => stage0p3
        );
        m4 : r_a18_b18_smul_c32_r
        port map (
                aclr    => rst,
                clock   => clk,
                dataa   => stage0mf40,
                datab   => stage0mf41,
                result  => stage0p4
        );
        m5 : r_a18_b18_smul_c32_r
        port map (
                aclr    => rst,
                clock   => clk,
                dataa   => stage0mf50,
                datab   => stage0mf51,
                result  => stage0p5
        );
 
        -- Adder Instantiation (sTaGe 1)
 
        --Adder 0, low adder 
        a0low : adder
        generic map (
                16,"CLA","YES"  --Carry Look Ahead Logic (More Gates Used, But Less Time)
                                                --Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
        )
        port map        (
                a => stage1p0(15 downto 0),
                b => stage1p1(15 downto 0),
                s => stage1opcode,
                ci => '0',
                result => stage1a0(15 downto 0),
                cout => stage1_internalCarry(0)
        );
        --Adder 0, high adder
        a0high : adder
        generic map (
                w => 16,
                carry_logic             => "CLA",       --Carry Look Ahead Logic (More Gates Used, But Less Time)
                substractor_selector    => "YES"        --Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
        )
        port map        (
                a => stage1p0(31 downto 16),
                b => stage1p1(31 downto 16),
                s => stage1opcode,
                ci => stage1_internalCarry(0),
                result => stage1a0(31 downto 16),
                cout => open
        );
        --Adder 1, low adder 
        a1low : adder
        generic map (
                w => 16,
                carry_logic             => "CLA",       --Carry Look Ahead Logic (More Gates Used, But Less Time)
                substractor_selector    => "YES"        --Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
        )
        port map        (
                a => stage1p2(15 downto 0),
                b => stage1p3(15 downto 0),
                s => stage1opcode,
                ci => '0',
                result => stage1a1(15 downto 0),
                cout => stage1_internalCarry(1)
        );
        --Adder 1, high adder
        a1high : adder
        generic map (
                w => 16,
                carry_logic             => "CLA",       --Carry Look Ahead Logic (More Gates Used, But Less Time)
                substractor_selector    => "YES"        --Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
        )
        port map        (
                a => stage1p2(31 downto 16),
                b => stage1p3(31 downto 16),
                s => stage1opcode,
                ci => stage1_internalCarry(1),
                result => stage1a1(31 downto 16),
                cout => open
        );
        --Adder 2, low adder 
        a2low : adder
        generic map (
                w => 16,
                carry_logic             => "CLA",       --Carry Look Ahead Logic (More Gates Used, But Less Time)
                substractor_selector    => "YES"        --Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
        )
        port map        (
                a => stage1p4(15 downto 0),
                b => stage1p5(15 downto 0),
                s => stage1opcode,
                ci => '0',
                result => stage1a2(15 downto 0),
                cout => stage1_internalCarry(2)
        );
        --Adder 2, high adder
        a2high : adder
        generic map (
                w => 16,
                carry_logic             => "CLA",       --Carry Look Ahead Logic (More Gates Used, But Less Time)
                substractor_selector    => "YES"        --Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.
        )
        port map        (
                a => stage1p4(31 downto 16),
                b => stage1p5(31 downto 16),
                s => stage1opcode,
                ci => stage1_internalCarry(2),
                result => stage1a2(31 downto 16),
                cout => open
        );
 
 
        -- Adder Instantiation (Stage 2)
        --Adder 3, low adder 
        a3low : adder
        generic map (
                w => 16,
                carry_logic             => "CLA",       --Carry Look Ahead Logic (More Gates Used, But Less Time)
                substractor_selector    => "NO"         --No Just Add.
        )
        port map        (
                a => stage2a0(15 downto 0),
                b => stage2p2(15 downto 0),
                s => '0',
                ci => '0',
                result => stage2a3(15 downto 0),
                cout => stage2_internalCarry(0)
        );
        --Adder 3, high adder
        a3high : adder
        generic map (
                w => 16,
                carry_logic             => "CLA",       --Carry Look Ahead Logic (More Gates Used, But Less Time)
                substractor_selector    => "NO"         --No Just Add.
        )
        port map        (
                a => stage2a0(31 downto 16),
                b => stage2p2(31 downto 16),
                s => '0',
                ci => stage2_internalCarry(0),
                result => stage2a3(31 downto 16),
                cout => open
        );
        --Adder 4, low adder 
        a4low : adder
        generic map (
                w => 16,
                carry_logic             => "CLA",       --Carry Look Ahead Logic (More Gates Used, But Less Time)
                substractor_selector    => "NO"         --No Just Add.
        )
        port map        (
                a => stage2p3(15 downto 0),
                b => stage2a2(15 downto 0),
                s => '0',
                ci => '0',
                result => stage2a4(15 downto 0),
                cout => stage2_internalCarry(1)
        );
        --Adder 4, high adder
        a4high : adder
        generic map (
                w => 16,
                carry_logic             => "CLA",       --Carry Look Ahead Logic (More Gates Used, But Less Time)
                substractor_selector    => "NO"         --No Just Add.
        )
        port map        (
                a => stage2p3(31 downto 16),
                b => stage2a2(31 downto 16),
                s => '0',
                ci => stage2_internalCarry(1),
                result => stage2a4(31 downto 16),
                cout => open
        );
 
        -- Incoming from opcoder.vhd signals into pipeline's stage 0.
        stage0mf00 <= m0f0;
        stage0mf01 <= m0f1;
        stage0mf10 <= m1f0;
        stage0mf11 <= m1f1;
        stage0mf20 <= m2f0;
        stage0mf21 <= m2f1;
        stage0mf30 <= m3f0;
        stage0mf31 <= m3f1;
        stage0mf40 <= m4f0;
        stage0mf41 <= m4f1;
        stage0mf50 <= m5f0;
        stage0mf51 <= m5f1;
 
        -- Signal sequencing: as the multipliers use registered output and registered input is not necessary to write the sequence of stage 0 signals to stage 1 signals.
        -- so the simplistic path is taken: simply connect stage 0 to stage 1 lines. However this would not apply for the opcode signal
        stage1p0 <= stage0p0;
        stage1p1 <= stage0p1;
        stage1p2 <= stage0p2;
        stage1p3 <= stage0p3;
        stage1p4 <= stage0p4;
        stage1p5 <= stage0p5;
 
 
        --Outcoming to the rest of the system (by the time i wrote this i dont know where this leads to... jeje)
        cpx <= stage1a0;
        cpy <= stage1a1;
        cpz <= stage1a2;
        dp0 <= stage2a3;
        dp1 <= stage2a4;
 
        -- Looking into the design the stage 1 to stage 2 are the sequences pipe stages that must be controlled in this particular HDL.
        uf_seq: process (clk,rst,opcode)
        begin
 
                if rst=rstMasterValue then
                        stage0opcode    <= '0';
                        stage1opcode    <= '0';
 
                        stage2a2 <= (others => '0');
                        stage2p3 <= (others => '0');
                        stage2p2 <= (others => '0');
                        stage2a0 <= (others => '0');
 
                elsif clk'event and clk = '1' then
 
                        stage2a2 <= stage1a2;
                        stage2p3 <= stage1p3;
                        stage2p2 <= stage1p2;
                        stage2a0 <= stage1a0;
 
                        -- Opcode control sequence
                        stage0opcode <= opcode;
                        stage1opcode <= stage0opcode;
 
                end if;
        end process uf_seq;
        uf_seq2: process (clk,rst,stage0opcode)
        begin
 
                if rst=rstMasterValue then
 
 
                elsif clk'event and clk='1' then
 
 
                end if;
 
        end process uf_seq2;
 
 
 
end uf_arch;

Line No.	Rev	Author	Line
1	8	jguarin200	`-- RAYTRAC`
2			`-- Author Julian Andres Guarin`
3			`-- uf.vhd`
4			`-- This file is part of raytrac.`
5			`--`
6			`-- raytrac is free software: you can redistribute it and/or modify`
7			`-- it under the terms of the GNU General Public License as published by`
8			`-- the Free Software Foundation, either version 3 of the License, or`
9			`-- (at your option) any later version.`
10			`--`
11			`-- raytrac is distributed in the hope that it will be useful,`
12			`-- but WITHOUT ANY WARRANTY; without even the implied warranty of`
13			`-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
14			`-- GNU General Public License for more details.`
15			`--`
16			`-- You should have received a copy of the GNU General Public License`
17			`-- along with raytrac. If not, see <http://www.gnu.org/licenses/>.`
18
19	2	jguarin200	`library ieee;`
20			`use ieee.std_logic_1164.all;`
21			`use work.arithpack.all;`
22
23			`entity uf is`
24			`port (`
25	3	jguarin200	`opcode : in std_logic;`
26	14	jguarin200	`m0f0,m0f1,m1f0,m1f1,m2f0,m2f1,m3f0,m3f1,m4f0,m4f1,m5f0,m5f1 : in std_logic_vector(17 downto 0);`
27	13	jguarin200	`cpx,cpy,cpz,dp0,dp1 : out std_logic_vector(31 downto 0);`
28	8	jguarin200	`clk,rst : in std_logic`
29	2	jguarin200	`);`
30			`end uf;`
31
32			`architecture uf_arch of uf is`
33
34	8	jguarin200	`-- Stage 0 signals`
35	2	jguarin200
36	15	jguarin200	`signal stage0mf00,stage0mf01,stage0mf10,stage0mf11,stage0mf20,stage0mf21,stage0mf30,stage0mf31,stage0mf40,stage0mf41,stage0mf50,stage0mf51 : std_logic_vector(17 downto 0);`
37			`signal stage0p0,stage0p1, stage0p2, stage0p3, stage0p4, stage0p5 : std_logic_vector(31 downto 0);`
38			`signal stage0opcode : std_logic;`
39	2	jguarin200
40	8	jguarin200	`--Stage 1 signals`
41	2	jguarin200
42	15	jguarin200	`signal stage1p0, stage1p1, stage1p2, stage1p3, stage1p4, stage1p5 : std_logic_vector (31 downto 0);`
43			`signal stage1a0, stage1a1, stage1a2 : std_logic_vector (31 downto 0);`
44			`signal stage1opcode : std_logic;`
45	2	jguarin200
46	8	jguarin200	`-- Some support signals`
47	15	jguarin200	`signal stage1_internalCarry : std_logic_vector(2 downto 0);`
48			`signal stage2_internalCarry : std_logic_vector(1 downto 0);`
49	2	jguarin200
50	8	jguarin200	`--Stage 2 signals`
51
52	15	jguarin200	`signal stage2a0, stage2a2, stage2a3, stage2a4, stage2p2, stage2p3 : std_logic_vector (31 downto 0);`
53	8	jguarin200
54
55
56	2	jguarin200	`begin`
57
58	8	jguarin200	`-- Multiplicator Instantiation (StAgE 0)`
59	2	jguarin200
60	14	jguarin200	`m0 : r_a18_b18_smul_c32_r`
61	8	jguarin200	`port map (`
62			`aclr => rst,`
63			`clock => clk,`
64	15	jguarin200	`dataa => stage0mf00,`
65			`datab => stage0mf01,`
66			`result => stage0p0`
67	8	jguarin200	`);`
68	14	jguarin200	`m1 : r_a18_b18_smul_c32_r`
69	8	jguarin200	`port map (`
70			`aclr => rst,`
71			`clock => clk,`
72	15	jguarin200	`dataa => stage0mf10,`
73			`datab => stage0mf11,`
74			`result => stage0p1`
75	8	jguarin200	`);`
76	14	jguarin200	`m2 : r_a18_b18_smul_c32_r`
77	8	jguarin200	`port map (`
78			`aclr => rst,`
79			`clock => clk,`
80	15	jguarin200	`dataa => stage0mf20,`
81			`datab => stage0mf21,`
82			`result => stage0p2`
83	8	jguarin200	`);`
84	14	jguarin200	`m3 : r_a18_b18_smul_c32_r`
85	8	jguarin200	`port map (`
86			`aclr => rst,`
87			`clock => clk,`
88	15	jguarin200	`dataa => stage0mf30,`
89			`datab => stage0mf31,`
90			`result => stage0p3`
91	8	jguarin200	`);`
92	14	jguarin200	`m4 : r_a18_b18_smul_c32_r`
93	8	jguarin200	`port map (`
94			`aclr => rst,`
95			`clock => clk,`
96	15	jguarin200	`dataa => stage0mf40,`
97			`datab => stage0mf41,`
98			`result => stage0p4`
99	8	jguarin200	`);`
100	14	jguarin200	`m5 : r_a18_b18_smul_c32_r`
101	8	jguarin200	`port map (`
102			`aclr => rst,`
103			`clock => clk,`
104	15	jguarin200	`dataa => stage0mf50,`
105			`datab => stage0mf51,`
106			`result => stage0p5`
107	8	jguarin200	`);`
108
109			`-- Adder Instantiation (sTaGe 1)`
110
111			`--Adder 0, low adder`
112			`a0low : adder`
113			`generic map (`
114	14	jguarin200	`16,"CLA","YES" --Carry Look Ahead Logic (More Gates Used, But Less Time)`
115			`--Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.`
116	8	jguarin200	`)`
117			`port map (`
118	15	jguarin200	`a => stage1p0(15 downto 0),`
119			`b => stage1p1(15 downto 0),`
120			`s => stage1opcode,`
121	8	jguarin200	`ci => '0',`
122	15	jguarin200	`result => stage1a0(15 downto 0),`
123			`cout => stage1_internalCarry(0)`
124	8	jguarin200	`);`
125			`--Adder 0, high adder`
126			`a0high : adder`
127			`generic map (`
128			`w => 16,`
129			`carry_logic => "CLA", --Carry Look Ahead Logic (More Gates Used, But Less Time)`
130	14	jguarin200	`substractor_selector => "YES" --Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.`
131	8	jguarin200	`)`
132			`port map (`
133	15	jguarin200	`a => stage1p0(31 downto 16),`
134			`b => stage1p1(31 downto 16),`
135			`s => stage1opcode,`
136			`ci => stage1_internalCarry(0),`
137			`result => stage1a0(31 downto 16),`
138	8	jguarin200	`cout => open`
139			`);`
140			`--Adder 1, low adder`
141			`a1low : adder`
142			`generic map (`
143			`w => 16,`
144			`carry_logic => "CLA", --Carry Look Ahead Logic (More Gates Used, But Less Time)`
145	14	jguarin200	`substractor_selector => "YES" --Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.`
146	8	jguarin200	`)`
147			`port map (`
148	15	jguarin200	`a => stage1p2(15 downto 0),`
149			`b => stage1p3(15 downto 0),`
150			`s => stage1opcode,`
151	8	jguarin200	`ci => '0',`
152	15	jguarin200	`result => stage1a1(15 downto 0),`
153			`cout => stage1_internalCarry(1)`
154	8	jguarin200	`);`
155			`--Adder 1, high adder`
156			`a1high : adder`
157			`generic map (`
158			`w => 16,`
159			`carry_logic => "CLA", --Carry Look Ahead Logic (More Gates Used, But Less Time)`
160	14	jguarin200	`substractor_selector => "YES" --Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.`
161	8	jguarin200	`)`
162			`port map (`
163	15	jguarin200	`a => stage1p2(31 downto 16),`
164			`b => stage1p3(31 downto 16),`
165			`s => stage1opcode,`
166			`ci => stage1_internalCarry(1),`
167			`result => stage1a1(31 downto 16),`
168	8	jguarin200	`cout => open`
169			`);`
170			`--Adder 2, low adder`
171	14	jguarin200	`a2low : adder`
172	8	jguarin200	`generic map (`
173			`w => 16,`
174			`carry_logic => "CLA", --Carry Look Ahead Logic (More Gates Used, But Less Time)`
175	14	jguarin200	`substractor_selector => "YES" --Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.`
176	8	jguarin200	`)`
177			`port map (`
178	15	jguarin200	`a => stage1p4(15 downto 0),`
179			`b => stage1p5(15 downto 0),`
180			`s => stage1opcode,`
181	8	jguarin200	`ci => '0',`
182	15	jguarin200	`result => stage1a2(15 downto 0),`
183			`cout => stage1_internalCarry(2)`
184	8	jguarin200	`);`
185			`--Adder 2, high adder`
186	14	jguarin200	`a2high : adder`
187	8	jguarin200	`generic map (`
188			`w => 16,`
189			`carry_logic => "CLA", --Carry Look Ahead Logic (More Gates Used, But Less Time)`
190	14	jguarin200	`substractor_selector => "YES" --Yes instantiate Xor gates stage in the adder so we can substract on the opcode signal command.`
191	8	jguarin200	`)`
192			`port map (`
193	15	jguarin200	`a => stage1p4(31 downto 16),`
194			`b => stage1p5(31 downto 16),`
195			`s => stage1opcode,`
196			`ci => stage1_internalCarry(2),`
197			`result => stage1a2(31 downto 16),`
198	8	jguarin200	`cout => open`
199			`);`
200
201
202			`-- Adder Instantiation (Stage 2)`
203			`--Adder 3, low adder`
204			`a3low : adder`
205			`generic map (`
206			`w => 16,`
207			`carry_logic => "CLA", --Carry Look Ahead Logic (More Gates Used, But Less Time)`
208	14	jguarin200	`substractor_selector => "NO" --No Just Add.`
209	8	jguarin200	`)`
210			`port map (`
211	15	jguarin200	`a => stage2a0(15 downto 0),`
212			`b => stage2p2(15 downto 0),`
213	14	jguarin200	`s => '0',`
214	8	jguarin200	`ci => '0',`
215	15	jguarin200	`result => stage2a3(15 downto 0),`
216			`cout => stage2_internalCarry(0)`
217	8	jguarin200	`);`
218			`--Adder 3, high adder`
219			`a3high : adder`
220			`generic map (`
221			`w => 16,`
222			`carry_logic => "CLA", --Carry Look Ahead Logic (More Gates Used, But Less Time)`
223	14	jguarin200	`substractor_selector => "NO" --No Just Add.`
224	8	jguarin200	`)`
225			`port map (`
226	15	jguarin200	`a => stage2a0(31 downto 16),`
227			`b => stage2p2(31 downto 16),`
228	14	jguarin200	`s => '0',`
229	15	jguarin200	`ci => stage2_internalCarry(0),`
230			`result => stage2a3(31 downto 16),`
231	8	jguarin200	`cout => open`
232			`);`
233			`--Adder 4, low adder`
234			`a4low : adder`
235			`generic map (`
236			`w => 16,`
237			`carry_logic => "CLA", --Carry Look Ahead Logic (More Gates Used, But Less Time)`
238	14	jguarin200	`substractor_selector => "NO" --No Just Add.`
239	8	jguarin200	`)`
240			`port map (`
241	15	jguarin200	`a => stage2p3(15 downto 0),`
242			`b => stage2a2(15 downto 0),`
243	14	jguarin200	`s => '0',`
244	8	jguarin200	`ci => '0',`
245	15	jguarin200	`result => stage2a4(15 downto 0),`
246			`cout => stage2_internalCarry(1)`
247	8	jguarin200	`);`
248			`--Adder 4, high adder`
249			`a4high : adder`
250			`generic map (`
251			`w => 16,`
252			`carry_logic => "CLA", --Carry Look Ahead Logic (More Gates Used, But Less Time)`
253	14	jguarin200	`substractor_selector => "NO" --No Just Add.`
254	8	jguarin200	`)`
255			`port map (`
256	15	jguarin200	`a => stage2p3(31 downto 16),`
257			`b => stage2a2(31 downto 16),`
258	14	jguarin200	`s => '0',`
259	15	jguarin200	`ci => stage2_internalCarry(1),`
260			`result => stage2a4(31 downto 16),`
261	8	jguarin200	`cout => open`
262			`);`
263
264			`-- Incoming from opcoder.vhd signals into pipeline's stage 0.`
265	15	jguarin200	`stage0mf00 <= m0f0;`
266			`stage0mf01 <= m0f1;`
267			`stage0mf10 <= m1f0;`
268			`stage0mf11 <= m1f1;`
269			`stage0mf20 <= m2f0;`
270			`stage0mf21 <= m2f1;`
271			`stage0mf30 <= m3f0;`
272			`stage0mf31 <= m3f1;`
273			`stage0mf40 <= m4f0;`
274			`stage0mf41 <= m4f1;`
275			`stage0mf50 <= m5f0;`
276			`stage0mf51 <= m5f1;`
277	8	jguarin200
278			`-- Signal sequencing: as the multipliers use registered output and registered input is not necessary to write the sequence of stage 0 signals to stage 1 signals.`
279			`-- so the simplistic path is taken: simply connect stage 0 to stage 1 lines. However this would not apply for the opcode signal`
280	15	jguarin200	`stage1p0 <= stage0p0;`
281			`stage1p1 <= stage0p1;`
282			`stage1p2 <= stage0p2;`
283			`stage1p3 <= stage0p3;`
284			`stage1p4 <= stage0p4;`
285			`stage1p5 <= stage0p5;`
286	8	jguarin200
287
288			`--Outcoming to the rest of the system (by the time i wrote this i dont know where this leads to... jeje)`
289	15	jguarin200	`cpx <= stage1a0;`
290			`cpy <= stage1a1;`
291			`cpz <= stage1a2;`
292			`dp0 <= stage2a3;`
293			`dp1 <= stage2a4;`
294	8	jguarin200
295			`-- Looking into the design the stage 1 to stage 2 are the sequences pipe stages that must be controlled in this particular HDL.`
296	15	jguarin200	`uf_seq: process (clk,rst,opcode)`
297	8	jguarin200	`begin`
298
299			`if rst=rstMasterValue then`
300	15	jguarin200	`stage0opcode <= '0';`
301			`stage1opcode <= '0';`
302	3	jguarin200
303	15	jguarin200	`stage2a2 <= (others => '0');`
304			`stage2p3 <= (others => '0');`
305			`stage2p2 <= (others => '0');`
306			`stage2a0 <= (others => '0');`
307	8	jguarin200
308			`elsif clk'event and clk = '1' then`
309
310	15	jguarin200	`stage2a2 <= stage1a2;`
311			`stage2p3 <= stage1p3;`
312			`stage2p2 <= stage1p2;`
313			`stage2a0 <= stage1a0;`
314	3	jguarin200
315	8	jguarin200	`-- Opcode control sequence`
316	15	jguarin200	`stage0opcode <= opcode;`
317			`stage1opcode <= stage0opcode;`
318	8	jguarin200
319			`end if;`
320			`end process uf_seq;`
321	15	jguarin200	`uf_seq2: process (clk,rst,stage0opcode)`
322			`begin`
323
324			`if rst=rstMasterValue then`
325
326
327			`elsif clk'event and clk='1' then`
328
329
330			`end if;`
331
332			`end process uf_seq2;`
333
334
335
336	2	jguarin200	`end uf_arch;`

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