5) Now you should start receiving the pseudo-random stream via the output bus, one byte every clock. The output_ready signal signals when a valid byte is present at the output K.
WARNING: The 256-byte register that this implementation uses is very costly in FPGA resources and will result in >2000 slices used in some synthetizers.
PS: This is licensed LGPL, not public domain or BSD, so you should, put a copy of the license in your software and stuff. Yes, I'm talking to you jhunjhun, you too have to do it.