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[/ ] [rc4-prbs/ ] [trunk/ ] [README.txt ] - Blame information for rev 19
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ortegaalfr
Hi,
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I was looking for a quick implementation of RC4 and I couldn't find one, so I wrote one based on the wikipedia example.
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It's quite easy to use:
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1) First, issue rst
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2) Load the password byte-by-byte into the password_input port. The lenght of the password is KEY_SIZE
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3) Issue 768 clocks to perform key expansion
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ortegaalfr
4) Wait 1536 clocks while the module discards the first weak bytes of the stream as per RFC 4345.
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ortegaalfr
5) Now you should start receiving the pseudo-random stream via the output bus, one byte every clock. The output_ready signal signals when a valid byte is present at the output K.
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ortegaalfr
To encrypt or decrypt using RC4 you simply xor your data with the output stream.
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ortegaalfr
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ortegaalfr
The testbench and makefile work using icarus verilog and you can peer into rc4_tb.v to see an example implementation.
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ortegaalfr
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ortegaalfr
After installing icarus verilog in your path, just issue:
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make
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and then
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./rc4.vvp
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And you should see the output of the simulation.
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ortegaalfr
Any question or suggestion send an email to aortega@alu.itba.edu.ar, cc: alfred@groundworkstech.com
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ortegaalfr
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Cheers,
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Alfredo
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ortegaalfr
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PS: This is licensed LGPL, not public domain or BSD, so you should, put a copy of the license in your software and stuff. Yes, I'm talking to you jhunjhun, you too have to do it.
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