URL https://opencores.org/ocsvn/rc4-prbs/rc4-prbs/trunk

Subversion Repositories rc4-prbs

[/] [rc4-prbs/] [trunk/] [rc4_tb.v] - Blame information for rev 2

Go to most recent revision | Details | Compare with Previous | View Log


/* RC4 PRGA Testbench */
 
`define RC4
 
 
`ifndef TEST_CYCLES
`define TEST_CYCLES 2000
`endif
 
`define KEY_SIZE 8
 
module rc4;
endmodule
 
module rc4_tb;
 
 
parameter tck = 10, program_cycles = `TEST_CYCLES;
 
 
reg clk, rst; // clock, reset
 
 
 
/* Clocking device */
always #(tck/2)
        clk = ~clk;
 
integer clkcount=0;
always @ (posedge clk)
        begin
        clkcount=clkcount+1;
                $display ("--- clk %d ---",clkcount);
        end
 
/* RC4 PRGA */
 
// S array
reg [7:0] S[0:256];
// Key
reg [7:0] key[0:`KEY_SIZE-1];
 
// Key-scheduling state
`define KSS_KEYSCHED1 4'h1
`define KSS_KEYSCHED2 4'h2
`define KSS_KEYSCHED3 4'h3
`define KSS_CRYPTO 4'h4
 
// Variable names from http://en.wikipedia.org/wiki/RC4
reg [3:0] KSState;
reg [7:0] i; // Counter
reg [7:0] j;
reg [7:0] temp;
reg [7:0] K;
reg KS_Finished;
always @ (posedge clk or posedge rst)
        begin
        if (rst)
                begin
                i <= 8'h0;
                KSState <= `KSS_KEYSCHED1;
                KS_Finished <= 0;
                j <= 0;
                end
        case (KSState)
                `KSS_KEYSCHED1: begin
                                S[i] <= i;
                                if (i == 8'hFF)
                                        begin
                                        KSState <= `KSS_KEYSCHED2;
                                        i <= 8'h00;
                                        end
                                else    i <= i +1;
                                end
                `KSS_KEYSCHED2: begin
                                j <= (j + S[i] + key[i % `KEY_SIZE]);
                                KSState <= `KSS_KEYSCHED3;
                                end
                `KSS_KEYSCHED3: begin
                                S[i]<=S[j];
                                S[j]<=S[i];
                                if (i == 8'hFF)
                                        begin
                                        KSState <= `KSS_CRYPTO;
                                        KS_Finished <= 1; // Flag keysched finished
                                        i <= 8'h00;
                                        end
                                else    begin
                                        i <= i + 1;
                                        KSState <= `KSS_KEYSCHED2;
                                        end
                                end
 
                `KSS_CRYPTO:    begin // It was all nicely pipelined until this point where I don't care anymore
                                i = i + 1;
                                j = (j + S[i]);
                                temp = S[j];
                                S[j]=S[i];
                                S[i]=temp;
                                K = S[ S[i]+S[j] ];
                                $display ("KSS_CRYPTO: K: %d",K);
                                end
                default:        begin
                                end
        endcase
        end
 
 
 
/* Simulation */
integer q;
initial begin
        for (q=0; q<`KEY_SIZE; q=q+1) key[q] = 8'h42; // initialize Key
        $display ("Start...");
        clk <= 0;
        KSState <= 8'h0; // Init key-schedule state
        rst <= 1;
        #(1*tck)
        rst <= 0;
        #(program_cycles*tck+100)
        $display ("Finish.");
        $finish;
end
 
 
endmodule

Line No.	Rev	Author	Line
1	2	ortegaalfr	`/* RC4 PRGA Testbench */`
2
3			`define RC4
4
5
6			`ifndef TEST_CYCLES
7			`define TEST_CYCLES 2000
8			`endif
9
10			`define KEY_SIZE 8
11
12			`module rc4;`
13			`endmodule`
14
15			`module rc4_tb;`
16
17
18			parameter tck = 10, program_cycles = `TEST_CYCLES;
19
20
21			`reg clk, rst; // clock, reset`
22
23
24
25			`/* Clocking device */`
26			`always #(tck/2)`
27			`clk = ~clk;`
28
29			`integer clkcount=0;`
30			`always @ (posedge clk)`
31			`begin`
32			`clkcount=clkcount+1;`
33			`$display ("--- clk %d ---",clkcount);`
34			`end`
35
36			`/* RC4 PRGA */`
37
38			`// S array`
39			`reg [7:0] S[0:256];`
40			`// Key`
41			reg [7:0] key[0:`KEY_SIZE-1];
42
43			`// Key-scheduling state`
44			`define KSS_KEYSCHED1 4'h1
45			`define KSS_KEYSCHED2 4'h2
46			`define KSS_KEYSCHED3 4'h3
47			`define KSS_CRYPTO 4'h4
48
49			`// Variable names from http://en.wikipedia.org/wiki/RC4`
50			`reg [3:0] KSState;`
51			`reg [7:0] i; // Counter`
52			`reg [7:0] j;`
53			`reg [7:0] temp;`
54			`reg [7:0] K;`
55			`reg KS_Finished;`
56			`always @ (posedge clk or posedge rst)`
57			`begin`
58			`if (rst)`
59			`begin`
60			`i <= 8'h0;`
61			KSState <= `KSS_KEYSCHED1;
62			`KS_Finished <= 0;`
63			`j <= 0;`
64			`end`
65			`case (KSState)`
66			`KSS_KEYSCHED1: begin
67			`S[i] <= i;`
68			`if (i == 8'hFF)`
69			`begin`
70			KSState <= `KSS_KEYSCHED2;
71			`i <= 8'h00;`
72			`end`
73			`else i <= i +1;`
74			`end`
75			`KSS_KEYSCHED2: begin
76			j <= (j + S[i] + key[i % `KEY_SIZE]);
77			KSState <= `KSS_KEYSCHED3;
78			`end`
79			`KSS_KEYSCHED3: begin
80			`S[i]<=S[j];`
81			`S[j]<=S[i];`
82			`if (i == 8'hFF)`
83			`begin`
84			KSState <= `KSS_CRYPTO;
85			`KS_Finished <= 1; // Flag keysched finished`
86			`i <= 8'h00;`
87			`end`
88			`else begin`
89			`i <= i + 1;`
90			KSState <= `KSS_KEYSCHED2;
91			`end`
92			`end`
93
94			`KSS_CRYPTO: begin // It was all nicely pipelined until this point where I don't care anymore
95			`i = i + 1;`
96			`j = (j + S[i]);`
97			`temp = S[j];`
98			`S[j]=S[i];`
99			`S[i]=temp;`
100			`K = S[ S[i]+S[j] ];`
101			`$display ("KSS_CRYPTO: K: %d",K);`
102			`end`
103			`default: begin`
104			`end`
105			`endcase`
106			`end`
107
108
109
110			`/* Simulation */`
111			`integer q;`
112			`initial begin`
113			for (q=0; q<`KEY_SIZE; q=q+1) key[q] = 8'h42; // initialize Key
114			`$display ("Start...");`
115			`clk <= 0;`
116			`KSState <= 8'h0; // Init key-schedule state`
117			`rst <= 1;`
118			`#(1*tck)`
119			`rst <= 0;`
120			`#(program_cycles*tck+100)`
121			`$display ("Finish.");`
122			`$finish;`
123			`end`
124
125
126			`endmodule`

Browse

Tools

Subversion Repositories rc4-prbs

[/] [rc4-prbs/] [trunk/] [rc4_tb.v] - Blame information for rev 2