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[/] [rc4-prbs/] [trunk/] [rc4_tb.v] - Blame information for rev 4

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1 3 ortegaalfr
/*
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        RC4 PRGA Testbench
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        Copyright 2012 - Alfredo Ortega
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        aortega@alu.itba.edu.ar
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 This library is free software: you can redistribute it and/or
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 modify it under the terms of the GNU Lesser General Public
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 License as published by the Free Software Foundation, either
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 version 3 of the License, or (at your option) any later version.
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 This library is distributed in the hope that it will be useful,
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 but WITHOUT ANY WARRANTY; without even the implied warranty of
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 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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 Lesser General Public License for more details.
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 You should have received a copy of the GNU Lesser General Public
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 License along with this library.  If not, see <http://www.gnu.org/licenses/>.
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*/
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`define RC4
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`ifndef TEST_CYCLES
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`define TEST_CYCLES 2000
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`endif
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`include "rc4.inc"
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module rc4_tb;
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reg [7:0] password[0:`KEY_SIZE-1];
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parameter tck = 10, program_cycles = `TEST_CYCLES;
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reg clk, rst; // clock, reset
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wire output_ready; // output ready (valid)
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wire [7:0] K; // output
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reg [7:0] password_input; //input
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//wire [7:0] Kreg; // output
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//assign Kreg=K;
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/* Clocking device */
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always #(tck/2)
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        clk = ~clk;
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integer clkcount;
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always @ (posedge clk)
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        begin
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        clkcount<=clkcount+1;
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        if (clkcount < `KEY_SIZE)
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                begin
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                password_input<=password[clkcount];
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                $display ("--- clk %d --- key[%x] = %08X",clkcount,clkcount,password[clkcount]);
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                end
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        else $display ("--- clk %d --- K %08X",clkcount,K);
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        end
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/* rc4 module implementation */
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rc4 rc4mod(
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        .clk(clk),
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        .rst(rst),
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        .password_input(password_input),
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        .output_ready(output_ready),
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        .K(K)
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);
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/* Simulation */
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integer q;
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initial begin
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        for (q=0; q<`KEY_SIZE; q=q+1) password[q] = 8'h42; // initialize Key
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        $display ("Start...");
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        clk = 0;
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        rst = 1;
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        clkcount =0;
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        password_input=password[clkcount];
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        #(1*tck)
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        rst = 0;
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        #(program_cycles*tck+100)
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        $display ("Finish.");
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        $finish;
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end
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endmodule

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