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[/] [reed_solomon_codec_generator/] [trunk/] [example/] [rtl/] [RsDecodeDelay.v] - Blame information for rev 4

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1 4 issei 
//===================================================================
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// Module Name : RsDecodeDelay
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// File Name   : RsDecodeDelay.v
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// Function    : Rs DpRam Memory controller Module
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//
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// Revision History:
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// Date          By           Version    Change Description
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//===================================================================
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// 2009/02/03  Gael Sapience     1.0       Original
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//
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//===================================================================
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// (C) COPYRIGHT 2009 SYSTEM LSI CO., Ltd.
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//
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module RsDecodeDelay(
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   CLK,      // system clock
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   RESET,    // system reset
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   enable,   // enable signal
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   dataIn,   // data input
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   dataOut   // data output
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);
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   input          CLK;       // system clock
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   input          RESET;     // system reset
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   input          enable;    // enable signal
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   input  [8:0]   dataIn;    // data input
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   output [8:0]   dataOut;   // data output
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   //------------------------------------------------------------------------
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   //- registers
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   //------------------------------------------------------------------------
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   reg  [8:0]   writePointer;
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   reg  [8:0]   readPointer;
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   wire [8:0]   dpramRdData;
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   //------------------------------------------------------------------------
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   //- RAM memory instantiation
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   //------------------------------------------------------------------------
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   RsDecodeDpRam RsDecodeDpRam(
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      // Outputs
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      .q(dpramRdData),
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      // Inputs
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      .clock(CLK),
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      .data(dataIn [8:0]),
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      .rdaddress(readPointer),
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      .rden(enable),
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      .wraddress(writePointer),
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      .wren(enable)
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   );
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   //------------------------------------------------------------------------
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   //+ dataOut
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   //------------------------------------------------------------------------
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   assign dataOut[8:0] = dpramRdData;
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   //------------------------------------------------------------------------
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   //- Write Pointer
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   //------------------------------------------------------------------------
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   always @(posedge CLK or negedge RESET) begin
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      if (~RESET) begin
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         writePointer   <= 9'd351;
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      end
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      else if (enable == 1'b1) begin
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         if (writePointer == 9'd351) begin
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            writePointer <= 9'd0;
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         end
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         else begin
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            writePointer <= writePointer + 9'd1;
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         end
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      end
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   end
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   //------------------------------------------------------------------------
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   //- Read Pointer
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   //------------------------------------------------------------------------
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   always @(posedge CLK or negedge RESET) begin
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      if (~RESET) begin
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         readPointer  [8:0] <= 9'd0;
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      end
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      else if (enable == 1'b1) begin
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         if (readPointer == 9'd351) begin
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            readPointer <= 9'd0;
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         end
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         else begin
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            readPointer <= readPointer + 9'd1;
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         end
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      end
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   end
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endmodule

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