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[/] [reed_solomon_codec_generator/] [trunk/] [example/] [rtl/] [RsDecodeDpRam.v] - Blame information for rev 4

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1 4 issei
//===================================================================
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// Module Name : RsDecodeDpRam
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// File Name   : RsDecodeDpRam.v
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// Function    : Rs Decoder DpRam Memory Module
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// 
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// Revision History:
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// Date          By           Version    Change Description
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//===================================================================
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// 2009/02/03  Gael Sapience     1.0       Original
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//
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//===================================================================
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// (C) COPYRIGHT 2009 SYSTEM LSI CO., Ltd.
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//
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module RsDecodeDpRam (/*AUTOARG*/
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   // Outputs
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   q,
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   // Inputs
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   clock,
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   data,
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   rdaddress,
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   rden,
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   wraddress,
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   wren
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   );
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   output [8:0]   q;
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   input          clock;
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   input  [8:0]   data;
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   input  [8:0]   rdaddress;
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   input  [8:0]   wraddress;
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   input          rden;
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   input          wren;
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    //------------------------------------------------------------------
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    // + mem
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    //  - DpRam Memory
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    //------------------------------------------------------------------
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   reg [8:0]   mem[0:351];
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    always@(posedge clock) begin
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       if (wren)
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         mem[wraddress] <= data;
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    end
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    //------------------------------------------------------------------
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    // + rRdAddr
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    //  - Read Address register
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    //------------------------------------------------------------------
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    reg [8:0] rRdAddr;
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    always@(posedge clock) begin
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       rRdAddr <= rdaddress;
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    end
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    //------------------------------------------------------------------
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    // + rRdEn
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    //  - リードイネーブ?
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    //------------------------------------------------------------------
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    reg  rRdEn;
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    always@(posedge clock) begin
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       rRdEn <= rden;
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    end
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    //------------------------------------------------------------------
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    // + q
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    //  - リード処理
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    //------------------------------------------------------------------
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    reg [8:0] q;
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    always@(posedge clock) begin
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       if (rRdEn)
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          q <= mem[rRdAddr];
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    end
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 endmodule

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