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[/] [reed_solomon_codec_generator/] [trunk/] [example/] [rtl/] [RsDecodeErasure.v] - Blame information for rev 4

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1 4 issei 
//===================================================================
2 
// Module Name : RsDecodeErasure
3 
// File Name   : RsDecodeErasure.v
4 
// Function    : Rs Decoder Erasure polynomial calculation Module
5 
//
6 
// Revision History:
7 
// Date          By           Version    Change Description
8 
//===================================================================
9 
// 2009/02/03  Gael Sapience     1.0       Original
10 
//
11 
//===================================================================
12 
// (C) COPYRIGHT 2009 SYSTEM LSI CO., Ltd.
13 
//
14 
 
15 
 
16 
module RsDecodeErasure(
17 
   CLK,          // system clock
18 
   RESET,        // system reset
19 
   enable,       // enable signal
20 
   sync,         // sync signal
21 
   erasureIn,    // erasure input
22 
   epsilon_0,    // epsilon polynom 0
23 
   epsilon_1,    // epsilon polynom 1
24 
   epsilon_2,    // epsilon polynom 2
25 
   epsilon_3,    // epsilon polynom 3
26 
   epsilon_4,    // epsilon polynom 4
27 
   epsilon_5,    // epsilon polynom 5
28 
   epsilon_6,    // epsilon polynom 6
29 
   epsilon_7,    // epsilon polynom 7
30 
   epsilon_8,    // epsilon polynom 8
31 
   epsilon_9,    // epsilon polynom 9
32 
   epsilon_10,   // epsilon polynom 10
33 
   epsilon_11,   // epsilon polynom 11
34 
   epsilon_12,   // epsilon polynom 12
35 
   epsilon_13,   // epsilon polynom 13
36 
   epsilon_14,   // epsilon polynom 14
37 
   epsilon_15,   // epsilon polynom 15
38 
   epsilon_16,   // epsilon polynom 16
39 
   epsilon_17,   // epsilon polynom 17
40 
   epsilon_18,   // epsilon polynom 18
41 
   epsilon_19,   // epsilon polynom 19
42 
   epsilon_20,   // epsilon polynom 20
43 
   epsilon_21,   // epsilon polynom 21
44 
   epsilon_22,   // epsilon polynom 22
45 
   numErasure,   // erasure amount
46 
   fail,         // decoder failure signal
47 
   done          // done signal
48 
);
49 
 
50 
 
51 
   input          CLK;           // system clock
52 
   input          RESET;         // system reset
53 
   input          enable;        // enable signal
54 
   input          sync;          // sync signal
55 
   input          erasureIn;     // erasure input
56 
   output [7:0]   epsilon_0;     // syndrome polynom 0
57 
   output [7:0]   epsilon_1;     // syndrome polynom 1
58 
   output [7:0]   epsilon_2;     // syndrome polynom 2
59 
   output [7:0]   epsilon_3;     // syndrome polynom 3
60 
   output [7:0]   epsilon_4;     // syndrome polynom 4
61 
   output [7:0]   epsilon_5;     // syndrome polynom 5
62 
   output [7:0]   epsilon_6;     // syndrome polynom 6
63 
   output [7:0]   epsilon_7;     // syndrome polynom 7
64 
   output [7:0]   epsilon_8;     // syndrome polynom 8
65 
   output [7:0]   epsilon_9;     // syndrome polynom 9
66 
   output [7:0]   epsilon_10;    // syndrome polynom 10
67 
   output [7:0]   epsilon_11;    // syndrome polynom 11
68 
   output [7:0]   epsilon_12;    // syndrome polynom 12
69 
   output [7:0]   epsilon_13;    // syndrome polynom 13
70 
   output [7:0]   epsilon_14;    // syndrome polynom 14
71 
   output [7:0]   epsilon_15;    // syndrome polynom 15
72 
   output [7:0]   epsilon_16;    // syndrome polynom 16
73 
   output [7:0]   epsilon_17;    // syndrome polynom 17
74 
   output [7:0]   epsilon_18;    // syndrome polynom 18
75 
   output [7:0]   epsilon_19;    // syndrome polynom 19
76 
   output [7:0]   epsilon_20;    // syndrome polynom 20
77 
   output [7:0]   epsilon_21;    // syndrome polynom 21
78 
   output [7:0]   epsilon_22;    // syndrome polynom 22
79 
   output [4:0]   numErasure;    // erasure amount
80 
   output         fail;          // decoder failure signal
81 
   output         done;          // done signal
82 
   //------------------------------------------------------------------
83 
   // - parameters
84 
   //------------------------------------------------------------------
85 
   parameter erasureInitialPower = 8'd2;
86 
 
87 
 
88 
 
89 
   //------------------------------------------------------------------------
90 
   // + count
91 
   //- Counter
92 
   //------------------------------------------------------------------------
93 
  reg    [7:0]   count;
94 
   always @(posedge CLK or negedge RESET) begin
95 
      if (~RESET) begin
96 
         count [7:0] <= 8'd0;
97 
      end
98 
      else if (enable == 1'b1) begin
99 
         if (sync == 1'b1) begin
100 
            count[7:0] <= 8'd1;
101 
         end
102 
         else if ( (count[7:0] ==8'd0) || (count[7:0] ==8'd255)) begin
103 
            count[7:0] <= 8'd0;
104 
         end
105 
         else begin
106 
            count[7:0] <= count[7:0] + 8'd1;
107 
         end
108 
      end
109 
   end
110 
 
111 
 
112 
 
113 
   //------------------------------------------------------------------------
114 
   // + done
115 
   //------------------------------------------------------------------------
116 
   reg         done;
117 
   always @(count) begin
118 
      if (count ==8'd255) begin
119 
         done = 1'b1;
120 
      end
121 
      else begin
122 
         done = 1'b0;
123 
      end
124 
   end
125 
 
126 
 
127 
   //------------------------------------------------------------------------
128 
   // + erasureCount
129 
   //- Erasure Counter
130 
   //------------------------------------------------------------------------
131 
   reg    [7:0]   erasureCount;
132 
   always @(posedge CLK or negedge RESET) begin
133 
      if (~RESET) begin
134 
         erasureCount [7:0] <= 8'd0;
135 
      end
136 
      else if (enable == 1'b1) begin
137 
         if (sync == 1'b1) begin
138 
            if (erasureIn == 1'b1) begin
139 
               erasureCount [7:0] <= 8'd1;
140 
            end
141 
            else begin
142 
               erasureCount [7:0] <= 8'd0;
143 
            end
144 
         end
145 
         else if (erasureIn == 1'b1) begin
146 
            erasureCount [7:0] <= erasureCount [7:0] + 8'd1;
147 
         end
148 
      end
149 
   end
150 
 
151 
 
152 
   //------------------------------------------------------------------------
153 
   // + fail
154 
   //- If Erasure amount > 22 -> fail is ON
155 
   //------------------------------------------------------------------------
156 
   reg         fail;
157 
   always @(erasureCount) begin
158 
      if (erasureCount [7:0]> 8'd22) begin
159 
         fail = 1'b1;
160 
      end
161 
      else begin
162 
         fail = 1'b0;
163 
      end
164 
   end
165 
 
166 
 
167 
   //------------------------------------------------------------------------
168 
   // Erasure Polynominal Generator
169 
   //------------------------------------------------------------------------
170 
   reg    [7:0]    powerReg;
171 
   wire    [7:0]   powerNew;
172 
   wire    [7:0]   powerInitialNew;
173 
 
174 
   assign powerInitialNew [0] = erasureInitialPower[7];
175 
   assign powerInitialNew [1] = erasureInitialPower[0];
176 
   assign powerInitialNew [2] = erasureInitialPower[1] ^ erasureInitialPower[7];
177 
   assign powerInitialNew [3] = erasureInitialPower[2] ^ erasureInitialPower[7];
178 
   assign powerInitialNew [4] = erasureInitialPower[3] ^ erasureInitialPower[7];
179 
   assign powerInitialNew [5] = erasureInitialPower[4];
180 
   assign powerInitialNew [6] = erasureInitialPower[5];
181 
   assign powerInitialNew [7] = erasureInitialPower[6];
182 
   assign powerNew [0] = powerReg[7];
183 
   assign powerNew [1] = powerReg[0];
184 
   assign powerNew [2] = powerReg[1] ^ powerReg[7];
185 
   assign powerNew [3] = powerReg[2] ^ powerReg[7];
186 
   assign powerNew [4] = powerReg[3] ^ powerReg[7];
187 
   assign powerNew [5] = powerReg[4];
188 
   assign powerNew [6] = powerReg[5];
189 
   assign powerNew [7] = powerReg[6];
190 
 
191 
 
192 
   //------------------------------------------------------------------
193 
   // + powerReg
194 
   //------------------------------------------------------------------
195 
   always @(posedge CLK or negedge RESET) begin
196 
      if (~RESET) begin
197 
         powerReg [7:0] <= 8'd0;
198 
      end
199 
      else if (enable == 1'b1) begin
200 
         if (sync == 1'b1) begin
201 
            powerReg[7:0] <= powerInitialNew[7:0];
202 
         end
203 
         else begin
204 
            powerReg[7:0] <= powerNew[7:0];
205 
         end
206 
      end
207 
   end
208 
 
209 
 
210 
   //------------------------------------------------------------------------
211 
   // + product_0,..., product_22
212 
   //- Erasure Polynominal Generator
213 
   //------------------------------------------------------------------------
214 
   wire [7:0]   product_0;
215 
   wire [7:0]   product_1;
216 
   wire [7:0]   product_2;
217 
   wire [7:0]   product_3;
218 
   wire [7:0]   product_4;
219 
   wire [7:0]   product_5;
220 
   wire [7:0]   product_6;
221 
   wire [7:0]   product_7;
222 
   wire [7:0]   product_8;
223 
   wire [7:0]   product_9;
224 
   wire [7:0]   product_10;
225 
   wire [7:0]   product_11;
226 
   wire [7:0]   product_12;
227 
   wire [7:0]   product_13;
228 
   wire [7:0]   product_14;
229 
   wire [7:0]   product_15;
230 
   wire [7:0]   product_16;
231 
   wire [7:0]   product_17;
232 
   wire [7:0]   product_18;
233 
   wire [7:0]   product_19;
234 
   wire [7:0]   product_20;
235 
   wire [7:0]   product_21;
236 
   wire [7:0]   product_22;
237 
 
238 
   reg  [7:0]    epsilonReg_0;
239 
   reg  [7:0]    epsilonReg_1;
240 
   reg  [7:0]    epsilonReg_2;
241 
   reg  [7:0]    epsilonReg_3;
242 
   reg  [7:0]    epsilonReg_4;
243 
   reg  [7:0]    epsilonReg_5;
244 
   reg  [7:0]    epsilonReg_6;
245 
   reg  [7:0]    epsilonReg_7;
246 
   reg  [7:0]    epsilonReg_8;
247 
   reg  [7:0]    epsilonReg_9;
248 
   reg  [7:0]    epsilonReg_10;
249 
   reg  [7:0]    epsilonReg_11;
250 
   reg  [7:0]    epsilonReg_12;
251 
   reg  [7:0]    epsilonReg_13;
252 
   reg  [7:0]    epsilonReg_14;
253 
   reg  [7:0]    epsilonReg_15;
254 
   reg  [7:0]    epsilonReg_16;
255 
   reg  [7:0]    epsilonReg_17;
256 
   reg  [7:0]    epsilonReg_18;
257 
   reg  [7:0]    epsilonReg_19;
258 
   reg  [7:0]    epsilonReg_20;
259 
   reg  [7:0]    epsilonReg_21;
260 
   reg  [7:0]    epsilonReg_22;
261 
 
262 
 
263 
   RsDecodeMult   RsDecodeMult_0 (.A(powerReg[7:0]), .B(epsilonReg_0[7:0]), .P(product_0[7:0]));
264 
   RsDecodeMult   RsDecodeMult_1 (.A(powerReg[7:0]), .B(epsilonReg_1[7:0]), .P(product_1[7:0]));
265 
   RsDecodeMult   RsDecodeMult_2 (.A(powerReg[7:0]), .B(epsilonReg_2[7:0]), .P(product_2[7:0]));
266 
   RsDecodeMult   RsDecodeMult_3 (.A(powerReg[7:0]), .B(epsilonReg_3[7:0]), .P(product_3[7:0]));
267 
   RsDecodeMult   RsDecodeMult_4 (.A(powerReg[7:0]), .B(epsilonReg_4[7:0]), .P(product_4[7:0]));
268 
   RsDecodeMult   RsDecodeMult_5 (.A(powerReg[7:0]), .B(epsilonReg_5[7:0]), .P(product_5[7:0]));
269 
   RsDecodeMult   RsDecodeMult_6 (.A(powerReg[7:0]), .B(epsilonReg_6[7:0]), .P(product_6[7:0]));
270 
   RsDecodeMult   RsDecodeMult_7 (.A(powerReg[7:0]), .B(epsilonReg_7[7:0]), .P(product_7[7:0]));
271 
   RsDecodeMult   RsDecodeMult_8 (.A(powerReg[7:0]), .B(epsilonReg_8[7:0]), .P(product_8[7:0]));
272 
   RsDecodeMult   RsDecodeMult_9 (.A(powerReg[7:0]), .B(epsilonReg_9[7:0]), .P(product_9[7:0]));
273 
   RsDecodeMult   RsDecodeMult_10 (.A(powerReg[7:0]), .B(epsilonReg_10[7:0]), .P(product_10[7:0]));
274 
   RsDecodeMult   RsDecodeMult_11 (.A(powerReg[7:0]), .B(epsilonReg_11[7:0]), .P(product_11[7:0]));
275 
   RsDecodeMult   RsDecodeMult_12 (.A(powerReg[7:0]), .B(epsilonReg_12[7:0]), .P(product_12[7:0]));
276 
   RsDecodeMult   RsDecodeMult_13 (.A(powerReg[7:0]), .B(epsilonReg_13[7:0]), .P(product_13[7:0]));
277 
   RsDecodeMult   RsDecodeMult_14 (.A(powerReg[7:0]), .B(epsilonReg_14[7:0]), .P(product_14[7:0]));
278 
   RsDecodeMult   RsDecodeMult_15 (.A(powerReg[7:0]), .B(epsilonReg_15[7:0]), .P(product_15[7:0]));
279 
   RsDecodeMult   RsDecodeMult_16 (.A(powerReg[7:0]), .B(epsilonReg_16[7:0]), .P(product_16[7:0]));
280 
   RsDecodeMult   RsDecodeMult_17 (.A(powerReg[7:0]), .B(epsilonReg_17[7:0]), .P(product_17[7:0]));
281 
   RsDecodeMult   RsDecodeMult_18 (.A(powerReg[7:0]), .B(epsilonReg_18[7:0]), .P(product_18[7:0]));
282 
   RsDecodeMult   RsDecodeMult_19 (.A(powerReg[7:0]), .B(epsilonReg_19[7:0]), .P(product_19[7:0]));
283 
   RsDecodeMult   RsDecodeMult_20 (.A(powerReg[7:0]), .B(epsilonReg_20[7:0]), .P(product_20[7:0]));
284 
   RsDecodeMult   RsDecodeMult_21 (.A(powerReg[7:0]), .B(epsilonReg_21[7:0]), .P(product_21[7:0]));
285 
   RsDecodeMult   RsDecodeMult_22 (.A(powerReg[7:0]), .B(epsilonReg_22[7:0]), .P(product_22[7:0]));
286 
 
287 
 
288 
 
289 
   //------------------------------------------------------------------------
290 
   // + epsilonReg_0,..., epsilonReg_21
291 
   //------------------------------------------------------------------------
292 
   always @(posedge CLK or negedge RESET) begin
293 
      if (~RESET) begin
294 
         epsilonReg_0 [7:0]  <= 8'd0;
295 
         epsilonReg_1 [7:0]  <= 8'd0;
296 
         epsilonReg_2 [7:0]  <= 8'd0;
297 
         epsilonReg_3 [7:0]  <= 8'd0;
298 
         epsilonReg_4 [7:0]  <= 8'd0;
299 
         epsilonReg_5 [7:0]  <= 8'd0;
300 
         epsilonReg_6 [7:0]  <= 8'd0;
301 
         epsilonReg_7 [7:0]  <= 8'd0;
302 
         epsilonReg_8 [7:0]  <= 8'd0;
303 
         epsilonReg_9 [7:0]  <= 8'd0;
304 
         epsilonReg_10 [7:0] <= 8'd0;
305 
         epsilonReg_11 [7:0] <= 8'd0;
306 
         epsilonReg_12 [7:0] <= 8'd0;
307 
         epsilonReg_13 [7:0] <= 8'd0;
308 
         epsilonReg_14 [7:0] <= 8'd0;
309 
         epsilonReg_15 [7:0] <= 8'd0;
310 
         epsilonReg_16 [7:0] <= 8'd0;
311 
         epsilonReg_17 [7:0] <= 8'd0;
312 
         epsilonReg_18 [7:0] <= 8'd0;
313 
         epsilonReg_19 [7:0] <= 8'd0;
314 
         epsilonReg_20 [7:0] <= 8'd0;
315 
         epsilonReg_21 [7:0] <= 8'd0;
316 
         epsilonReg_22 [7:0] <= 8'd0;
317 
      end
318 
      else if (enable == 1'b1) begin
319 
         if (sync == 1'b1) begin
320 
            if (erasureIn == 1'b1) begin
321 
               epsilonReg_0 [7:0]   <= erasureInitialPower[7:0];
322 
               epsilonReg_1 [7:0]   <= 8'd1;
323 
               epsilonReg_2 [7:0]   <= 8'd0;
324 
               epsilonReg_3 [7:0]   <= 8'd0;
325 
               epsilonReg_4 [7:0]   <= 8'd0;
326 
               epsilonReg_5 [7:0]   <= 8'd0;
327 
               epsilonReg_6 [7:0]   <= 8'd0;
328 
               epsilonReg_7 [7:0]   <= 8'd0;
329 
               epsilonReg_8 [7:0]   <= 8'd0;
330 
               epsilonReg_9 [7:0]   <= 8'd0;
331 
               epsilonReg_10 [7:0]  <= 8'd0;
332 
               epsilonReg_11 [7:0]  <= 8'd0;
333 
               epsilonReg_12 [7:0]  <= 8'd0;
334 
               epsilonReg_13 [7:0]  <= 8'd0;
335 
               epsilonReg_14 [7:0]  <= 8'd0;
336 
               epsilonReg_15 [7:0]  <= 8'd0;
337 
               epsilonReg_16 [7:0]  <= 8'd0;
338 
               epsilonReg_17 [7:0]  <= 8'd0;
339 
               epsilonReg_18 [7:0]  <= 8'd0;
340 
               epsilonReg_19 [7:0]  <= 8'd0;
341 
               epsilonReg_20 [7:0]  <= 8'd0;
342 
               epsilonReg_21 [7:0]  <= 8'd0;
343 
               epsilonReg_22 [7:0]  <= 8'd0;
344 
            end
345 
            else begin
346 
               epsilonReg_0 [7:0]  <= 8'd1;
347 
               epsilonReg_1 [7:0]  <= 8'd0;
348 
               epsilonReg_2 [7:0]  <= 8'd0;
349 
               epsilonReg_3 [7:0]  <= 8'd0;
350 
               epsilonReg_4 [7:0]  <= 8'd0;
351 
               epsilonReg_5 [7:0]  <= 8'd0;
352 
               epsilonReg_6 [7:0]  <= 8'd0;
353 
               epsilonReg_7 [7:0]  <= 8'd0;
354 
               epsilonReg_8 [7:0]  <= 8'd0;
355 
               epsilonReg_9 [7:0]  <= 8'd0;
356 
               epsilonReg_10 [7:0] <= 8'd0;
357 
               epsilonReg_11 [7:0] <= 8'd0;
358 
               epsilonReg_12 [7:0] <= 8'd0;
359 
               epsilonReg_13 [7:0] <= 8'd0;
360 
               epsilonReg_14 [7:0] <= 8'd0;
361 
               epsilonReg_15 [7:0] <= 8'd0;
362 
               epsilonReg_16 [7:0] <= 8'd0;
363 
               epsilonReg_17 [7:0] <= 8'd0;
364 
               epsilonReg_18 [7:0] <= 8'd0;
365 
               epsilonReg_19 [7:0] <= 8'd0;
366 
               epsilonReg_20 [7:0] <= 8'd0;
367 
               epsilonReg_21 [7:0] <= 8'd0;
368 
               epsilonReg_22 [7:0] <= 8'd0;
369 
            end
370 
         end
371 
         else if (erasureIn == 1'b1) begin
372 
            epsilonReg_0 [7:0]  <= product_0[7:0];
373 
            epsilonReg_1 [7:0]  <= epsilonReg_0 [7:0] ^ product_1[7:0];
374 
            epsilonReg_2 [7:0]  <= epsilonReg_1 [7:0] ^ product_2[7:0];
375 
            epsilonReg_3 [7:0]  <= epsilonReg_2 [7:0] ^ product_3[7:0];
376 
            epsilonReg_4 [7:0]  <= epsilonReg_3 [7:0] ^ product_4[7:0];
377 
            epsilonReg_5 [7:0]  <= epsilonReg_4 [7:0] ^ product_5[7:0];
378 
            epsilonReg_6 [7:0]  <= epsilonReg_5 [7:0] ^ product_6[7:0];
379 
            epsilonReg_7 [7:0]  <= epsilonReg_6 [7:0] ^ product_7[7:0];
380 
            epsilonReg_8 [7:0]  <= epsilonReg_7 [7:0] ^ product_8[7:0];
381 
            epsilonReg_9 [7:0]  <= epsilonReg_8 [7:0] ^ product_9[7:0];
382 
            epsilonReg_10 [7:0] <= epsilonReg_9 [7:0] ^ product_10[7:0];
383 
            epsilonReg_11 [7:0] <= epsilonReg_10 [7:0] ^ product_11[7:0];
384 
            epsilonReg_12 [7:0] <= epsilonReg_11 [7:0] ^ product_12[7:0];
385 
            epsilonReg_13 [7:0] <= epsilonReg_12 [7:0] ^ product_13[7:0];
386 
            epsilonReg_14 [7:0] <= epsilonReg_13 [7:0] ^ product_14[7:0];
387 
            epsilonReg_15 [7:0] <= epsilonReg_14 [7:0] ^ product_15[7:0];
388 
            epsilonReg_16 [7:0] <= epsilonReg_15 [7:0] ^ product_16[7:0];
389 
            epsilonReg_17 [7:0] <= epsilonReg_16 [7:0] ^ product_17[7:0];
390 
            epsilonReg_18 [7:0] <= epsilonReg_17 [7:0] ^ product_18[7:0];
391 
            epsilonReg_19 [7:0] <= epsilonReg_18 [7:0] ^ product_19[7:0];
392 
            epsilonReg_20 [7:0] <= epsilonReg_19 [7:0] ^ product_20[7:0];
393 
            epsilonReg_21 [7:0] <= epsilonReg_20 [7:0] ^ product_21[7:0];
394 
            epsilonReg_22 [7:0] <= epsilonReg_21 [7:0] ^ product_22[7:0];
395 
         end
396 
      end
397 
   end
398 
 
399 
 
400 
 
401 
   //------------------------------------------------------------------------
402 
   //- Output Ports
403 
   //------------------------------------------------------------------------
404 
   assign epsilon_0 [7:0]   = epsilonReg_0[7:0];
405 
   assign epsilon_1 [7:0]   = epsilonReg_1[7:0];
406 
   assign epsilon_2 [7:0]   = epsilonReg_2[7:0];
407 
   assign epsilon_3 [7:0]   = epsilonReg_3[7:0];
408 
   assign epsilon_4 [7:0]   = epsilonReg_4[7:0];
409 
   assign epsilon_5 [7:0]   = epsilonReg_5[7:0];
410 
   assign epsilon_6 [7:0]   = epsilonReg_6[7:0];
411 
   assign epsilon_7 [7:0]   = epsilonReg_7[7:0];
412 
   assign epsilon_8 [7:0]   = epsilonReg_8[7:0];
413 
   assign epsilon_9 [7:0]   = epsilonReg_9[7:0];
414 
   assign epsilon_10 [7:0]  = epsilonReg_10[7:0];
415 
   assign epsilon_11 [7:0]  = epsilonReg_11[7:0];
416 
   assign epsilon_12 [7:0]  = epsilonReg_12[7:0];
417 
   assign epsilon_13 [7:0]  = epsilonReg_13[7:0];
418 
   assign epsilon_14 [7:0]  = epsilonReg_14[7:0];
419 
   assign epsilon_15 [7:0]  = epsilonReg_15[7:0];
420 
   assign epsilon_16 [7:0]  = epsilonReg_16[7:0];
421 
   assign epsilon_17 [7:0]  = epsilonReg_17[7:0];
422 
   assign epsilon_18 [7:0]  = epsilonReg_18[7:0];
423 
   assign epsilon_19 [7:0]  = epsilonReg_19[7:0];
424 
   assign epsilon_20 [7:0]  = epsilonReg_20[7:0];
425 
   assign epsilon_21 [7:0]  = epsilonReg_21[7:0];
426 
   assign epsilon_22 [7:0]  = epsilonReg_22[7:0];
427 
 
428 
   assign numErasure   = erasureCount[4:0];
429 
 
430 
endmodule

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