OpenCores
URL https://opencores.org/ocsvn/reed_solomon_codec_generator/reed_solomon_codec_generator/trunk

Subversion Repositories reed_solomon_codec_generator

[/] [reed_solomon_codec_generator/] [trunk/] [example/] [rtl/] [RsDecodeEuclide.v] - Blame information for rev 4

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 4 issei 
//===================================================================
2 
// Module Name : RsDecodeEuclide
3 
// File Name   : RsDecodeEuclide.v
4 
// Function    : Rs Decoder Euclide algorithm Module
5 
//
6 
// Revision History:
7 
// Date          By           Version    Change Description
8 
//===================================================================
9 
// 2009/02/03  Gael Sapience     1.0       Original
10 
//
11 
//===================================================================
12 
// (C) COPYRIGHT 2009 SYSTEM LSI CO., Ltd.
13 
//
14 
 
15 
 
16 
module RsDecodeEuclide(
17 
   CLK,           // system clock
18 
   RESET,         // system reset
19 
   enable,        // enable signal
20 
   sync,          // sync signal
21 
   syndrome_0,    // syndrome polynom 0
22 
   syndrome_1,    // syndrome polynom 1
23 
   syndrome_2,    // syndrome polynom 2
24 
   syndrome_3,    // syndrome polynom 3
25 
   syndrome_4,    // syndrome polynom 4
26 
   syndrome_5,    // syndrome polynom 5
27 
   syndrome_6,    // syndrome polynom 6
28 
   syndrome_7,    // syndrome polynom 7
29 
   syndrome_8,    // syndrome polynom 8
30 
   syndrome_9,    // syndrome polynom 9
31 
   syndrome_10,   // syndrome polynom 10
32 
   syndrome_11,   // syndrome polynom 11
33 
   syndrome_12,   // syndrome polynom 12
34 
   syndrome_13,   // syndrome polynom 13
35 
   syndrome_14,   // syndrome polynom 14
36 
   syndrome_15,   // syndrome polynom 15
37 
   syndrome_16,   // syndrome polynom 16
38 
   syndrome_17,   // syndrome polynom 17
39 
   syndrome_18,   // syndrome polynom 18
40 
   syndrome_19,   // syndrome polynom 19
41 
   syndrome_20,   // syndrome polynom 20
42 
   syndrome_21,   // syndrome polynom 21
43 
   numErasure,    // erasure amount
44 
   lambda_0,      // lambda polynom 0
45 
   lambda_1,      // lambda polynom 1
46 
   lambda_2,      // lambda polynom 2
47 
   lambda_3,      // lambda polynom 3
48 
   lambda_4,      // lambda polynom 4
49 
   lambda_5,      // lambda polynom 5
50 
   lambda_6,      // lambda polynom 6
51 
   lambda_7,      // lambda polynom 7
52 
   lambda_8,      // lambda polynom 8
53 
   lambda_9,      // lambda polynom 9
54 
   lambda_10,     // lambda polynom 10
55 
   lambda_11,     // lambda polynom 11
56 
   lambda_12,     // lambda polynom 12
57 
   lambda_13,     // lambda polynom 13
58 
   lambda_14,     // lambda polynom 14
59 
   lambda_15,     // lambda polynom 15
60 
   lambda_16,     // lambda polynom 16
61 
   lambda_17,     // lambda polynom 17
62 
   lambda_18,     // lambda polynom 18
63 
   lambda_19,     // lambda polynom 19
64 
   lambda_20,     // lambda polynom 20
65 
   lambda_21,     // lambda polynom 21
66 
   omega_0,       // omega polynom 0
67 
   omega_1,       // omega polynom 1
68 
   omega_2,       // omega polynom 2
69 
   omega_3,       // omega polynom 3
70 
   omega_4,       // omega polynom 4
71 
   omega_5,       // omega polynom 5
72 
   omega_6,       // omega polynom 6
73 
   omega_7,       // omega polynom 7
74 
   omega_8,       // omega polynom 8
75 
   omega_9,       // omega polynom 9
76 
   omega_10,      // omega polynom 10
77 
   omega_11,      // omega polynom 11
78 
   omega_12,      // omega polynom 12
79 
   omega_13,      // omega polynom 13
80 
   omega_14,      // omega polynom 14
81 
   omega_15,      // omega polynom 15
82 
   omega_16,      // omega polynom 16
83 
   omega_17,      // omega polynom 17
84 
   omega_18,      // omega polynom 18
85 
   omega_19,      // omega polynom 19
86 
   omega_20,      // omega polynom 20
87 
   omega_21,      // omega polynom 21
88 
   numShifted,    // shift amount
89 
   done           // done signal
90 
);
91 
 
92 
 
93 
   input          CLK;           // system clock
94 
   input          RESET;         // system reset
95 
   input          enable;        // enable signal
96 
   input          sync;          // sync signal
97 
   input  [7:0]   syndrome_0;    // syndrome polynom 0
98 
   input  [7:0]   syndrome_1;    // syndrome polynom 1
99 
   input  [7:0]   syndrome_2;    // syndrome polynom 2
100 
   input  [7:0]   syndrome_3;    // syndrome polynom 3
101 
   input  [7:0]   syndrome_4;    // syndrome polynom 4
102 
   input  [7:0]   syndrome_5;    // syndrome polynom 5
103 
   input  [7:0]   syndrome_6;    // syndrome polynom 6
104 
   input  [7:0]   syndrome_7;    // syndrome polynom 7
105 
   input  [7:0]   syndrome_8;    // syndrome polynom 8
106 
   input  [7:0]   syndrome_9;    // syndrome polynom 9
107 
   input  [7:0]   syndrome_10;   // syndrome polynom 10
108 
   input  [7:0]   syndrome_11;   // syndrome polynom 11
109 
   input  [7:0]   syndrome_12;   // syndrome polynom 12
110 
   input  [7:0]   syndrome_13;   // syndrome polynom 13
111 
   input  [7:0]   syndrome_14;   // syndrome polynom 14
112 
   input  [7:0]   syndrome_15;   // syndrome polynom 15
113 
   input  [7:0]   syndrome_16;   // syndrome polynom 16
114 
   input  [7:0]   syndrome_17;   // syndrome polynom 17
115 
   input  [7:0]   syndrome_18;   // syndrome polynom 18
116 
   input  [7:0]   syndrome_19;   // syndrome polynom 19
117 
   input  [7:0]   syndrome_20;   // syndrome polynom 20
118 
   input  [7:0]   syndrome_21;   // syndrome polynom 21
119 
   input  [4:0]   numErasure;    // erasure amount
120 
 
121 
   output [7:0]   lambda_0;       // lambda polynom 0
122 
   output [7:0]   lambda_1;       // lambda polynom 1
123 
   output [7:0]   lambda_2;       // lambda polynom 2
124 
   output [7:0]   lambda_3;       // lambda polynom 3
125 
   output [7:0]   lambda_4;       // lambda polynom 4
126 
   output [7:0]   lambda_5;       // lambda polynom 5
127 
   output [7:0]   lambda_6;       // lambda polynom 6
128 
   output [7:0]   lambda_7;       // lambda polynom 7
129 
   output [7:0]   lambda_8;       // lambda polynom 8
130 
   output [7:0]   lambda_9;       // lambda polynom 9
131 
   output [7:0]   lambda_10;      // lambda polynom 10
132 
   output [7:0]   lambda_11;      // lambda polynom 11
133 
   output [7:0]   lambda_12;      // lambda polynom 12
134 
   output [7:0]   lambda_13;      // lambda polynom 13
135 
   output [7:0]   lambda_14;      // lambda polynom 14
136 
   output [7:0]   lambda_15;      // lambda polynom 15
137 
   output [7:0]   lambda_16;      // lambda polynom 16
138 
   output [7:0]   lambda_17;      // lambda polynom 17
139 
   output [7:0]   lambda_18;      // lambda polynom 18
140 
   output [7:0]   lambda_19;      // lambda polynom 19
141 
   output [7:0]   lambda_20;      // lambda polynom 20
142 
   output [7:0]   lambda_21;      // lambda polynom 21
143 
   output [7:0]   omega_0;        // omega polynom 0
144 
   output [7:0]   omega_1;        // omega polynom 1
145 
   output [7:0]   omega_2;        // omega polynom 2
146 
   output [7:0]   omega_3;        // omega polynom 3
147 
   output [7:0]   omega_4;        // omega polynom 4
148 
   output [7:0]   omega_5;        // omega polynom 5
149 
   output [7:0]   omega_6;        // omega polynom 6
150 
   output [7:0]   omega_7;        // omega polynom 7
151 
   output [7:0]   omega_8;        // omega polynom 8
152 
   output [7:0]   omega_9;        // omega polynom 9
153 
   output [7:0]   omega_10;       // omega polynom 10
154 
   output [7:0]   omega_11;       // omega polynom 11
155 
   output [7:0]   omega_12;       // omega polynom 12
156 
   output [7:0]   omega_13;       // omega polynom 13
157 
   output [7:0]   omega_14;       // omega polynom 14
158 
   output [7:0]   omega_15;       // omega polynom 15
159 
   output [7:0]   omega_16;       // omega polynom 16
160 
   output [7:0]   omega_17;       // omega polynom 17
161 
   output [7:0]   omega_18;       // omega polynom 18
162 
   output [7:0]   omega_19;       // omega polynom 19
163 
   output [7:0]   omega_20;       // omega polynom 20
164 
   output [7:0]   omega_21;       // omega polynom 21
165 
   output [4:0]   numShifted;     // shift amount
166 
   output         done;           // done signal
167 
 
168 
 
169 
 
170 
 
171 
 
172 
   //------------------------------------------------------------------------
173 
   // -registers
174 
   //------------------------------------------------------------------------
175 
   reg [7:0]   omegaBkp_0;
176 
   reg [7:0]   omegaBkp_1;
177 
   reg [7:0]   omegaBkp_2;
178 
   reg [7:0]   omegaBkp_3;
179 
   reg [7:0]   omegaBkp_4;
180 
   reg [7:0]   omegaBkp_5;
181 
   reg [7:0]   omegaBkp_6;
182 
   reg [7:0]   omegaBkp_7;
183 
   reg [7:0]   omegaBkp_8;
184 
   reg [7:0]   omegaBkp_9;
185 
   reg [7:0]   omegaBkp_10;
186 
   reg [7:0]   omegaBkp_11;
187 
   reg [7:0]   omegaBkp_12;
188 
   reg [7:0]   omegaBkp_13;
189 
   reg [7:0]   omegaBkp_14;
190 
   reg [7:0]   omegaBkp_15;
191 
   reg [7:0]   omegaBkp_16;
192 
   reg [7:0]   omegaBkp_17;
193 
   reg [7:0]   omegaBkp_18;
194 
   reg [7:0]   omegaBkp_19;
195 
   reg [7:0]   omegaBkp_20;
196 
   reg [7:0]   omegaBkp_21;
197 
   reg [7:0]   lambdaBkp_0;
198 
   reg [7:0]   lambdaBkp_1;
199 
   reg [7:0]   lambdaBkp_2;
200 
   reg [7:0]   lambdaBkp_3;
201 
   reg [7:0]   lambdaBkp_4;
202 
   reg [7:0]   lambdaBkp_5;
203 
   reg [7:0]   lambdaBkp_6;
204 
   reg [7:0]   lambdaBkp_7;
205 
   reg [7:0]   lambdaBkp_8;
206 
   reg [7:0]   lambdaBkp_9;
207 
   reg [7:0]   lambdaBkp_10;
208 
   reg [7:0]   lambdaBkp_11;
209 
   reg [7:0]   lambdaBkp_12;
210 
   reg [7:0]   lambdaBkp_13;
211 
   reg [7:0]   lambdaBkp_14;
212 
   reg [7:0]   lambdaBkp_15;
213 
   reg [7:0]   lambdaBkp_16;
214 
   reg [7:0]   lambdaBkp_17;
215 
   reg [7:0]   lambdaBkp_18;
216 
   reg [7:0]   lambdaBkp_19;
217 
   reg [7:0]   lambdaBkp_20;
218 
   reg [7:0]   lambdaBkp_21;
219 
   reg [7:0]   lambdaInner_0;
220 
   reg [7:0]   lambdaInner_1;
221 
   reg [7:0]   lambdaInner_2;
222 
   reg [7:0]   lambdaInner_3;
223 
   reg [7:0]   lambdaInner_4;
224 
   reg [7:0]   lambdaInner_5;
225 
   reg [7:0]   lambdaInner_6;
226 
   reg [7:0]   lambdaInner_7;
227 
   reg [7:0]   lambdaInner_8;
228 
   reg [7:0]   lambdaInner_9;
229 
   reg [7:0]   lambdaInner_10;
230 
   reg [7:0]   lambdaInner_11;
231 
   reg [7:0]   lambdaInner_12;
232 
   reg [7:0]   lambdaInner_13;
233 
   reg [7:0]   lambdaInner_14;
234 
   reg [7:0]   lambdaInner_15;
235 
   reg [7:0]   lambdaInner_16;
236 
   reg [7:0]   lambdaInner_17;
237 
   reg [7:0]   lambdaInner_18;
238 
   reg [7:0]   lambdaInner_19;
239 
   reg [7:0]   lambdaInner_20;
240 
   reg [7:0]   lambdaInner_21;
241 
   reg [7:0]   lambdaXorReg_0;
242 
   reg [7:0]   lambdaXorReg_1;
243 
   reg [7:0]   lambdaXorReg_2;
244 
   reg [7:0]   lambdaXorReg_3;
245 
   reg [7:0]   lambdaXorReg_4;
246 
   reg [7:0]   lambdaXorReg_5;
247 
   reg [7:0]   lambdaXorReg_6;
248 
   reg [7:0]   lambdaXorReg_7;
249 
   reg [7:0]   lambdaXorReg_8;
250 
   reg [7:0]   lambdaXorReg_9;
251 
   reg [7:0]   lambdaXorReg_10;
252 
   reg [7:0]   lambdaXorReg_11;
253 
   reg [7:0]   lambdaXorReg_12;
254 
   reg [7:0]   lambdaXorReg_13;
255 
   reg [7:0]   lambdaXorReg_14;
256 
   reg [7:0]   lambdaXorReg_15;
257 
   reg [7:0]   lambdaXorReg_16;
258 
   reg [7:0]   lambdaXorReg_17;
259 
   reg [7:0]   lambdaXorReg_18;
260 
   reg [7:0]   lambdaXorReg_19;
261 
   reg [7:0]   lambdaXorReg_20;
262 
   wire [7:0]   omegaMultqNew_0;
263 
   wire [7:0]   omegaMultqNew_1;
264 
   wire [7:0]   omegaMultqNew_2;
265 
   wire [7:0]   omegaMultqNew_3;
266 
   wire [7:0]   omegaMultqNew_4;
267 
   wire [7:0]   omegaMultqNew_5;
268 
   wire [7:0]   omegaMultqNew_6;
269 
   wire [7:0]   omegaMultqNew_7;
270 
   wire [7:0]   omegaMultqNew_8;
271 
   wire [7:0]   omegaMultqNew_9;
272 
   wire [7:0]   omegaMultqNew_10;
273 
   wire [7:0]   omegaMultqNew_11;
274 
   wire [7:0]   omegaMultqNew_12;
275 
   wire [7:0]   omegaMultqNew_13;
276 
   wire [7:0]   omegaMultqNew_14;
277 
   wire [7:0]   omegaMultqNew_15;
278 
   wire [7:0]   omegaMultqNew_16;
279 
   wire [7:0]   omegaMultqNew_17;
280 
   wire [7:0]   omegaMultqNew_18;
281 
   wire [7:0]   omegaMultqNew_19;
282 
   wire [7:0]   omegaMultqNew_20;
283 
   wire [7:0]   lambdaMultqNew_0;
284 
   wire [7:0]   lambdaMultqNew_1;
285 
   wire [7:0]   lambdaMultqNew_2;
286 
   wire [7:0]   lambdaMultqNew_3;
287 
   wire [7:0]   lambdaMultqNew_4;
288 
   wire [7:0]   lambdaMultqNew_5;
289 
   wire [7:0]   lambdaMultqNew_6;
290 
   wire [7:0]   lambdaMultqNew_7;
291 
   wire [7:0]   lambdaMultqNew_8;
292 
   wire [7:0]   lambdaMultqNew_9;
293 
   wire [7:0]   lambdaMultqNew_10;
294 
   wire [7:0]   lambdaMultqNew_11;
295 
   wire [7:0]   lambdaMultqNew_12;
296 
   wire [7:0]   lambdaMultqNew_13;
297 
   wire [7:0]   lambdaMultqNew_14;
298 
   wire [7:0]   lambdaMultqNew_15;
299 
   wire [7:0]   lambdaMultqNew_16;
300 
   wire [7:0]   lambdaMultqNew_17;
301 
   wire [7:0]   lambdaMultqNew_18;
302 
   wire [7:0]   lambdaMultqNew_19;
303 
   wire [7:0]   lambdaMultqNew_20;
304 
   wire [7:0]   lambdaMultqNew_21;
305 
   reg  [4:0]   offset;
306 
   reg  [4:0]   numShiftedReg;
307 
 
308 
 
309 
 
310 
   //------------------------------------------------------------------------
311 
   // + phase
312 
   // Counters
313 
   //------------------------------------------------------------------------
314 
   reg     [1:0]   phase;
315 
   always @(posedge CLK or negedge RESET) begin
316 
      if (~RESET) begin
317 
         phase [1:0] <= 2'd0;
318 
      end
319 
      else if (enable == 1'b1) begin
320 
         if (sync == 1'b1) begin
321 
            phase [1:0] <= 2'd1;
322 
         end
323 
         else if (phase [1:0] == 2'd2) begin
324 
            phase [1:0] <= 2'd0;
325 
         end
326 
         else begin
327 
            phase [1:0] <= phase [1:0] + 2'd1;
328 
         end
329 
      end
330 
   end
331 
 
332 
 
333 
 
334 
   //------------------------------------------------------------------------
335 
   // + count
336 
   //- Counter
337 
   //------------------------------------------------------------------------
338 
   reg     [6:0]   count;
339 
   always @(posedge CLK or negedge RESET) begin
340 
      if (~RESET) begin
341 
         count [6:0] <= 7'd0;
342 
      end
343 
      else if (enable == 1'b1) begin
344 
         if (sync == 1'b1) begin
345 
            count [6:0] <= 7'd1;
346 
         end
347 
         else if ( (count [6:0]==7'd0) ||  (count [6:0]==7'd69) ) begin
348 
            count [6:0] <= 7'd0;
349 
         end
350 
         else begin
351 
            count [6:0] <=  count [6:0] + 7'd1;
352 
         end
353 
      end
354 
   end
355 
 
356 
 
357 
 
358 
   //------------------------------------------------------------------
359 
   // + skip
360 
   //------------------------------------------------------------------
361 
   reg [7:0]   omegaInner_0;
362 
   reg [7:0]   omegaInner_1;
363 
   reg [7:0]   omegaInner_2;
364 
   reg [7:0]   omegaInner_3;
365 
   reg [7:0]   omegaInner_4;
366 
   reg [7:0]   omegaInner_5;
367 
   reg [7:0]   omegaInner_6;
368 
   reg [7:0]   omegaInner_7;
369 
   reg [7:0]   omegaInner_8;
370 
   reg [7:0]   omegaInner_9;
371 
   reg [7:0]   omegaInner_10;
372 
   reg [7:0]   omegaInner_11;
373 
   reg [7:0]   omegaInner_12;
374 
   reg [7:0]   omegaInner_13;
375 
   reg [7:0]   omegaInner_14;
376 
   reg [7:0]   omegaInner_15;
377 
   reg [7:0]   omegaInner_16;
378 
   reg [7:0]   omegaInner_17;
379 
   reg [7:0]   omegaInner_18;
380 
   reg [7:0]   omegaInner_19;
381 
   reg [7:0]   omegaInner_20;
382 
   reg [7:0]   omegaInner_21;
383 
   reg         skip;
384 
 
385 
   always @(omegaInner_21) begin
386 
      if (omegaInner_21 [7:0] == 8'd0) begin
387 
         skip   = 1'b1;
388 
      end else begin
389 
         skip   = 1'b0;
390 
      end
391 
   end
392 
 
393 
 
394 
   //------------------------------------------------------------------------
395 
   // + done
396 
   //------------------------------------------------------------------------
397 
   reg         done;
398 
   always @(count) begin
399 
      if (count[6:0] == 7'd69) begin
400 
         done = 1'b1;
401 
      end
402 
      else begin
403 
         done = 1'b0;
404 
      end
405 
   end
406 
 
407 
 
408 
   //------------------------------------------------------------------
409 
   // + euclideSteps
410 
   //------------------------------------------------------------------
411 
   reg     [6:0]   euclideSteps;
412 
   always @(posedge CLK or negedge RESET) begin
413 
      if (~RESET) begin
414 
         euclideSteps <= 7'd0;
415 
      end
416 
      else if (sync) begin
417 
      case (numErasure[4:0])
418 
         5'd0: begin
419 
            euclideSteps[6:0] <=  7'd69; // step: 0
420 
         end
421 
         5'd1: begin
422 
            euclideSteps[6:0] <=  7'd63; // step: 1
423 
         end
424 
         5'd2: begin
425 
            euclideSteps[6:0] <=  7'd63; // step: 2
426 
         end
427 
         5'd3: begin
428 
            euclideSteps[6:0] <=  7'd57; // step: 3
429 
         end
430 
         5'd4: begin
431 
            euclideSteps[6:0] <=  7'd57; // step: 4
432 
         end
433 
         5'd5: begin
434 
            euclideSteps[6:0] <=  7'd51; // step: 5
435 
         end
436 
         5'd6: begin
437 
            euclideSteps[6:0] <=  7'd51; // step: 6
438 
         end
439 
         5'd7: begin
440 
            euclideSteps[6:0] <=  7'd45; // step: 7
441 
         end
442 
         5'd8: begin
443 
            euclideSteps[6:0] <=  7'd45; // step: 8
444 
         end
445 
         5'd9: begin
446 
            euclideSteps[6:0] <=  7'd39; // step: 9
447 
         end
448 
         5'd10: begin
449 
            euclideSteps[6:0] <=  7'd39; // step: 10
450 
         end
451 
         5'd11: begin
452 
            euclideSteps[6:0] <=  7'd33; // step: 11
453 
         end
454 
         5'd12: begin
455 
            euclideSteps[6:0] <=  7'd33; // step: 12
456 
         end
457 
         5'd13: begin
458 
            euclideSteps[6:0] <=  7'd27; // step: 13
459 
         end
460 
         5'd14: begin
461 
            euclideSteps[6:0] <=  7'd27; // step: 14
462 
         end
463 
         5'd15: begin
464 
            euclideSteps[6:0] <=  7'd21; // step: 15
465 
         end
466 
         5'd16: begin
467 
            euclideSteps[6:0] <=  7'd21; // step: 16
468 
         end
469 
         5'd17: begin
470 
            euclideSteps[6:0] <=  7'd15; // step: 17
471 
         end
472 
         5'd18: begin
473 
            euclideSteps[6:0] <=  7'd15; // step: 18
474 
         end
475 
         5'd19: begin
476 
            euclideSteps[6:0] <=  7'd9; // step: 19
477 
         end
478 
         5'd20: begin
479 
            euclideSteps[6:0] <=  7'd9; // step: 20
480 
         end
481 
         5'd21: begin
482 
            euclideSteps[6:0] <=  7'd3; // step: 21
483 
         end
484 
         5'd22: begin
485 
            euclideSteps[6:0] <=  7'd3; // step: 22
486 
         end
487 
         default: begin
488 
            euclideSteps[6:0] <= 7'd0;
489 
         end
490 
      endcase
491 
     end
492 
   end
493 
 
494 
 
495 
   //------------------------------------------------------------------
496 
   // + enable_E
497 
   //------------------------------------------------------------------
498 
   reg          enable_E;
499 
   always @(sync or count or enable or numErasure or euclideSteps) begin
500 
      if (numErasure[4:0] <= 5'd22) begin
501 
         if ((sync == 1'b1) || (count[6:0] <= euclideSteps[6:0])) begin
502 
            enable_E   = enable;
503 
         end
504 
         else begin
505 
            enable_E   = 1'b0;
506 
         end
507 
      end
508 
      else begin
509 
         if ((sync == 1'b1) || (count[6:0] <= 7'd3)) begin
510 
            enable_E   = enable;
511 
         end
512 
         else begin
513 
            enable_E   = 1'b0;
514 
         end
515 
      end
516 
   end
517 
 
518 
 
519 
   //------------------------------------------------------------------------
520 
   // Get Partial Q
521 
   //------------------------------------------------------------------------
522 
   wire   [7:0]   omegaInv;
523 
   reg    [7:0]   omegaInvReg;
524 
   wire   [7:0]   qNew;
525 
   reg    [7:0]   qNewReg;
526 
   reg    [7:0]   omegaBkpReg;
527 
 
528 
   RsDecodeInv RsDecodeInv_Q (.B(omegaInner_21[7:0]), .R(omegaInv[7:0]));
529 
   RsDecodeMult RsDecodeMult_Q (.A(omegaBkpReg[7:0]), .B(omegaInvReg[7:0]), .P(qNew[7:0]) );
530 
 
531 
 
532 
   //------------------------------------------------------------------
533 
   // + omegaInvReg
534 
   //------------------------------------------------------------------
535 
   always @(posedge CLK or negedge RESET) begin
536 
      if (~RESET) begin
537 
         omegaInvReg   <= 8'd0;
538 
      end
539 
      else if (enable == 1'b1) begin
540 
         omegaInvReg   <= omegaInv;
541 
      end
542 
   end
543 
 
544 
 
545 
   //------------------------------------------------------------------
546 
   // + omegaBkpReg
547 
   //------------------------------------------------------------------
548 
   always @(posedge CLK or negedge RESET) begin
549 
      if (~RESET) begin
550 
         omegaBkpReg   <= 8'd0;
551 
      end
552 
      else if (enable == 1'b1) begin
553 
         omegaBkpReg   <= omegaBkp_21[7:0];
554 
      end
555 
   end
556 
 
557 
 
558 
   //------------------------------------------------------------------
559 
   // + qNewReg
560 
   //------------------------------------------------------------------
561 
   always @(posedge CLK or negedge RESET) begin
562 
      if (~RESET) begin
563 
         qNewReg   <= 8'd0;
564 
      end
565 
      else if (enable == 1'b1) begin
566 
         qNewReg   <= qNew;
567 
      end
568 
   end
569 
 
570 
 
571 
   //------------------------------------------------------------------------
572 
   // + omegaMultqNew_0,..., omegaMultqNew_18
573 
   //- QT = qNewReg * omegaInner
574 
   //- Multipliers
575 
   //------------------------------------------------------------------------
576 
   RsDecodeMult   RsDecodeMult_PDIV0 (.A(qNewReg[7:0]), .B(omegaInner_0[7:0]), .P(omegaMultqNew_0[7:0]) );
577 
   RsDecodeMult   RsDecodeMult_PDIV1 (.A(qNewReg[7:0]), .B(omegaInner_1[7:0]), .P(omegaMultqNew_1[7:0]) );
578 
   RsDecodeMult   RsDecodeMult_PDIV2 (.A(qNewReg[7:0]), .B(omegaInner_2[7:0]), .P(omegaMultqNew_2[7:0]) );
579 
   RsDecodeMult   RsDecodeMult_PDIV3 (.A(qNewReg[7:0]), .B(omegaInner_3[7:0]), .P(omegaMultqNew_3[7:0]) );
580 
   RsDecodeMult   RsDecodeMult_PDIV4 (.A(qNewReg[7:0]), .B(omegaInner_4[7:0]), .P(omegaMultqNew_4[7:0]) );
581 
   RsDecodeMult   RsDecodeMult_PDIV5 (.A(qNewReg[7:0]), .B(omegaInner_5[7:0]), .P(omegaMultqNew_5[7:0]) );
582 
   RsDecodeMult   RsDecodeMult_PDIV6 (.A(qNewReg[7:0]), .B(omegaInner_6[7:0]), .P(omegaMultqNew_6[7:0]) );
583 
   RsDecodeMult   RsDecodeMult_PDIV7 (.A(qNewReg[7:0]), .B(omegaInner_7[7:0]), .P(omegaMultqNew_7[7:0]) );
584 
   RsDecodeMult   RsDecodeMult_PDIV8 (.A(qNewReg[7:0]), .B(omegaInner_8[7:0]), .P(omegaMultqNew_8[7:0]) );
585 
   RsDecodeMult   RsDecodeMult_PDIV9 (.A(qNewReg[7:0]), .B(omegaInner_9[7:0]), .P(omegaMultqNew_9[7:0]) );
586 
   RsDecodeMult   RsDecodeMult_PDIV10 (.A(qNewReg[7:0]), .B(omegaInner_10[7:0]), .P(omegaMultqNew_10[7:0]) );
587 
   RsDecodeMult   RsDecodeMult_PDIV11 (.A(qNewReg[7:0]), .B(omegaInner_11[7:0]), .P(omegaMultqNew_11[7:0]) );
588 
   RsDecodeMult   RsDecodeMult_PDIV12 (.A(qNewReg[7:0]), .B(omegaInner_12[7:0]), .P(omegaMultqNew_12[7:0]) );
589 
   RsDecodeMult   RsDecodeMult_PDIV13 (.A(qNewReg[7:0]), .B(omegaInner_13[7:0]), .P(omegaMultqNew_13[7:0]) );
590 
   RsDecodeMult   RsDecodeMult_PDIV14 (.A(qNewReg[7:0]), .B(omegaInner_14[7:0]), .P(omegaMultqNew_14[7:0]) );
591 
   RsDecodeMult   RsDecodeMult_PDIV15 (.A(qNewReg[7:0]), .B(omegaInner_15[7:0]), .P(omegaMultqNew_15[7:0]) );
592 
   RsDecodeMult   RsDecodeMult_PDIV16 (.A(qNewReg[7:0]), .B(omegaInner_16[7:0]), .P(omegaMultqNew_16[7:0]) );
593 
   RsDecodeMult   RsDecodeMult_PDIV17 (.A(qNewReg[7:0]), .B(omegaInner_17[7:0]), .P(omegaMultqNew_17[7:0]) );
594 
   RsDecodeMult   RsDecodeMult_PDIV18 (.A(qNewReg[7:0]), .B(omegaInner_18[7:0]), .P(omegaMultqNew_18[7:0]) );
595 
   RsDecodeMult   RsDecodeMult_PDIV19 (.A(qNewReg[7:0]), .B(omegaInner_19[7:0]), .P(omegaMultqNew_19[7:0]) );
596 
   RsDecodeMult   RsDecodeMult_PDIV20 (.A(qNewReg[7:0]), .B(omegaInner_20[7:0]), .P(omegaMultqNew_20[7:0]) );
597 
 
598 
 
599 
   //------------------------------------------------------------------------
600 
   // + lambdaMultqNew_0, ..., QA_19
601 
   //- QA22 = qNewReg * lambdaInner
602 
   //- Multipliers
603 
   //------------------------------------------------------------------------
604 
   RsDecodeMult   RsDecodeMult_PMUL0 (.A(qNewReg[7:0]), .B(lambdaInner_0[7:0]), .P(lambdaMultqNew_0[7:0]) );
605 
   RsDecodeMult   RsDecodeMult_PMUL1 (.A(qNewReg[7:0]), .B(lambdaInner_1[7:0]), .P(lambdaMultqNew_1[7:0]) );
606 
   RsDecodeMult   RsDecodeMult_PMUL2 (.A(qNewReg[7:0]), .B(lambdaInner_2[7:0]), .P(lambdaMultqNew_2[7:0]) );
607 
   RsDecodeMult   RsDecodeMult_PMUL3 (.A(qNewReg[7:0]), .B(lambdaInner_3[7:0]), .P(lambdaMultqNew_3[7:0]) );
608 
   RsDecodeMult   RsDecodeMult_PMUL4 (.A(qNewReg[7:0]), .B(lambdaInner_4[7:0]), .P(lambdaMultqNew_4[7:0]) );
609 
   RsDecodeMult   RsDecodeMult_PMUL5 (.A(qNewReg[7:0]), .B(lambdaInner_5[7:0]), .P(lambdaMultqNew_5[7:0]) );
610 
   RsDecodeMult   RsDecodeMult_PMUL6 (.A(qNewReg[7:0]), .B(lambdaInner_6[7:0]), .P(lambdaMultqNew_6[7:0]) );
611 
   RsDecodeMult   RsDecodeMult_PMUL7 (.A(qNewReg[7:0]), .B(lambdaInner_7[7:0]), .P(lambdaMultqNew_7[7:0]) );
612 
   RsDecodeMult   RsDecodeMult_PMUL8 (.A(qNewReg[7:0]), .B(lambdaInner_8[7:0]), .P(lambdaMultqNew_8[7:0]) );
613 
   RsDecodeMult   RsDecodeMult_PMUL9 (.A(qNewReg[7:0]), .B(lambdaInner_9[7:0]), .P(lambdaMultqNew_9[7:0]) );
614 
   RsDecodeMult   RsDecodeMult_PMUL10 (.A(qNewReg[7:0]), .B(lambdaInner_10[7:0]), .P(lambdaMultqNew_10[7:0]) );
615 
   RsDecodeMult   RsDecodeMult_PMUL11 (.A(qNewReg[7:0]), .B(lambdaInner_11[7:0]), .P(lambdaMultqNew_11[7:0]) );
616 
   RsDecodeMult   RsDecodeMult_PMUL12 (.A(qNewReg[7:0]), .B(lambdaInner_12[7:0]), .P(lambdaMultqNew_12[7:0]) );
617 
   RsDecodeMult   RsDecodeMult_PMUL13 (.A(qNewReg[7:0]), .B(lambdaInner_13[7:0]), .P(lambdaMultqNew_13[7:0]) );
618 
   RsDecodeMult   RsDecodeMult_PMUL14 (.A(qNewReg[7:0]), .B(lambdaInner_14[7:0]), .P(lambdaMultqNew_14[7:0]) );
619 
   RsDecodeMult   RsDecodeMult_PMUL15 (.A(qNewReg[7:0]), .B(lambdaInner_15[7:0]), .P(lambdaMultqNew_15[7:0]) );
620 
   RsDecodeMult   RsDecodeMult_PMUL16 (.A(qNewReg[7:0]), .B(lambdaInner_16[7:0]), .P(lambdaMultqNew_16[7:0]) );
621 
   RsDecodeMult   RsDecodeMult_PMUL17 (.A(qNewReg[7:0]), .B(lambdaInner_17[7:0]), .P(lambdaMultqNew_17[7:0]) );
622 
   RsDecodeMult   RsDecodeMult_PMUL18 (.A(qNewReg[7:0]), .B(lambdaInner_18[7:0]), .P(lambdaMultqNew_18[7:0]) );
623 
   RsDecodeMult   RsDecodeMult_PMUL19 (.A(qNewReg[7:0]), .B(lambdaInner_19[7:0]), .P(lambdaMultqNew_19[7:0]) );
624 
   RsDecodeMult   RsDecodeMult_PMUL20 (.A(qNewReg[7:0]), .B(lambdaInner_20[7:0]), .P(lambdaMultqNew_20[7:0]) );
625 
   RsDecodeMult   RsDecodeMult_PMUL21 (.A(qNewReg[7:0]), .B(lambdaInner_21[7:0]), .P(lambdaMultqNew_21[7:0]) );
626 
 
627 
 
628 
   //------------------------------------------------------------------------
629 
   // + omegaBkp_0, ..., omegaBkp_19
630 
   //- Registers
631 
   //------------------------------------------------------------------------
632 
      always @(posedge CLK or negedge RESET) begin
633 
         if (~RESET) begin
634 
            omegaBkp_0 [7:0]   <= 8'd0;
635 
            omegaBkp_1 [7:0]   <= 8'd0;
636 
            omegaBkp_2 [7:0]   <= 8'd0;
637 
            omegaBkp_3 [7:0]   <= 8'd0;
638 
            omegaBkp_4 [7:0]   <= 8'd0;
639 
            omegaBkp_5 [7:0]   <= 8'd0;
640 
            omegaBkp_6 [7:0]   <= 8'd0;
641 
            omegaBkp_7 [7:0]   <= 8'd0;
642 
            omegaBkp_8 [7:0]   <= 8'd0;
643 
            omegaBkp_9 [7:0]   <= 8'd0;
644 
            omegaBkp_10 [7:0]  <= 8'd0;
645 
            omegaBkp_11 [7:0]  <= 8'd0;
646 
            omegaBkp_12 [7:0]  <= 8'd0;
647 
            omegaBkp_13 [7:0]  <= 8'd0;
648 
            omegaBkp_14 [7:0]  <= 8'd0;
649 
            omegaBkp_15 [7:0]  <= 8'd0;
650 
            omegaBkp_16 [7:0]  <= 8'd0;
651 
            omegaBkp_17 [7:0]  <= 8'd0;
652 
            omegaBkp_18 [7:0]  <= 8'd0;
653 
            omegaBkp_19 [7:0]  <= 8'd0;
654 
            omegaBkp_20 [7:0]  <= 8'd0;
655 
            omegaBkp_21 [7:0]  <= 8'd0;
656 
         end
657 
         else if (enable_E == 1'b1) begin
658 
            if (sync == 1'b1) begin
659 
                omegaBkp_0 [7:0]   <= 8'd0;
660 
                omegaBkp_1 [7:0]   <= 8'd0;
661 
                omegaBkp_2 [7:0]   <= 8'd0;
662 
                omegaBkp_3 [7:0]   <= 8'd0;
663 
                omegaBkp_4 [7:0]   <= 8'd0;
664 
                omegaBkp_5 [7:0]   <= 8'd0;
665 
                omegaBkp_6 [7:0]   <= 8'd0;
666 
                omegaBkp_7 [7:0]   <= 8'd0;
667 
                omegaBkp_8 [7:0]   <= 8'd0;
668 
                omegaBkp_9 [7:0]   <= 8'd0;
669 
                omegaBkp_10 [7:0]  <= 8'd0;
670 
                omegaBkp_11 [7:0]  <= 8'd0;
671 
                omegaBkp_12 [7:0]  <= 8'd0;
672 
                omegaBkp_13 [7:0]  <= 8'd0;
673 
                omegaBkp_14 [7:0]  <= 8'd0;
674 
                omegaBkp_15 [7:0]  <= 8'd0;
675 
                omegaBkp_16 [7:0]  <= 8'd0;
676 
                omegaBkp_17 [7:0]  <= 8'd0;
677 
                omegaBkp_18 [7:0]  <= 8'd0;
678 
                omegaBkp_19 [7:0]  <= 8'd0;
679 
                omegaBkp_20 [7:0]  <= 8'd0;
680 
                omegaBkp_21[7:0]   <= 8'd1;
681 
            end
682 
            else if (phase[1:0] == 2'b00) begin
683 
               if ((skip== 1'b0) && (offset == 5'd0)) begin
684 
                  omegaBkp_0 [7:0]   <= omegaInner_0[7:0];
685 
                  omegaBkp_1 [7:0]   <= omegaInner_1[7:0];
686 
                  omegaBkp_2 [7:0]   <= omegaInner_2[7:0];
687 
                  omegaBkp_3 [7:0]   <= omegaInner_3[7:0];
688 
                  omegaBkp_4 [7:0]   <= omegaInner_4[7:0];
689 
                  omegaBkp_5 [7:0]   <= omegaInner_5[7:0];
690 
                  omegaBkp_6 [7:0]   <= omegaInner_6[7:0];
691 
                  omegaBkp_7 [7:0]   <= omegaInner_7[7:0];
692 
                  omegaBkp_8 [7:0]   <= omegaInner_8[7:0];
693 
                  omegaBkp_9 [7:0]   <= omegaInner_9[7:0];
694 
                  omegaBkp_10 [7:0]  <= omegaInner_10[7:0];
695 
                  omegaBkp_11 [7:0]  <= omegaInner_11[7:0];
696 
                  omegaBkp_12 [7:0]  <= omegaInner_12[7:0];
697 
                  omegaBkp_13 [7:0]  <= omegaInner_13[7:0];
698 
                  omegaBkp_14 [7:0]  <= omegaInner_14[7:0];
699 
                  omegaBkp_15 [7:0]  <= omegaInner_15[7:0];
700 
                  omegaBkp_16 [7:0]  <= omegaInner_16[7:0];
701 
                  omegaBkp_17 [7:0]  <= omegaInner_17[7:0];
702 
                  omegaBkp_18 [7:0]  <= omegaInner_18[7:0];
703 
                  omegaBkp_19 [7:0]  <= omegaInner_19[7:0];
704 
                  omegaBkp_20 [7:0]  <= omegaInner_20[7:0];
705 
                  omegaBkp_21 [7:0]  <= omegaInner_21[7:0];
706 
               end
707 
               else if (skip== 1'b0) begin
708 
                  omegaBkp_0 [7:0]   <= 8'd0;
709 
                  omegaBkp_1 [7:0]   <= omegaMultqNew_0[7:0] ^ omegaBkp_0[7:0];
710 
                  omegaBkp_2 [7:0]   <= omegaMultqNew_1[7:0] ^ omegaBkp_1[7:0];
711 
                  omegaBkp_3 [7:0]   <= omegaMultqNew_2[7:0] ^ omegaBkp_2[7:0];
712 
                  omegaBkp_4 [7:0]   <= omegaMultqNew_3[7:0] ^ omegaBkp_3[7:0];
713 
                  omegaBkp_5 [7:0]   <= omegaMultqNew_4[7:0] ^ omegaBkp_4[7:0];
714 
                  omegaBkp_6 [7:0]   <= omegaMultqNew_5[7:0] ^ omegaBkp_5[7:0];
715 
                  omegaBkp_7 [7:0]   <= omegaMultqNew_6[7:0] ^ omegaBkp_6[7:0];
716 
                  omegaBkp_8 [7:0]   <= omegaMultqNew_7[7:0] ^ omegaBkp_7[7:0];
717 
                  omegaBkp_9 [7:0]   <= omegaMultqNew_8[7:0] ^ omegaBkp_8[7:0];
718 
                  omegaBkp_10 [7:0]  <= omegaMultqNew_9[7:0] ^ omegaBkp_9[7:0];
719 
                  omegaBkp_11 [7:0]  <= omegaMultqNew_10[7:0] ^ omegaBkp_10[7:0];
720 
                  omegaBkp_12 [7:0]  <= omegaMultqNew_11[7:0] ^ omegaBkp_11[7:0];
721 
                  omegaBkp_13 [7:0]  <= omegaMultqNew_12[7:0] ^ omegaBkp_12[7:0];
722 
                  omegaBkp_14 [7:0]  <= omegaMultqNew_13[7:0] ^ omegaBkp_13[7:0];
723 
                  omegaBkp_15 [7:0]  <= omegaMultqNew_14[7:0] ^ omegaBkp_14[7:0];
724 
                  omegaBkp_16 [7:0]  <= omegaMultqNew_15[7:0] ^ omegaBkp_15[7:0];
725 
                  omegaBkp_17 [7:0]  <= omegaMultqNew_16[7:0] ^ omegaBkp_16[7:0];
726 
                  omegaBkp_18 [7:0]  <= omegaMultqNew_17[7:0] ^ omegaBkp_17[7:0];
727 
                  omegaBkp_19 [7:0]  <= omegaMultqNew_18[7:0] ^ omegaBkp_18[7:0];
728 
                  omegaBkp_20 [7:0]  <= omegaMultqNew_19[7:0] ^ omegaBkp_19[7:0];
729 
                  omegaBkp_21 [7:0]  <= omegaMultqNew_20[7:0] ^ omegaBkp_20[7:0];
730 
               end
731 
            end
732 
         end
733 
      end
734 
 
735 
 
736 
   //------------------------------------------------------------------
737 
   // +omegaInner
738 
   //------------------------------------------------------------------
739 
   always @(posedge CLK or negedge RESET) begin
740 
      if (~RESET) begin
741 
         omegaInner_0 [7:0]  <= 8'd0;
742 
         omegaInner_1 [7:0]  <= 8'd0;
743 
         omegaInner_2 [7:0]  <= 8'd0;
744 
         omegaInner_3 [7:0]  <= 8'd0;
745 
         omegaInner_4 [7:0]  <= 8'd0;
746 
         omegaInner_5 [7:0]  <= 8'd0;
747 
         omegaInner_6 [7:0]  <= 8'd0;
748 
         omegaInner_7 [7:0]  <= 8'd0;
749 
         omegaInner_8 [7:0]  <= 8'd0;
750 
         omegaInner_9 [7:0]  <= 8'd0;
751 
         omegaInner_10 [7:0] <= 8'd0;
752 
         omegaInner_11 [7:0] <= 8'd0;
753 
         omegaInner_12 [7:0] <= 8'd0;
754 
         omegaInner_13 [7:0] <= 8'd0;
755 
         omegaInner_14 [7:0] <= 8'd0;
756 
         omegaInner_15 [7:0] <= 8'd0;
757 
         omegaInner_16 [7:0] <= 8'd0;
758 
         omegaInner_17 [7:0] <= 8'd0;
759 
         omegaInner_18 [7:0] <= 8'd0;
760 
         omegaInner_19 [7:0] <= 8'd0;
761 
         omegaInner_20 [7:0] <= 8'd0;
762 
         omegaInner_21 [7:0] <= 8'd0;
763 
      end
764 
      else if (enable_E == 1'b1) begin
765 
         if (sync == 1'b1) begin
766 
            omegaInner_0 [7:0]  <= syndrome_0[7:0];
767 
            omegaInner_1 [7:0]  <= syndrome_1[7:0];
768 
            omegaInner_2 [7:0]  <= syndrome_2[7:0];
769 
            omegaInner_3 [7:0]  <= syndrome_3[7:0];
770 
            omegaInner_4 [7:0]  <= syndrome_4[7:0];
771 
            omegaInner_5 [7:0]  <= syndrome_5[7:0];
772 
            omegaInner_6 [7:0]  <= syndrome_6[7:0];
773 
            omegaInner_7 [7:0]  <= syndrome_7[7:0];
774 
            omegaInner_8 [7:0]  <= syndrome_8[7:0];
775 
            omegaInner_9 [7:0]  <= syndrome_9[7:0];
776 
            omegaInner_10 [7:0] <= syndrome_10[7:0];
777 
            omegaInner_11 [7:0] <= syndrome_11[7:0];
778 
            omegaInner_12 [7:0] <= syndrome_12[7:0];
779 
            omegaInner_13 [7:0] <= syndrome_13[7:0];
780 
            omegaInner_14 [7:0] <= syndrome_14[7:0];
781 
            omegaInner_15 [7:0] <= syndrome_15[7:0];
782 
            omegaInner_16 [7:0] <= syndrome_16[7:0];
783 
            omegaInner_17 [7:0] <= syndrome_17[7:0];
784 
            omegaInner_18 [7:0] <= syndrome_18[7:0];
785 
            omegaInner_19 [7:0] <= syndrome_19[7:0];
786 
            omegaInner_20 [7:0] <= syndrome_20[7:0];
787 
            omegaInner_21 [7:0] <= syndrome_21[7:0];
788 
         end
789 
         else if (phase == 2'b00) begin
790 
            if ((skip == 1'b0) && (offset == 5'd0)) begin
791 
               omegaInner_0 [7:0]  <= 8'd0;
792 
               omegaInner_1 [7:0]  <= omegaMultqNew_0 [7:0] ^ omegaBkp_0 [7:0];
793 
               omegaInner_2 [7:0]  <= omegaMultqNew_1 [7:0] ^ omegaBkp_1 [7:0];
794 
               omegaInner_3 [7:0]  <= omegaMultqNew_2 [7:0] ^ omegaBkp_2 [7:0];
795 
               omegaInner_4 [7:0]  <= omegaMultqNew_3 [7:0] ^ omegaBkp_3 [7:0];
796 
               omegaInner_5 [7:0]  <= omegaMultqNew_4 [7:0] ^ omegaBkp_4 [7:0];
797 
               omegaInner_6 [7:0]  <= omegaMultqNew_5 [7:0] ^ omegaBkp_5 [7:0];
798 
               omegaInner_7 [7:0]  <= omegaMultqNew_6 [7:0] ^ omegaBkp_6 [7:0];
799 
               omegaInner_8 [7:0]  <= omegaMultqNew_7 [7:0] ^ omegaBkp_7 [7:0];
800 
               omegaInner_9 [7:0]  <= omegaMultqNew_8 [7:0] ^ omegaBkp_8 [7:0];
801 
               omegaInner_10 [7:0] <= omegaMultqNew_9 [7:0] ^ omegaBkp_9 [7:0];
802 
               omegaInner_11 [7:0] <= omegaMultqNew_10 [7:0] ^ omegaBkp_10 [7:0];
803 
               omegaInner_12 [7:0] <= omegaMultqNew_11 [7:0] ^ omegaBkp_11 [7:0];
804 
               omegaInner_13 [7:0] <= omegaMultqNew_12 [7:0] ^ omegaBkp_12 [7:0];
805 
               omegaInner_14 [7:0] <= omegaMultqNew_13 [7:0] ^ omegaBkp_13 [7:0];
806 
               omegaInner_15 [7:0] <= omegaMultqNew_14 [7:0] ^ omegaBkp_14 [7:0];
807 
               omegaInner_16 [7:0] <= omegaMultqNew_15 [7:0] ^ omegaBkp_15 [7:0];
808 
               omegaInner_17 [7:0] <= omegaMultqNew_16 [7:0] ^ omegaBkp_16 [7:0];
809 
               omegaInner_18 [7:0] <= omegaMultqNew_17 [7:0] ^ omegaBkp_17 [7:0];
810 
               omegaInner_19 [7:0] <= omegaMultqNew_18 [7:0] ^ omegaBkp_18 [7:0];
811 
               omegaInner_20 [7:0] <= omegaMultqNew_19 [7:0] ^ omegaBkp_19 [7:0];
812 
               omegaInner_21 [7:0] <= omegaMultqNew_20 [7:0] ^ omegaBkp_20 [7:0];
813 
            end
814 
            else if (skip == 1'b1) begin
815 
               omegaInner_0 [7:0]  <= 8'd0;
816 
               omegaInner_1 [7:0]  <= omegaInner_0 [7:0];
817 
               omegaInner_2 [7:0]  <= omegaInner_1 [7:0];
818 
               omegaInner_3 [7:0]  <= omegaInner_2 [7:0];
819 
               omegaInner_4 [7:0]  <= omegaInner_3 [7:0];
820 
               omegaInner_5 [7:0]  <= omegaInner_4 [7:0];
821 
               omegaInner_6 [7:0]  <= omegaInner_5 [7:0];
822 
               omegaInner_7 [7:0]  <= omegaInner_6 [7:0];
823 
               omegaInner_8 [7:0]  <= omegaInner_7 [7:0];
824 
               omegaInner_9 [7:0]  <= omegaInner_8 [7:0];
825 
               omegaInner_10 [7:0] <= omegaInner_9 [7:0];
826 
               omegaInner_11 [7:0] <= omegaInner_10 [7:0];
827 
               omegaInner_12 [7:0] <= omegaInner_11 [7:0];
828 
               omegaInner_13 [7:0] <= omegaInner_12 [7:0];
829 
               omegaInner_14 [7:0] <= omegaInner_13 [7:0];
830 
               omegaInner_15 [7:0] <= omegaInner_14 [7:0];
831 
               omegaInner_16 [7:0] <= omegaInner_15 [7:0];
832 
               omegaInner_17 [7:0] <= omegaInner_16 [7:0];
833 
               omegaInner_18 [7:0] <= omegaInner_17 [7:0];
834 
               omegaInner_19 [7:0] <= omegaInner_18 [7:0];
835 
               omegaInner_20 [7:0] <= omegaInner_19 [7:0];
836 
               omegaInner_21 [7:0] <= omegaInner_20 [7:0];
837 
            end
838 
         end
839 
      end
840 
   end
841 
 
842 
 
843 
   //------------------------------------------------------------------
844 
   // + lambdaBkp_0,..,lambdaBkp_21
845 
   //------------------------------------------------------------------
846 
   always @(posedge CLK or negedge RESET) begin
847 
      if (~RESET) begin
848 
         lambdaBkp_0 [7:0]   <= 8'd0;
849 
         lambdaBkp_1 [7:0]   <= 8'd0;
850 
         lambdaBkp_2 [7:0]   <= 8'd0;
851 
         lambdaBkp_3 [7:0]   <= 8'd0;
852 
         lambdaBkp_4 [7:0]   <= 8'd0;
853 
         lambdaBkp_5 [7:0]   <= 8'd0;
854 
         lambdaBkp_6 [7:0]   <= 8'd0;
855 
         lambdaBkp_7 [7:0]   <= 8'd0;
856 
         lambdaBkp_8 [7:0]   <= 8'd0;
857 
         lambdaBkp_9 [7:0]   <= 8'd0;
858 
         lambdaBkp_10 [7:0]  <= 8'd0;
859 
         lambdaBkp_11 [7:0]  <= 8'd0;
860 
         lambdaBkp_12 [7:0]  <= 8'd0;
861 
         lambdaBkp_13 [7:0]  <= 8'd0;
862 
         lambdaBkp_14 [7:0]  <= 8'd0;
863 
         lambdaBkp_15 [7:0]  <= 8'd0;
864 
         lambdaBkp_16 [7:0]  <= 8'd0;
865 
         lambdaBkp_17 [7:0]  <= 8'd0;
866 
         lambdaBkp_18 [7:0]  <= 8'd0;
867 
         lambdaBkp_19 [7:0]  <= 8'd0;
868 
         lambdaBkp_20 [7:0]  <= 8'd0;
869 
         lambdaBkp_21 [7:0]  <= 8'd0;
870 
      end
871 
      else if (enable_E == 1'b1) begin
872 
         if (sync == 1'b1) begin
873 
            lambdaBkp_0 [7:0]  <= 8'd0;
874 
            lambdaBkp_1 [7:0]  <= 8'd0;
875 
            lambdaBkp_2 [7:0]  <= 8'd0;
876 
            lambdaBkp_3 [7:0]  <= 8'd0;
877 
            lambdaBkp_4 [7:0]  <= 8'd0;
878 
            lambdaBkp_5 [7:0]  <= 8'd0;
879 
            lambdaBkp_6 [7:0]  <= 8'd0;
880 
            lambdaBkp_7 [7:0]  <= 8'd0;
881 
            lambdaBkp_8 [7:0]  <= 8'd0;
882 
            lambdaBkp_9 [7:0]  <= 8'd0;
883 
            lambdaBkp_10 [7:0] <= 8'd0;
884 
            lambdaBkp_11 [7:0] <= 8'd0;
885 
            lambdaBkp_12 [7:0] <= 8'd0;
886 
            lambdaBkp_13 [7:0] <= 8'd0;
887 
            lambdaBkp_14 [7:0] <= 8'd0;
888 
            lambdaBkp_15 [7:0] <= 8'd0;
889 
            lambdaBkp_16 [7:0] <= 8'd0;
890 
            lambdaBkp_17 [7:0] <= 8'd0;
891 
            lambdaBkp_18 [7:0] <= 8'd0;
892 
            lambdaBkp_19 [7:0] <= 8'd0;
893 
            lambdaBkp_20 [7:0] <= 8'd0;
894 
            lambdaBkp_21 [7:0] <= 8'd0;
895 
         end
896 
         else if ((phase == 2'b00) && (skip == 1'b0) && (offset == 5'd0)) begin
897 
            lambdaBkp_0 [7:0]  <= lambdaInner_0[7:0];
898 
            lambdaBkp_1 [7:0]  <= lambdaInner_1[7:0];
899 
            lambdaBkp_2 [7:0]  <= lambdaInner_2[7:0];
900 
            lambdaBkp_3 [7:0]  <= lambdaInner_3[7:0];
901 
            lambdaBkp_4 [7:0]  <= lambdaInner_4[7:0];
902 
            lambdaBkp_5 [7:0]  <= lambdaInner_5[7:0];
903 
            lambdaBkp_6 [7:0]  <= lambdaInner_6[7:0];
904 
            lambdaBkp_7 [7:0]  <= lambdaInner_7[7:0];
905 
            lambdaBkp_8 [7:0]  <= lambdaInner_8[7:0];
906 
            lambdaBkp_9 [7:0]  <= lambdaInner_9[7:0];
907 
            lambdaBkp_10 [7:0] <= lambdaInner_10[7:0];
908 
            lambdaBkp_11 [7:0] <= lambdaInner_11[7:0];
909 
            lambdaBkp_12 [7:0] <= lambdaInner_12[7:0];
910 
            lambdaBkp_13 [7:0] <= lambdaInner_13[7:0];
911 
            lambdaBkp_14 [7:0] <= lambdaInner_14[7:0];
912 
            lambdaBkp_15 [7:0] <= lambdaInner_15[7:0];
913 
            lambdaBkp_16 [7:0] <= lambdaInner_16[7:0];
914 
            lambdaBkp_17 [7:0] <= lambdaInner_17[7:0];
915 
            lambdaBkp_18 [7:0] <= lambdaInner_18[7:0];
916 
            lambdaBkp_19 [7:0] <= lambdaInner_19[7:0];
917 
            lambdaBkp_20 [7:0] <= lambdaInner_20[7:0];
918 
            lambdaBkp_21 [7:0] <= lambdaInner_21[7:0];
919 
         end
920 
      end
921 
   end
922 
 
923 
 
924 
   //------------------------------------------------------------------
925 
   // + lambdaInner_0, lambdaInner_21
926 
   //------------------------------------------------------------------
927 
   always @(posedge CLK or negedge RESET) begin
928 
      if (~RESET) begin
929 
         lambdaInner_0 [7:0]  <= 8'd0;
930 
         lambdaInner_1 [7:0]  <= 8'd0;
931 
         lambdaInner_2 [7:0]  <= 8'd0;
932 
         lambdaInner_3 [7:0]  <= 8'd0;
933 
         lambdaInner_4 [7:0]  <= 8'd0;
934 
         lambdaInner_5 [7:0]  <= 8'd0;
935 
         lambdaInner_6 [7:0]  <= 8'd0;
936 
         lambdaInner_7 [7:0]  <= 8'd0;
937 
         lambdaInner_8 [7:0]  <= 8'd0;
938 
         lambdaInner_9 [7:0]  <= 8'd0;
939 
         lambdaInner_10 [7:0] <= 8'd0;
940 
         lambdaInner_11 [7:0] <= 8'd0;
941 
         lambdaInner_12 [7:0] <= 8'd0;
942 
         lambdaInner_13 [7:0] <= 8'd0;
943 
         lambdaInner_14 [7:0] <= 8'd0;
944 
         lambdaInner_15 [7:0] <= 8'd0;
945 
         lambdaInner_16 [7:0] <= 8'd0;
946 
         lambdaInner_17 [7:0] <= 8'd0;
947 
         lambdaInner_18 [7:0] <= 8'd0;
948 
         lambdaInner_19 [7:0] <= 8'd0;
949 
         lambdaInner_20 [7:0] <= 8'd0;
950 
         lambdaInner_21 [7:0] <= 8'd0;
951 
      end
952 
      else if (enable_E == 1'b1) begin
953 
         if (sync == 1'b1) begin
954 
            lambdaInner_0 [7:0]  <= 8'd1;
955 
            lambdaInner_1 [7:0]  <= 8'd0;
956 
            lambdaInner_2 [7:0]  <= 8'd0;
957 
            lambdaInner_3 [7:0]  <= 8'd0;
958 
            lambdaInner_4 [7:0]  <= 8'd0;
959 
            lambdaInner_5 [7:0]  <= 8'd0;
960 
            lambdaInner_6 [7:0]  <= 8'd0;
961 
            lambdaInner_7 [7:0]  <= 8'd0;
962 
            lambdaInner_8 [7:0]  <= 8'd0;
963 
            lambdaInner_9 [7:0]  <= 8'd0;
964 
            lambdaInner_10 [7:0] <= 8'd0;
965 
            lambdaInner_11 [7:0] <= 8'd0;
966 
            lambdaInner_12 [7:0] <= 8'd0;
967 
            lambdaInner_13 [7:0] <= 8'd0;
968 
            lambdaInner_14 [7:0] <= 8'd0;
969 
            lambdaInner_15 [7:0] <= 8'd0;
970 
            lambdaInner_16 [7:0] <= 8'd0;
971 
            lambdaInner_17 [7:0] <= 8'd0;
972 
            lambdaInner_18 [7:0] <= 8'd0;
973 
            lambdaInner_19 [7:0] <= 8'd0;
974 
            lambdaInner_20 [7:0] <= 8'd0;
975 
            lambdaInner_21 [7:0] <= 8'd0;
976 
         end
977 
         else if ((phase[1:0] == 2'b00) && (skip == 1'b0) && (offset== 5'd0)) begin
978 
            lambdaInner_0 [7:0]  <= lambdaBkp_0 [7:0] ^ lambdaMultqNew_0 [7:0];
979 
            lambdaInner_1 [7:0]  <= lambdaBkp_1 [7:0] ^ lambdaMultqNew_1 [7:0] ^ lambdaXorReg_0 [7:0];
980 
            lambdaInner_2 [7:0]  <= lambdaBkp_2 [7:0] ^ lambdaMultqNew_2 [7:0] ^ lambdaXorReg_1 [7:0];
981 
            lambdaInner_3 [7:0]  <= lambdaBkp_3 [7:0] ^ lambdaMultqNew_3 [7:0] ^ lambdaXorReg_2 [7:0];
982 
            lambdaInner_4 [7:0]  <= lambdaBkp_4 [7:0] ^ lambdaMultqNew_4 [7:0] ^ lambdaXorReg_3 [7:0];
983 
            lambdaInner_5 [7:0]  <= lambdaBkp_5 [7:0] ^ lambdaMultqNew_5 [7:0] ^ lambdaXorReg_4 [7:0];
984 
            lambdaInner_6 [7:0]  <= lambdaBkp_6 [7:0] ^ lambdaMultqNew_6 [7:0] ^ lambdaXorReg_5 [7:0];
985 
            lambdaInner_7 [7:0]  <= lambdaBkp_7 [7:0] ^ lambdaMultqNew_7 [7:0] ^ lambdaXorReg_6 [7:0];
986 
            lambdaInner_8 [7:0]  <= lambdaBkp_8 [7:0] ^ lambdaMultqNew_8 [7:0] ^ lambdaXorReg_7 [7:0];
987 
            lambdaInner_9 [7:0]  <= lambdaBkp_9 [7:0] ^ lambdaMultqNew_9 [7:0] ^ lambdaXorReg_8 [7:0];
988 
            lambdaInner_10 [7:0] <= lambdaBkp_10 [7:0] ^ lambdaMultqNew_10 [7:0] ^ lambdaXorReg_9 [7:0];
989 
            lambdaInner_11 [7:0] <= lambdaBkp_11 [7:0] ^ lambdaMultqNew_11 [7:0] ^ lambdaXorReg_10 [7:0];
990 
            lambdaInner_12 [7:0] <= lambdaBkp_12 [7:0] ^ lambdaMultqNew_12 [7:0] ^ lambdaXorReg_11 [7:0];
991 
            lambdaInner_13 [7:0] <= lambdaBkp_13 [7:0] ^ lambdaMultqNew_13 [7:0] ^ lambdaXorReg_12 [7:0];
992 
            lambdaInner_14 [7:0] <= lambdaBkp_14 [7:0] ^ lambdaMultqNew_14 [7:0] ^ lambdaXorReg_13 [7:0];
993 
            lambdaInner_15 [7:0] <= lambdaBkp_15 [7:0] ^ lambdaMultqNew_15 [7:0] ^ lambdaXorReg_14 [7:0];
994 
            lambdaInner_16 [7:0] <= lambdaBkp_16 [7:0] ^ lambdaMultqNew_16 [7:0] ^ lambdaXorReg_15 [7:0];
995 
            lambdaInner_17 [7:0] <= lambdaBkp_17 [7:0] ^ lambdaMultqNew_17 [7:0] ^ lambdaXorReg_16 [7:0];
996 
            lambdaInner_18 [7:0] <= lambdaBkp_18 [7:0] ^ lambdaMultqNew_18 [7:0] ^ lambdaXorReg_17 [7:0];
997 
            lambdaInner_19 [7:0] <= lambdaBkp_19 [7:0] ^ lambdaMultqNew_19 [7:0] ^ lambdaXorReg_18 [7:0];
998 
            lambdaInner_20 [7:0] <= lambdaBkp_20 [7:0] ^ lambdaMultqNew_20 [7:0] ^ lambdaXorReg_19 [7:0];
999 
            lambdaInner_21 [7:0] <= lambdaBkp_21 [7:0] ^ lambdaMultqNew_21 [7:0] ^ lambdaXorReg_20 [7:0];
1000 
         end
1001 
      end
1002 
   end
1003 
 
1004 
 
1005 
   //------------------------------------------------------------------
1006 
   // + lambdaXorReg_0,..., lambdaXorReg_22
1007 
   //------------------------------------------------------------------
1008 
   always @(posedge CLK or negedge RESET) begin
1009 
      if (~RESET) begin
1010 
         lambdaXorReg_0 [7:0]  <= 8'd0;
1011 
         lambdaXorReg_1 [7:0]  <= 8'd0;
1012 
         lambdaXorReg_2 [7:0]  <= 8'd0;
1013 
         lambdaXorReg_3 [7:0]  <= 8'd0;
1014 
         lambdaXorReg_4 [7:0]  <= 8'd0;
1015 
         lambdaXorReg_5 [7:0]  <= 8'd0;
1016 
         lambdaXorReg_6 [7:0]  <= 8'd0;
1017 
         lambdaXorReg_7 [7:0]  <= 8'd0;
1018 
         lambdaXorReg_8 [7:0]  <= 8'd0;
1019 
         lambdaXorReg_9 [7:0]  <= 8'd0;
1020 
         lambdaXorReg_10 [7:0] <= 8'd0;
1021 
         lambdaXorReg_11 [7:0] <= 8'd0;
1022 
         lambdaXorReg_12 [7:0] <= 8'd0;
1023 
         lambdaXorReg_13 [7:0] <= 8'd0;
1024 
         lambdaXorReg_14 [7:0] <= 8'd0;
1025 
         lambdaXorReg_15 [7:0] <= 8'd0;
1026 
         lambdaXorReg_16 [7:0] <= 8'd0;
1027 
         lambdaXorReg_17 [7:0] <= 8'd0;
1028 
         lambdaXorReg_18 [7:0] <= 8'd0;
1029 
         lambdaXorReg_19 [7:0] <= 8'd0;
1030 
         lambdaXorReg_20 [7:0] <= 8'd0;
1031 
      end
1032 
      else if (enable_E == 1'b1) begin
1033 
         if (sync == 1'b1) begin
1034 
            lambdaXorReg_0 [7:0]  <= 8'd0;
1035 
            lambdaXorReg_1 [7:0]  <= 8'd0;
1036 
            lambdaXorReg_2 [7:0]  <= 8'd0;
1037 
            lambdaXorReg_3 [7:0]  <= 8'd0;
1038 
            lambdaXorReg_4 [7:0]  <= 8'd0;
1039 
            lambdaXorReg_5 [7:0]  <= 8'd0;
1040 
            lambdaXorReg_6 [7:0]  <= 8'd0;
1041 
            lambdaXorReg_7 [7:0]  <= 8'd0;
1042 
            lambdaXorReg_8 [7:0]  <= 8'd0;
1043 
            lambdaXorReg_9 [7:0]  <= 8'd0;
1044 
            lambdaXorReg_10 [7:0] <= 8'd0;
1045 
            lambdaXorReg_11 [7:0] <= 8'd0;
1046 
            lambdaXorReg_12 [7:0] <= 8'd0;
1047 
            lambdaXorReg_13 [7:0] <= 8'd0;
1048 
            lambdaXorReg_14 [7:0] <= 8'd0;
1049 
            lambdaXorReg_15 [7:0] <= 8'd0;
1050 
            lambdaXorReg_16 [7:0] <= 8'd0;
1051 
            lambdaXorReg_17 [7:0] <= 8'd0;
1052 
            lambdaXorReg_18 [7:0] <= 8'd0;
1053 
            lambdaXorReg_19 [7:0] <= 8'd0;
1054 
            lambdaXorReg_20 [7:0] <= 8'd0;
1055 
         end
1056 
         else if (phase == 2'b00) begin
1057 
            if ((skip == 1'b0) && (offset == 5'd0)) begin
1058 
               lambdaXorReg_0 [7:0]  <= 8'd0;
1059 
               lambdaXorReg_1 [7:0]  <= 8'd0;
1060 
               lambdaXorReg_2 [7:0]  <= 8'd0;
1061 
               lambdaXorReg_3 [7:0]  <= 8'd0;
1062 
               lambdaXorReg_4 [7:0]  <= 8'd0;
1063 
               lambdaXorReg_5 [7:0]  <= 8'd0;
1064 
               lambdaXorReg_6 [7:0]  <= 8'd0;
1065 
               lambdaXorReg_7 [7:0]  <= 8'd0;
1066 
               lambdaXorReg_8 [7:0]  <= 8'd0;
1067 
               lambdaXorReg_9 [7:0]  <= 8'd0;
1068 
               lambdaXorReg_10 [7:0] <= 8'd0;
1069 
               lambdaXorReg_11 [7:0] <= 8'd0;
1070 
               lambdaXorReg_12 [7:0] <= 8'd0;
1071 
               lambdaXorReg_13 [7:0] <= 8'd0;
1072 
               lambdaXorReg_14 [7:0] <= 8'd0;
1073 
               lambdaXorReg_15 [7:0] <= 8'd0;
1074 
               lambdaXorReg_16 [7:0] <= 8'd0;
1075 
               lambdaXorReg_17 [7:0] <= 8'd0;
1076 
               lambdaXorReg_18 [7:0] <= 8'd0;
1077 
               lambdaXorReg_19 [7:0] <= 8'd0;
1078 
               lambdaXorReg_20 [7:0] <= 8'd0;
1079 
            end
1080 
            else if (skip == 1'b0) begin
1081 
               lambdaXorReg_0 [7:0]  <= lambdaMultqNew_0 [7:0];
1082 
               lambdaXorReg_1 [7:0]  <= lambdaMultqNew_1 [7:0] ^ lambdaXorReg_0[7:0];
1083 
               lambdaXorReg_2 [7:0]  <= lambdaMultqNew_2 [7:0] ^ lambdaXorReg_1[7:0];
1084 
               lambdaXorReg_3 [7:0]  <= lambdaMultqNew_3 [7:0] ^ lambdaXorReg_2[7:0];
1085 
               lambdaXorReg_4 [7:0]  <= lambdaMultqNew_4 [7:0] ^ lambdaXorReg_3[7:0];
1086 
               lambdaXorReg_5 [7:0]  <= lambdaMultqNew_5 [7:0] ^ lambdaXorReg_4[7:0];
1087 
               lambdaXorReg_6 [7:0]  <= lambdaMultqNew_6 [7:0] ^ lambdaXorReg_5[7:0];
1088 
               lambdaXorReg_7 [7:0]  <= lambdaMultqNew_7 [7:0] ^ lambdaXorReg_6[7:0];
1089 
               lambdaXorReg_8 [7:0]  <= lambdaMultqNew_8 [7:0] ^ lambdaXorReg_7[7:0];
1090 
               lambdaXorReg_9 [7:0]  <= lambdaMultqNew_9 [7:0] ^ lambdaXorReg_8[7:0];
1091 
               lambdaXorReg_10 [7:0] <= lambdaMultqNew_10 [7:0] ^ lambdaXorReg_9[7:0];
1092 
               lambdaXorReg_11 [7:0] <= lambdaMultqNew_11 [7:0] ^ lambdaXorReg_10[7:0];
1093 
               lambdaXorReg_12 [7:0] <= lambdaMultqNew_12 [7:0] ^ lambdaXorReg_11[7:0];
1094 
               lambdaXorReg_13 [7:0] <= lambdaMultqNew_13 [7:0] ^ lambdaXorReg_12[7:0];
1095 
               lambdaXorReg_14 [7:0] <= lambdaMultqNew_14 [7:0] ^ lambdaXorReg_13[7:0];
1096 
               lambdaXorReg_15 [7:0] <= lambdaMultqNew_15 [7:0] ^ lambdaXorReg_14[7:0];
1097 
               lambdaXorReg_16 [7:0] <= lambdaMultqNew_16 [7:0] ^ lambdaXorReg_15[7:0];
1098 
               lambdaXorReg_17 [7:0] <= lambdaMultqNew_17 [7:0] ^ lambdaXorReg_16[7:0];
1099 
               lambdaXorReg_18 [7:0] <= lambdaMultqNew_18 [7:0] ^ lambdaXorReg_17[7:0];
1100 
               lambdaXorReg_19 [7:0] <= lambdaMultqNew_19 [7:0] ^ lambdaXorReg_18[7:0];
1101 
               lambdaXorReg_20 [7:0] <= lambdaMultqNew_20 [7:0] ^ lambdaXorReg_19[7:0];
1102 
            end
1103 
         end
1104 
      end
1105 
   end
1106 
 
1107 
 
1108 
   //------------------------------------------------------------------
1109 
   // + offset
1110 
   //------------------------------------------------------------------
1111 
   always @(posedge CLK or negedge RESET) begin
1112 
      if (~RESET) begin
1113 
         offset [4:0] <= 5'd0;
1114 
      end
1115 
      else if (enable_E == 1'b1) begin
1116 
         if (sync == 1'b1) begin
1117 
            offset [4:0] <= 5'd1;
1118 
         end
1119 
         else if (phase [1:0] == 2'b00) begin
1120 
            if ((skip == 1'b0) && (offset[4:0]==5'd0)) begin
1121 
               offset [4:0] <= 5'd1;
1122 
            end
1123 
            else if (skip == 1'b1) begin
1124 
               offset [4:0] <= offset [4:0] + 5'd1;
1125 
            end
1126 
            else begin
1127 
               offset [4:0] <= offset [4:0] - 5'd1;
1128 
            end
1129 
         end
1130 
      end
1131 
   end
1132 
 
1133 
 
1134 
   //------------------------------------------------------------------
1135 
   // + numShiftedReg
1136 
   //------------------------------------------------------------------
1137 
   always @(posedge CLK or negedge RESET) begin
1138 
      if (~RESET) begin
1139 
         numShiftedReg   [4:0] <= 5'd0;
1140 
      end
1141 
      else if (enable_E == 1'b1) begin
1142 
         if (sync == 1'b1) begin
1143 
            numShiftedReg   <= 5'd0;
1144 
         end
1145 
         else if (phase == 2'd0) begin
1146 
            if ((skip == 1'b0) && (offset == 5'd0)) begin
1147 
               numShiftedReg   <= numShiftedReg + 5'd1;
1148 
            end
1149 
            else if (skip == 1'b1) begin
1150 
               numShiftedReg   <= numShiftedReg + 5'd1;
1151 
            end
1152 
         end
1153 
      end
1154 
   end
1155 
 
1156 
 
1157 
   //------------------------------------------------------------------------
1158 
   //- OutputPorts
1159 
   //------------------------------------------------------------------------
1160 
   assign lambda_0 [7:0]  = lambdaInner_0 [7:0];
1161 
   assign lambda_1 [7:0]  = lambdaInner_1 [7:0];
1162 
   assign lambda_2 [7:0]  = lambdaInner_2 [7:0];
1163 
   assign lambda_3 [7:0]  = lambdaInner_3 [7:0];
1164 
   assign lambda_4 [7:0]  = lambdaInner_4 [7:0];
1165 
   assign lambda_5 [7:0]  = lambdaInner_5 [7:0];
1166 
   assign lambda_6 [7:0]  = lambdaInner_6 [7:0];
1167 
   assign lambda_7 [7:0]  = lambdaInner_7 [7:0];
1168 
   assign lambda_8 [7:0]  = lambdaInner_8 [7:0];
1169 
   assign lambda_9 [7:0]  = lambdaInner_9 [7:0];
1170 
   assign lambda_10 [7:0] = lambdaInner_10 [7:0];
1171 
   assign lambda_11 [7:0] = lambdaInner_11 [7:0];
1172 
   assign lambda_12 [7:0] = lambdaInner_12 [7:0];
1173 
   assign lambda_13 [7:0] = lambdaInner_13 [7:0];
1174 
   assign lambda_14 [7:0] = lambdaInner_14 [7:0];
1175 
   assign lambda_15 [7:0] = lambdaInner_15 [7:0];
1176 
   assign lambda_16 [7:0] = lambdaInner_16 [7:0];
1177 
   assign lambda_17 [7:0] = lambdaInner_17 [7:0];
1178 
   assign lambda_18 [7:0] = lambdaInner_18 [7:0];
1179 
   assign lambda_19 [7:0] = lambdaInner_19 [7:0];
1180 
   assign lambda_20 [7:0] = lambdaInner_20 [7:0];
1181 
   assign lambda_21 [7:0] = lambdaInner_21 [7:0];
1182 
 
1183 
   assign omega_0 [7:0]  = omegaInner_0 [7:0];
1184 
   assign omega_1 [7:0]  = omegaInner_1 [7:0];
1185 
   assign omega_2 [7:0]  = omegaInner_2 [7:0];
1186 
   assign omega_3 [7:0]  = omegaInner_3 [7:0];
1187 
   assign omega_4 [7:0]  = omegaInner_4 [7:0];
1188 
   assign omega_5 [7:0]  = omegaInner_5 [7:0];
1189 
   assign omega_6 [7:0]  = omegaInner_6 [7:0];
1190 
   assign omega_7 [7:0]  = omegaInner_7 [7:0];
1191 
   assign omega_8 [7:0]  = omegaInner_8 [7:0];
1192 
   assign omega_9 [7:0]  = omegaInner_9 [7:0];
1193 
   assign omega_10 [7:0] = omegaInner_10 [7:0];
1194 
   assign omega_11 [7:0] = omegaInner_11 [7:0];
1195 
   assign omega_12 [7:0] = omegaInner_12 [7:0];
1196 
   assign omega_13 [7:0] = omegaInner_13 [7:0];
1197 
   assign omega_14 [7:0] = omegaInner_14 [7:0];
1198 
   assign omega_15 [7:0] = omegaInner_15 [7:0];
1199 
   assign omega_16 [7:0] = omegaInner_16 [7:0];
1200 
   assign omega_17 [7:0] = omegaInner_17 [7:0];
1201 
   assign omega_18 [7:0] = omegaInner_18 [7:0];
1202 
   assign omega_19 [7:0] = omegaInner_19 [7:0];
1203 
   assign omega_20 [7:0] = omegaInner_20 [7:0];
1204 
   assign omega_21 [7:0] = omegaInner_21 [7:0];
1205 
   assign numShifted     = numShiftedReg;
1206 
 
1207 
 
1208 
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2026 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.