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//===================================================================
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// Module Name : RsDecodePolymul
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// File Name : RsDecodePolymul.v
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// Function : Rs Decoder polymul calculation Module
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//
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// Revision History:
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// Date By Version Change Description
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//===================================================================
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// 2009/02/03 Gael Sapience 1.0 Original
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//
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//===================================================================
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// (C) COPYRIGHT 2009 SYSTEM LSI CO., Ltd.
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//
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module RsDecodePolymul(
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CLK, // system clock
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RESET, // system reset
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enable, // enable signal
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sync, // sync signal
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syndromeIn_0, // syndrome polynom 0
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syndromeIn_1, // syndrome polynom 1
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syndromeIn_2, // syndrome polynom 2
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syndromeIn_3, // syndrome polynom 3
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syndromeIn_4, // syndrome polynom 4
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syndromeIn_5, // syndrome polynom 5
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syndromeIn_6, // syndrome polynom 6
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syndromeIn_7, // syndrome polynom 7
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syndromeIn_8, // syndrome polynom 8
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syndromeIn_9, // syndrome polynom 9
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syndromeIn_10, // syndrome polynom 10
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syndromeIn_11, // syndrome polynom 11
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syndromeIn_12, // syndrome polynom 12
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syndromeIn_13, // syndrome polynom 13
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syndromeIn_14, // syndrome polynom 14
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syndromeIn_15, // syndrome polynom 15
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syndromeIn_16, // syndrome polynom 16
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syndromeIn_17, // syndrome polynom 17
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syndromeIn_18, // syndrome polynom 18
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syndromeIn_19, // syndrome polynom 19
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syndromeIn_20, // syndrome polynom 20
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syndromeIn_21, // syndrome polynom 21
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epsilon_0, // epsilon polynom 0
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epsilon_1, // epsilon polynom 1
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epsilon_2, // epsilon polynom 2
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epsilon_3, // epsilon polynom 3
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epsilon_4, // epsilon polynom 4
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epsilon_5, // epsilon polynom 5
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epsilon_6, // epsilon polynom 6
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epsilon_7, // epsilon polynom 7
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epsilon_8, // epsilon polynom 8
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epsilon_9, // epsilon polynom 9
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epsilon_10, // epsilon polynom 10
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epsilon_11, // epsilon polynom 11
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epsilon_12, // epsilon polynom 12
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epsilon_13, // epsilon polynom 13
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epsilon_14, // epsilon polynom 14
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epsilon_15, // epsilon polynom 15
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epsilon_16, // epsilon polynom 16
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epsilon_17, // epsilon polynom 17
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epsilon_18, // epsilon polynom 18
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epsilon_19, // epsilon polynom 19
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epsilon_20, // epsilon polynom 20
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epsilon_21, // epsilon polynom 21
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epsilon_22, // epsilon polynom 22
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syndromeOut_0, // modified syndrome polynom 0
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syndromeOut_1, // modified syndrome polynom 1
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syndromeOut_2, // modified syndrome polynom 2
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syndromeOut_3, // modified syndrome polynom 3
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syndromeOut_4, // modified syndrome polynom 4
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syndromeOut_5, // modified syndrome polynom 5
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syndromeOut_6, // modified syndrome polynom 6
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syndromeOut_7, // modified syndrome polynom 7
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syndromeOut_8, // modified syndrome polynom 8
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syndromeOut_9, // modified syndrome polynom 9
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syndromeOut_10, // modified syndrome polynom 10
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syndromeOut_11, // modified syndrome polynom 11
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syndromeOut_12, // modified syndrome polynom 12
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syndromeOut_13, // modified syndrome polynom 13
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syndromeOut_14, // modified syndrome polynom 14
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syndromeOut_15, // modified syndrome polynom 15
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syndromeOut_16, // modified syndrome polynom 16
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syndromeOut_17, // modified syndrome polynom 17
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syndromeOut_18, // modified syndrome polynom 18
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syndromeOut_19, // modified syndrome polynom 19
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syndromeOut_20, // modified syndrome polynom 20
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syndromeOut_21, // modified syndrome polynom 21
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done // done signal
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);
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input CLK; // system clock
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input RESET; // system reset
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input enable; // enable signal
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input sync; // sync signal
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input [7:0] syndromeIn_0; // syndrome polynom 0
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input [7:0] syndromeIn_1; // syndrome polynom 1
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input [7:0] syndromeIn_2; // syndrome polynom 2
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input [7:0] syndromeIn_3; // syndrome polynom 3
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input [7:0] syndromeIn_4; // syndrome polynom 4
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input [7:0] syndromeIn_5; // syndrome polynom 5
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input [7:0] syndromeIn_6; // syndrome polynom 6
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input [7:0] syndromeIn_7; // syndrome polynom 7
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input [7:0] syndromeIn_8; // syndrome polynom 8
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input [7:0] syndromeIn_9; // syndrome polynom 9
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input [7:0] syndromeIn_10; // syndrome polynom 10
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input [7:0] syndromeIn_11; // syndrome polynom 11
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input [7:0] syndromeIn_12; // syndrome polynom 12
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input [7:0] syndromeIn_13; // syndrome polynom 13
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input [7:0] syndromeIn_14; // syndrome polynom 14
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input [7:0] syndromeIn_15; // syndrome polynom 15
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input [7:0] syndromeIn_16; // syndrome polynom 16
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input [7:0] syndromeIn_17; // syndrome polynom 17
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input [7:0] syndromeIn_18; // syndrome polynom 18
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input [7:0] syndromeIn_19; // syndrome polynom 19
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input [7:0] syndromeIn_20; // syndrome polynom 20
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input [7:0] syndromeIn_21; // syndrome polynom 21
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input [7:0] epsilon_0; // epsilon polynom 0
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input [7:0] epsilon_1; // epsilon polynom 1
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input [7:0] epsilon_2; // epsilon polynom 2
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input [7:0] epsilon_3; // epsilon polynom 3
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input [7:0] epsilon_4; // epsilon polynom 4
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input [7:0] epsilon_5; // epsilon polynom 5
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input [7:0] epsilon_6; // epsilon polynom 6
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input [7:0] epsilon_7; // epsilon polynom 7
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input [7:0] epsilon_8; // epsilon polynom 8
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input [7:0] epsilon_9; // epsilon polynom 9
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input [7:0] epsilon_10; // epsilon polynom 10
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input [7:0] epsilon_11; // epsilon polynom 11
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input [7:0] epsilon_12; // epsilon polynom 12
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input [7:0] epsilon_13; // epsilon polynom 13
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input [7:0] epsilon_14; // epsilon polynom 14
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input [7:0] epsilon_15; // epsilon polynom 15
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input [7:0] epsilon_16; // epsilon polynom 16
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input [7:0] epsilon_17; // epsilon polynom 17
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input [7:0] epsilon_18; // epsilon polynom 18
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input [7:0] epsilon_19; // epsilon polynom 19
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input [7:0] epsilon_20; // epsilon polynom 20
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input [7:0] epsilon_21; // epsilon polynom 21
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input [7:0] epsilon_22; // epsilon polynom 22
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output [7:0] syndromeOut_0; // modified syndrome polynom 0
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output [7:0] syndromeOut_1; // modified syndrome polynom 1
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output [7:0] syndromeOut_2; // modified syndrome polynom 2
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output [7:0] syndromeOut_3; // modified syndrome polynom 3
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output [7:0] syndromeOut_4; // modified syndrome polynom 4
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output [7:0] syndromeOut_5; // modified syndrome polynom 5
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output [7:0] syndromeOut_6; // modified syndrome polynom 6
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output [7:0] syndromeOut_7; // modified syndrome polynom 7
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output [7:0] syndromeOut_8; // modified syndrome polynom 8
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output [7:0] syndromeOut_9; // modified syndrome polynom 9
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output [7:0] syndromeOut_10; // modified syndrome polynom 10
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output [7:0] syndromeOut_11; // modified syndrome polynom 11
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output [7:0] syndromeOut_12; // modified syndrome polynom 12
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output [7:0] syndromeOut_13; // modified syndrome polynom 13
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output [7:0] syndromeOut_14; // modified syndrome polynom 14
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output [7:0] syndromeOut_15; // modified syndrome polynom 15
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output [7:0] syndromeOut_16; // modified syndrome polynom 16
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output [7:0] syndromeOut_17; // modified syndrome polynom 17
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output [7:0] syndromeOut_18; // modified syndrome polynom 18
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output [7:0] syndromeOut_19; // modified syndrome polynom 19
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output [7:0] syndromeOut_20; // modified syndrome polynom 20
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output [7:0] syndromeOut_21; // modified syndrome polynom 21
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output done; // done signal
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//------------------------------------------------------------------------
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// + count
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//- Counter
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//------------------------------------------------------------------------
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reg [4:0] count;
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always @(posedge CLK or negedge RESET) begin
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if (~RESET) begin
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count [4:0] <= 5'd0;
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end
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else if (enable == 1'b1) begin
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if (sync == 1'b1) begin
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count[4:0] <= 5'd1;
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end
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else if ((count[4:0] ==5'd0) || (count[4:0] ==5'd23)) begin
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count[4:0] <= 5'd0;
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end
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else begin
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count[4:0] <= count[4:0] + 5'd1;
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end
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end
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end
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//------------------------------------------------------------------------
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// + done
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//------------------------------------------------------------------------
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reg done;
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always @(count) begin
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if (count[4:0] == 5'd23) begin
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done = 1'b1;
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end
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else begin
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done = 1'b0;
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end
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end
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//------------------------------------------------------------------------
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// + syndromeReg_0,..., syndromeReg_21
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//------------------------------------------------------------------------
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reg [7:0] syndromeReg_0;
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reg [7:0] syndromeReg_1;
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reg [7:0] syndromeReg_2;
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reg [7:0] syndromeReg_3;
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reg [7:0] syndromeReg_4;
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reg [7:0] syndromeReg_5;
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reg [7:0] syndromeReg_6;
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reg [7:0] syndromeReg_7;
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reg [7:0] syndromeReg_8;
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reg [7:0] syndromeReg_9;
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reg [7:0] syndromeReg_10;
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reg [7:0] syndromeReg_11;
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reg [7:0] syndromeReg_12;
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reg [7:0] syndromeReg_13;
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reg [7:0] syndromeReg_14;
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reg [7:0] syndromeReg_15;
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reg [7:0] syndromeReg_16;
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reg [7:0] syndromeReg_17;
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reg [7:0] syndromeReg_18;
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reg [7:0] syndromeReg_19;
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reg [7:0] syndromeReg_20;
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reg [7:0] syndromeReg_21;
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always @(posedge CLK or negedge RESET) begin
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if (~RESET) begin
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syndromeReg_0 [7:0] <= 8'd0;
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syndromeReg_1 [7:0] <= 8'd0;
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syndromeReg_2 [7:0] <= 8'd0;
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syndromeReg_3 [7:0] <= 8'd0;
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syndromeReg_4 [7:0] <= 8'd0;
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syndromeReg_5 [7:0] <= 8'd0;
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syndromeReg_6 [7:0] <= 8'd0;
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syndromeReg_7 [7:0] <= 8'd0;
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syndromeReg_8 [7:0] <= 8'd0;
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syndromeReg_9 [7:0] <= 8'd0;
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syndromeReg_10 [7:0] <= 8'd0;
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syndromeReg_11 [7:0] <= 8'd0;
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syndromeReg_12 [7:0] <= 8'd0;
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syndromeReg_13 [7:0] <= 8'd0;
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syndromeReg_14 [7:0] <= 8'd0;
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syndromeReg_15 [7:0] <= 8'd0;
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syndromeReg_16 [7:0] <= 8'd0;
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syndromeReg_17 [7:0] <= 8'd0;
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syndromeReg_18 [7:0] <= 8'd0;
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syndromeReg_19 [7:0] <= 8'd0;
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syndromeReg_20 [7:0] <= 8'd0;
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syndromeReg_21 [7:0] <= 8'd0;
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end
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else if ((enable == 1'b1) && (sync == 1'b1)) begin
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syndromeReg_0 [7:0] <= syndromeIn_0 [7:0];
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syndromeReg_1 [7:0] <= syndromeIn_1 [7:0];
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syndromeReg_2 [7:0] <= syndromeIn_2 [7:0];
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syndromeReg_3 [7:0] <= syndromeIn_3 [7:0];
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syndromeReg_4 [7:0] <= syndromeIn_4 [7:0];
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syndromeReg_5 [7:0] <= syndromeIn_5 [7:0];
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syndromeReg_6 [7:0] <= syndromeIn_6 [7:0];
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syndromeReg_7 [7:0] <= syndromeIn_7 [7:0];
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syndromeReg_8 [7:0] <= syndromeIn_8 [7:0];
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syndromeReg_9 [7:0] <= syndromeIn_9 [7:0];
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syndromeReg_10 [7:0] <= syndromeIn_10 [7:0];
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syndromeReg_11 [7:0] <= syndromeIn_11 [7:0];
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syndromeReg_12 [7:0] <= syndromeIn_12 [7:0];
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syndromeReg_13 [7:0] <= syndromeIn_13 [7:0];
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syndromeReg_14 [7:0] <= syndromeIn_14 [7:0];
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syndromeReg_15 [7:0] <= syndromeIn_15 [7:0];
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syndromeReg_16 [7:0] <= syndromeIn_16 [7:0];
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syndromeReg_17 [7:0] <= syndromeIn_17 [7:0];
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syndromeReg_18 [7:0] <= syndromeIn_18 [7:0];
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syndromeReg_19 [7:0] <= syndromeIn_19 [7:0];
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syndromeReg_20 [7:0] <= syndromeIn_20 [7:0];
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syndromeReg_21 [7:0] <= syndromeIn_21 [7:0];
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end
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end
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//------------------------------------------------------------------------
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// + epsilonReg_0,..., epsilonReg_22
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//------------------------------------------------------------------------
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reg [7:0] epsilonReg_0;
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reg [7:0] epsilonReg_1;
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reg [7:0] epsilonReg_2;
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reg [7:0] epsilonReg_3;
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reg [7:0] epsilonReg_4;
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reg [7:0] epsilonReg_5;
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reg [7:0] epsilonReg_6;
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reg [7:0] epsilonReg_7;
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reg [7:0] epsilonReg_8;
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reg [7:0] epsilonReg_9;
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reg [7:0] epsilonReg_10;
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reg [7:0] epsilonReg_11;
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reg [7:0] epsilonReg_12;
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reg [7:0] epsilonReg_13;
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|
|
reg [7:0] epsilonReg_14;
|
| 302 |
|
|
reg [7:0] epsilonReg_15;
|
| 303 |
|
|
reg [7:0] epsilonReg_16;
|
| 304 |
|
|
reg [7:0] epsilonReg_17;
|
| 305 |
|
|
reg [7:0] epsilonReg_18;
|
| 306 |
|
|
reg [7:0] epsilonReg_19;
|
| 307 |
|
|
reg [7:0] epsilonReg_20;
|
| 308 |
|
|
reg [7:0] epsilonReg_21;
|
| 309 |
|
|
reg [7:0] epsilonReg_22;
|
| 310 |
|
|
|
| 311 |
|
|
always @(posedge CLK or negedge RESET) begin
|
| 312 |
|
|
if (~RESET) begin
|
| 313 |
|
|
epsilonReg_0 [7:0] <= 8'd0;
|
| 314 |
|
|
epsilonReg_1 [7:0] <= 8'd0;
|
| 315 |
|
|
epsilonReg_2 [7:0] <= 8'd0;
|
| 316 |
|
|
epsilonReg_3 [7:0] <= 8'd0;
|
| 317 |
|
|
epsilonReg_4 [7:0] <= 8'd0;
|
| 318 |
|
|
epsilonReg_5 [7:0] <= 8'd0;
|
| 319 |
|
|
epsilonReg_6 [7:0] <= 8'd0;
|
| 320 |
|
|
epsilonReg_7 [7:0] <= 8'd0;
|
| 321 |
|
|
epsilonReg_8 [7:0] <= 8'd0;
|
| 322 |
|
|
epsilonReg_9 [7:0] <= 8'd0;
|
| 323 |
|
|
epsilonReg_10 [7:0] <= 8'd0;
|
| 324 |
|
|
epsilonReg_11 [7:0] <= 8'd0;
|
| 325 |
|
|
epsilonReg_12 [7:0] <= 8'd0;
|
| 326 |
|
|
epsilonReg_13 [7:0] <= 8'd0;
|
| 327 |
|
|
epsilonReg_14 [7:0] <= 8'd0;
|
| 328 |
|
|
epsilonReg_15 [7:0] <= 8'd0;
|
| 329 |
|
|
epsilonReg_16 [7:0] <= 8'd0;
|
| 330 |
|
|
epsilonReg_17 [7:0] <= 8'd0;
|
| 331 |
|
|
epsilonReg_18 [7:0] <= 8'd0;
|
| 332 |
|
|
epsilonReg_19 [7:0] <= 8'd0;
|
| 333 |
|
|
epsilonReg_20 [7:0] <= 8'd0;
|
| 334 |
|
|
epsilonReg_21 [7:0] <= 8'd0;
|
| 335 |
|
|
epsilonReg_22 [7:0] <= 8'd0;
|
| 336 |
|
|
end
|
| 337 |
|
|
else if (enable == 1'b1) begin
|
| 338 |
|
|
if (sync == 1'b1) begin
|
| 339 |
|
|
epsilonReg_0 [7:0] <= 8'd0;
|
| 340 |
|
|
epsilonReg_1 [7:0] <= epsilon_0[7:0];
|
| 341 |
|
|
epsilonReg_2 [7:0] <= epsilon_1[7:0];
|
| 342 |
|
|
epsilonReg_3 [7:0] <= epsilon_2[7:0];
|
| 343 |
|
|
epsilonReg_4 [7:0] <= epsilon_3[7:0];
|
| 344 |
|
|
epsilonReg_5 [7:0] <= epsilon_4[7:0];
|
| 345 |
|
|
epsilonReg_6 [7:0] <= epsilon_5[7:0];
|
| 346 |
|
|
epsilonReg_7 [7:0] <= epsilon_6[7:0];
|
| 347 |
|
|
epsilonReg_8 [7:0] <= epsilon_7[7:0];
|
| 348 |
|
|
epsilonReg_9 [7:0] <= epsilon_8[7:0];
|
| 349 |
|
|
epsilonReg_10 [7:0] <= epsilon_9[7:0];
|
| 350 |
|
|
epsilonReg_11 [7:0] <= epsilon_10[7:0];
|
| 351 |
|
|
epsilonReg_12 [7:0] <= epsilon_11[7:0];
|
| 352 |
|
|
epsilonReg_13 [7:0] <= epsilon_12[7:0];
|
| 353 |
|
|
epsilonReg_14 [7:0] <= epsilon_13[7:0];
|
| 354 |
|
|
epsilonReg_15 [7:0] <= epsilon_14[7:0];
|
| 355 |
|
|
epsilonReg_16 [7:0] <= epsilon_15[7:0];
|
| 356 |
|
|
epsilonReg_17 [7:0] <= epsilon_16[7:0];
|
| 357 |
|
|
epsilonReg_18 [7:0] <= epsilon_17[7:0];
|
| 358 |
|
|
epsilonReg_19 [7:0] <= epsilon_18[7:0];
|
| 359 |
|
|
epsilonReg_20 [7:0] <= epsilon_19[7:0];
|
| 360 |
|
|
epsilonReg_21 [7:0] <= epsilon_20[7:0];
|
| 361 |
|
|
epsilonReg_22 [7:0] <= epsilon_21[7:0];
|
| 362 |
|
|
end
|
| 363 |
|
|
else begin
|
| 364 |
|
|
epsilonReg_0 [7:0] <= 8'd0;
|
| 365 |
|
|
epsilonReg_1 [7:0] <= epsilonReg_0[7:0];
|
| 366 |
|
|
epsilonReg_2 [7:0] <= epsilonReg_1[7:0];
|
| 367 |
|
|
epsilonReg_3 [7:0] <= epsilonReg_2[7:0];
|
| 368 |
|
|
epsilonReg_4 [7:0] <= epsilonReg_3[7:0];
|
| 369 |
|
|
epsilonReg_5 [7:0] <= epsilonReg_4[7:0];
|
| 370 |
|
|
epsilonReg_6 [7:0] <= epsilonReg_5[7:0];
|
| 371 |
|
|
epsilonReg_7 [7:0] <= epsilonReg_6[7:0];
|
| 372 |
|
|
epsilonReg_8 [7:0] <= epsilonReg_7[7:0];
|
| 373 |
|
|
epsilonReg_9 [7:0] <= epsilonReg_8[7:0];
|
| 374 |
|
|
epsilonReg_10 [7:0] <= epsilonReg_9[7:0];
|
| 375 |
|
|
epsilonReg_11 [7:0] <= epsilonReg_10[7:0];
|
| 376 |
|
|
epsilonReg_12 [7:0] <= epsilonReg_11[7:0];
|
| 377 |
|
|
epsilonReg_13 [7:0] <= epsilonReg_12[7:0];
|
| 378 |
|
|
epsilonReg_14 [7:0] <= epsilonReg_13[7:0];
|
| 379 |
|
|
epsilonReg_15 [7:0] <= epsilonReg_14[7:0];
|
| 380 |
|
|
epsilonReg_16 [7:0] <= epsilonReg_15[7:0];
|
| 381 |
|
|
epsilonReg_17 [7:0] <= epsilonReg_16[7:0];
|
| 382 |
|
|
epsilonReg_18 [7:0] <= epsilonReg_17[7:0];
|
| 383 |
|
|
epsilonReg_19 [7:0] <= epsilonReg_18[7:0];
|
| 384 |
|
|
epsilonReg_20 [7:0] <= epsilonReg_19[7:0];
|
| 385 |
|
|
epsilonReg_21 [7:0] <= epsilonReg_20[7:0];
|
| 386 |
|
|
epsilonReg_22 [7:0] <= epsilonReg_21[7:0];
|
| 387 |
|
|
end
|
| 388 |
|
|
end
|
| 389 |
|
|
end
|
| 390 |
|
|
|
| 391 |
|
|
|
| 392 |
|
|
//------------------------------------------------------------------------
|
| 393 |
|
|
// + epsilonMsb
|
| 394 |
|
|
//------------------------------------------------------------------------
|
| 395 |
|
|
reg [7:0] epsilonMsb;
|
| 396 |
|
|
|
| 397 |
|
|
always @(sync or epsilon_22 or epsilonReg_22 ) begin
|
| 398 |
|
|
if (sync == 1'b1) begin
|
| 399 |
|
|
epsilonMsb [7:0] = epsilon_22 [7:0];
|
| 400 |
|
|
end
|
| 401 |
|
|
else begin
|
| 402 |
|
|
epsilonMsb [7:0] = epsilonReg_22 [7:0];
|
| 403 |
|
|
end
|
| 404 |
|
|
end
|
| 405 |
|
|
|
| 406 |
|
|
|
| 407 |
|
|
//------------------------------------------------------------------------
|
| 408 |
|
|
// + product_0,..., product_21
|
| 409 |
|
|
//------------------------------------------------------------------------
|
| 410 |
|
|
wire [7:0] product_0;
|
| 411 |
|
|
wire [7:0] product_1;
|
| 412 |
|
|
wire [7:0] product_2;
|
| 413 |
|
|
wire [7:0] product_3;
|
| 414 |
|
|
wire [7:0] product_4;
|
| 415 |
|
|
wire [7:0] product_5;
|
| 416 |
|
|
wire [7:0] product_6;
|
| 417 |
|
|
wire [7:0] product_7;
|
| 418 |
|
|
wire [7:0] product_8;
|
| 419 |
|
|
wire [7:0] product_9;
|
| 420 |
|
|
wire [7:0] product_10;
|
| 421 |
|
|
wire [7:0] product_11;
|
| 422 |
|
|
wire [7:0] product_12;
|
| 423 |
|
|
wire [7:0] product_13;
|
| 424 |
|
|
wire [7:0] product_14;
|
| 425 |
|
|
wire [7:0] product_15;
|
| 426 |
|
|
wire [7:0] product_16;
|
| 427 |
|
|
wire [7:0] product_17;
|
| 428 |
|
|
wire [7:0] product_18;
|
| 429 |
|
|
wire [7:0] product_19;
|
| 430 |
|
|
wire [7:0] product_20;
|
| 431 |
|
|
wire [7:0] product_21;
|
| 432 |
|
|
|
| 433 |
|
|
|
| 434 |
|
|
RsDecodeMult RsDecodeMult_0 ( .A(epsilonMsb[7:0]), .B(syndromeReg_0[7:0]), .P(product_0[7:0]));
|
| 435 |
|
|
RsDecodeMult RsDecodeMult_1 ( .A(epsilonMsb[7:0]), .B(syndromeReg_1[7:0]), .P(product_1[7:0]));
|
| 436 |
|
|
RsDecodeMult RsDecodeMult_2 ( .A(epsilonMsb[7:0]), .B(syndromeReg_2[7:0]), .P(product_2[7:0]));
|
| 437 |
|
|
RsDecodeMult RsDecodeMult_3 ( .A(epsilonMsb[7:0]), .B(syndromeReg_3[7:0]), .P(product_3[7:0]));
|
| 438 |
|
|
RsDecodeMult RsDecodeMult_4 ( .A(epsilonMsb[7:0]), .B(syndromeReg_4[7:0]), .P(product_4[7:0]));
|
| 439 |
|
|
RsDecodeMult RsDecodeMult_5 ( .A(epsilonMsb[7:0]), .B(syndromeReg_5[7:0]), .P(product_5[7:0]));
|
| 440 |
|
|
RsDecodeMult RsDecodeMult_6 ( .A(epsilonMsb[7:0]), .B(syndromeReg_6[7:0]), .P(product_6[7:0]));
|
| 441 |
|
|
RsDecodeMult RsDecodeMult_7 ( .A(epsilonMsb[7:0]), .B(syndromeReg_7[7:0]), .P(product_7[7:0]));
|
| 442 |
|
|
RsDecodeMult RsDecodeMult_8 ( .A(epsilonMsb[7:0]), .B(syndromeReg_8[7:0]), .P(product_8[7:0]));
|
| 443 |
|
|
RsDecodeMult RsDecodeMult_9 ( .A(epsilonMsb[7:0]), .B(syndromeReg_9[7:0]), .P(product_9[7:0]));
|
| 444 |
|
|
RsDecodeMult RsDecodeMult_10 ( .A(epsilonMsb[7:0]), .B(syndromeReg_10[7:0]), .P(product_10[7:0]));
|
| 445 |
|
|
RsDecodeMult RsDecodeMult_11 ( .A(epsilonMsb[7:0]), .B(syndromeReg_11[7:0]), .P(product_11[7:0]));
|
| 446 |
|
|
RsDecodeMult RsDecodeMult_12 ( .A(epsilonMsb[7:0]), .B(syndromeReg_12[7:0]), .P(product_12[7:0]));
|
| 447 |
|
|
RsDecodeMult RsDecodeMult_13 ( .A(epsilonMsb[7:0]), .B(syndromeReg_13[7:0]), .P(product_13[7:0]));
|
| 448 |
|
|
RsDecodeMult RsDecodeMult_14 ( .A(epsilonMsb[7:0]), .B(syndromeReg_14[7:0]), .P(product_14[7:0]));
|
| 449 |
|
|
RsDecodeMult RsDecodeMult_15 ( .A(epsilonMsb[7:0]), .B(syndromeReg_15[7:0]), .P(product_15[7:0]));
|
| 450 |
|
|
RsDecodeMult RsDecodeMult_16 ( .A(epsilonMsb[7:0]), .B(syndromeReg_16[7:0]), .P(product_16[7:0]));
|
| 451 |
|
|
RsDecodeMult RsDecodeMult_17 ( .A(epsilonMsb[7:0]), .B(syndromeReg_17[7:0]), .P(product_17[7:0]));
|
| 452 |
|
|
RsDecodeMult RsDecodeMult_18 ( .A(epsilonMsb[7:0]), .B(syndromeReg_18[7:0]), .P(product_18[7:0]));
|
| 453 |
|
|
RsDecodeMult RsDecodeMult_19 ( .A(epsilonMsb[7:0]), .B(syndromeReg_19[7:0]), .P(product_19[7:0]));
|
| 454 |
|
|
RsDecodeMult RsDecodeMult_20 ( .A(epsilonMsb[7:0]), .B(syndromeReg_20[7:0]), .P(product_20[7:0]));
|
| 455 |
|
|
RsDecodeMult RsDecodeMult_21 ( .A(epsilonMsb[7:0]), .B(syndromeReg_21[7:0]), .P(product_21[7:0]));
|
| 456 |
|
|
|
| 457 |
|
|
|
| 458 |
|
|
|
| 459 |
|
|
//------------------------------------------------------------------------
|
| 460 |
|
|
// + sumReg_0,..., sumReg_21
|
| 461 |
|
|
//------------------------------------------------------------------------
|
| 462 |
|
|
reg [7:0] sumReg_0;
|
| 463 |
|
|
reg [7:0] sumReg_1;
|
| 464 |
|
|
reg [7:0] sumReg_2;
|
| 465 |
|
|
reg [7:0] sumReg_3;
|
| 466 |
|
|
reg [7:0] sumReg_4;
|
| 467 |
|
|
reg [7:0] sumReg_5;
|
| 468 |
|
|
reg [7:0] sumReg_6;
|
| 469 |
|
|
reg [7:0] sumReg_7;
|
| 470 |
|
|
reg [7:0] sumReg_8;
|
| 471 |
|
|
reg [7:0] sumReg_9;
|
| 472 |
|
|
reg [7:0] sumReg_10;
|
| 473 |
|
|
reg [7:0] sumReg_11;
|
| 474 |
|
|
reg [7:0] sumReg_12;
|
| 475 |
|
|
reg [7:0] sumReg_13;
|
| 476 |
|
|
reg [7:0] sumReg_14;
|
| 477 |
|
|
reg [7:0] sumReg_15;
|
| 478 |
|
|
reg [7:0] sumReg_16;
|
| 479 |
|
|
reg [7:0] sumReg_17;
|
| 480 |
|
|
reg [7:0] sumReg_18;
|
| 481 |
|
|
reg [7:0] sumReg_19;
|
| 482 |
|
|
reg [7:0] sumReg_20;
|
| 483 |
|
|
reg [7:0] sumReg_21;
|
| 484 |
|
|
|
| 485 |
|
|
|
| 486 |
|
|
always @(posedge CLK or negedge RESET) begin
|
| 487 |
|
|
if (~RESET) begin
|
| 488 |
|
|
sumReg_0 [7:0] <= 8'd0;
|
| 489 |
|
|
sumReg_1 [7:0] <= 8'd0;
|
| 490 |
|
|
sumReg_2 [7:0] <= 8'd0;
|
| 491 |
|
|
sumReg_3 [7:0] <= 8'd0;
|
| 492 |
|
|
sumReg_4 [7:0] <= 8'd0;
|
| 493 |
|
|
sumReg_5 [7:0] <= 8'd0;
|
| 494 |
|
|
sumReg_6 [7:0] <= 8'd0;
|
| 495 |
|
|
sumReg_7 [7:0] <= 8'd0;
|
| 496 |
|
|
sumReg_8 [7:0] <= 8'd0;
|
| 497 |
|
|
sumReg_9 [7:0] <= 8'd0;
|
| 498 |
|
|
sumReg_10 [7:0] <= 8'd0;
|
| 499 |
|
|
sumReg_11 [7:0] <= 8'd0;
|
| 500 |
|
|
sumReg_12 [7:0] <= 8'd0;
|
| 501 |
|
|
sumReg_13 [7:0] <= 8'd0;
|
| 502 |
|
|
sumReg_14 [7:0] <= 8'd0;
|
| 503 |
|
|
sumReg_15 [7:0] <= 8'd0;
|
| 504 |
|
|
sumReg_16 [7:0] <= 8'd0;
|
| 505 |
|
|
sumReg_17 [7:0] <= 8'd0;
|
| 506 |
|
|
sumReg_18 [7:0] <= 8'd0;
|
| 507 |
|
|
sumReg_19 [7:0] <= 8'd0;
|
| 508 |
|
|
sumReg_20 [7:0] <= 8'd0;
|
| 509 |
|
|
sumReg_21 [7:0] <= 8'd0;
|
| 510 |
|
|
end
|
| 511 |
|
|
else if (enable == 1'b1) begin
|
| 512 |
|
|
if (sync == 1'b1) begin
|
| 513 |
|
|
if (epsilon_22[7:0] != 8'd0) begin
|
| 514 |
|
|
sumReg_0 [7:0] <= syndromeIn_0 [7:0];
|
| 515 |
|
|
sumReg_1 [7:0] <= syndromeIn_1 [7:0];
|
| 516 |
|
|
sumReg_2 [7:0] <= syndromeIn_2 [7:0];
|
| 517 |
|
|
sumReg_3 [7:0] <= syndromeIn_3 [7:0];
|
| 518 |
|
|
sumReg_4 [7:0] <= syndromeIn_4 [7:0];
|
| 519 |
|
|
sumReg_5 [7:0] <= syndromeIn_5 [7:0];
|
| 520 |
|
|
sumReg_6 [7:0] <= syndromeIn_6 [7:0];
|
| 521 |
|
|
sumReg_7 [7:0] <= syndromeIn_7 [7:0];
|
| 522 |
|
|
sumReg_8 [7:0] <= syndromeIn_8 [7:0];
|
| 523 |
|
|
sumReg_9 [7:0] <= syndromeIn_9 [7:0];
|
| 524 |
|
|
sumReg_10 [7:0] <= syndromeIn_10 [7:0];
|
| 525 |
|
|
sumReg_11 [7:0] <= syndromeIn_11 [7:0];
|
| 526 |
|
|
sumReg_12 [7:0] <= syndromeIn_12 [7:0];
|
| 527 |
|
|
sumReg_13 [7:0] <= syndromeIn_13 [7:0];
|
| 528 |
|
|
sumReg_14 [7:0] <= syndromeIn_14 [7:0];
|
| 529 |
|
|
sumReg_15 [7:0] <= syndromeIn_15 [7:0];
|
| 530 |
|
|
sumReg_16 [7:0] <= syndromeIn_16 [7:0];
|
| 531 |
|
|
sumReg_17 [7:0] <= syndromeIn_17 [7:0];
|
| 532 |
|
|
sumReg_18 [7:0] <= syndromeIn_18 [7:0];
|
| 533 |
|
|
sumReg_19 [7:0] <= syndromeIn_19 [7:0];
|
| 534 |
|
|
sumReg_20 [7:0] <= syndromeIn_20 [7:0];
|
| 535 |
|
|
sumReg_21 [7:0] <= syndromeIn_21 [7:0];
|
| 536 |
|
|
end
|
| 537 |
|
|
else begin
|
| 538 |
|
|
sumReg_0 [7:0] <= 8'd0;
|
| 539 |
|
|
sumReg_1 [7:0] <= 8'd0;
|
| 540 |
|
|
sumReg_2 [7:0] <= 8'd0;
|
| 541 |
|
|
sumReg_3 [7:0] <= 8'd0;
|
| 542 |
|
|
sumReg_4 [7:0] <= 8'd0;
|
| 543 |
|
|
sumReg_5 [7:0] <= 8'd0;
|
| 544 |
|
|
sumReg_6 [7:0] <= 8'd0;
|
| 545 |
|
|
sumReg_7 [7:0] <= 8'd0;
|
| 546 |
|
|
sumReg_8 [7:0] <= 8'd0;
|
| 547 |
|
|
sumReg_9 [7:0] <= 8'd0;
|
| 548 |
|
|
sumReg_10 [7:0] <= 8'd0;
|
| 549 |
|
|
sumReg_11 [7:0] <= 8'd0;
|
| 550 |
|
|
sumReg_12 [7:0] <= 8'd0;
|
| 551 |
|
|
sumReg_13 [7:0] <= 8'd0;
|
| 552 |
|
|
sumReg_14 [7:0] <= 8'd0;
|
| 553 |
|
|
sumReg_15 [7:0] <= 8'd0;
|
| 554 |
|
|
sumReg_16 [7:0] <= 8'd0;
|
| 555 |
|
|
sumReg_17 [7:0] <= 8'd0;
|
| 556 |
|
|
sumReg_18 [7:0] <= 8'd0;
|
| 557 |
|
|
sumReg_19 [7:0] <= 8'd0;
|
| 558 |
|
|
sumReg_20 [7:0] <= 8'd0;
|
| 559 |
|
|
sumReg_21 [7:0] <= 8'd0;
|
| 560 |
|
|
end
|
| 561 |
|
|
end
|
| 562 |
|
|
else begin
|
| 563 |
|
|
sumReg_0 [7:0] <= product_0 [7:0];
|
| 564 |
|
|
sumReg_1 [7:0] <= sumReg_0 [7:0] ^ product_1 [7:0];
|
| 565 |
|
|
sumReg_2 [7:0] <= sumReg_1 [7:0] ^ product_2 [7:0];
|
| 566 |
|
|
sumReg_3 [7:0] <= sumReg_2 [7:0] ^ product_3 [7:0];
|
| 567 |
|
|
sumReg_4 [7:0] <= sumReg_3 [7:0] ^ product_4 [7:0];
|
| 568 |
|
|
sumReg_5 [7:0] <= sumReg_4 [7:0] ^ product_5 [7:0];
|
| 569 |
|
|
sumReg_6 [7:0] <= sumReg_5 [7:0] ^ product_6 [7:0];
|
| 570 |
|
|
sumReg_7 [7:0] <= sumReg_6 [7:0] ^ product_7 [7:0];
|
| 571 |
|
|
sumReg_8 [7:0] <= sumReg_7 [7:0] ^ product_8 [7:0];
|
| 572 |
|
|
sumReg_9 [7:0] <= sumReg_8 [7:0] ^ product_9 [7:0];
|
| 573 |
|
|
sumReg_10 [7:0] <= sumReg_9 [7:0] ^ product_10 [7:0];
|
| 574 |
|
|
sumReg_11 [7:0] <= sumReg_10 [7:0] ^ product_11 [7:0];
|
| 575 |
|
|
sumReg_12 [7:0] <= sumReg_11 [7:0] ^ product_12 [7:0];
|
| 576 |
|
|
sumReg_13 [7:0] <= sumReg_12 [7:0] ^ product_13 [7:0];
|
| 577 |
|
|
sumReg_14 [7:0] <= sumReg_13 [7:0] ^ product_14 [7:0];
|
| 578 |
|
|
sumReg_15 [7:0] <= sumReg_14 [7:0] ^ product_15 [7:0];
|
| 579 |
|
|
sumReg_16 [7:0] <= sumReg_15 [7:0] ^ product_16 [7:0];
|
| 580 |
|
|
sumReg_17 [7:0] <= sumReg_16 [7:0] ^ product_17 [7:0];
|
| 581 |
|
|
sumReg_18 [7:0] <= sumReg_17 [7:0] ^ product_18 [7:0];
|
| 582 |
|
|
sumReg_19 [7:0] <= sumReg_18 [7:0] ^ product_19 [7:0];
|
| 583 |
|
|
sumReg_20 [7:0] <= sumReg_19 [7:0] ^ product_20 [7:0];
|
| 584 |
|
|
sumReg_21 [7:0] <= sumReg_20 [7:0] ^ product_21 [7:0];
|
| 585 |
|
|
end
|
| 586 |
|
|
end
|
| 587 |
|
|
end
|
| 588 |
|
|
|
| 589 |
|
|
|
| 590 |
|
|
|
| 591 |
|
|
//------------------------------------------------------------------------
|
| 592 |
|
|
// Output signals
|
| 593 |
|
|
//------------------------------------------------------------------------
|
| 594 |
|
|
assign syndromeOut_0 [7:0] = sumReg_0 [7:0];
|
| 595 |
|
|
assign syndromeOut_1 [7:0] = sumReg_1 [7:0];
|
| 596 |
|
|
assign syndromeOut_2 [7:0] = sumReg_2 [7:0];
|
| 597 |
|
|
assign syndromeOut_3 [7:0] = sumReg_3 [7:0];
|
| 598 |
|
|
assign syndromeOut_4 [7:0] = sumReg_4 [7:0];
|
| 599 |
|
|
assign syndromeOut_5 [7:0] = sumReg_5 [7:0];
|
| 600 |
|
|
assign syndromeOut_6 [7:0] = sumReg_6 [7:0];
|
| 601 |
|
|
assign syndromeOut_7 [7:0] = sumReg_7 [7:0];
|
| 602 |
|
|
assign syndromeOut_8 [7:0] = sumReg_8 [7:0];
|
| 603 |
|
|
assign syndromeOut_9 [7:0] = sumReg_9 [7:0];
|
| 604 |
|
|
assign syndromeOut_10 [7:0] = sumReg_10 [7:0];
|
| 605 |
|
|
assign syndromeOut_11 [7:0] = sumReg_11 [7:0];
|
| 606 |
|
|
assign syndromeOut_12 [7:0] = sumReg_12 [7:0];
|
| 607 |
|
|
assign syndromeOut_13 [7:0] = sumReg_13 [7:0];
|
| 608 |
|
|
assign syndromeOut_14 [7:0] = sumReg_14 [7:0];
|
| 609 |
|
|
assign syndromeOut_15 [7:0] = sumReg_15 [7:0];
|
| 610 |
|
|
assign syndromeOut_16 [7:0] = sumReg_16 [7:0];
|
| 611 |
|
|
assign syndromeOut_17 [7:0] = sumReg_17 [7:0];
|
| 612 |
|
|
assign syndromeOut_18 [7:0] = sumReg_18 [7:0];
|
| 613 |
|
|
assign syndromeOut_19 [7:0] = sumReg_19 [7:0];
|
| 614 |
|
|
assign syndromeOut_20 [7:0] = sumReg_20 [7:0];
|
| 615 |
|
|
assign syndromeOut_21 [7:0] = sumReg_21 [7:0];
|
| 616 |
|
|
|
| 617 |
|
|
|
| 618 |
|
|
endmodule
|
