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//===================================================================
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// Module Name : RsDecodeSyndrome
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// File Name : RsDecodeSyndrome.v
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// Function : Rs Decoder syndrome calculation
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//
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// Revision History:
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// Date By Version Change Description
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//===================================================================
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// 2009/02/03 Gael Sapience 1.0 Original
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//
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//===================================================================
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// (C) COPYRIGHT 2009 SYSTEM LSI CO., Ltd.
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//
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module RsDecodeSyndrome(
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CLK, // system clock
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RESET, // system reset
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enable, // enable signal
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sync, // sync signal
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dataIn, // data input
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syndrome_0, // syndrome polynom 0
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syndrome_1, // syndrome polynom 1
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syndrome_2, // syndrome polynom 2
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syndrome_3, // syndrome polynom 3
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syndrome_4, // syndrome polynom 4
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syndrome_5, // syndrome polynom 5
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syndrome_6, // syndrome polynom 6
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syndrome_7, // syndrome polynom 7
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syndrome_8, // syndrome polynom 8
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syndrome_9, // syndrome polynom 9
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syndrome_10, // syndrome polynom 10
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syndrome_11, // syndrome polynom 11
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syndrome_12, // syndrome polynom 12
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syndrome_13, // syndrome polynom 13
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syndrome_14, // syndrome polynom 14
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syndrome_15, // syndrome polynom 15
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syndrome_16, // syndrome polynom 16
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syndrome_17, // syndrome polynom 17
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syndrome_18, // syndrome polynom 18
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syndrome_19, // syndrome polynom 19
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syndrome_20, // syndrome polynom 20
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syndrome_21, // syndrome polynom 21
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done // done signal
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);
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input CLK; // system clock
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input RESET; // system reset
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input enable; // enable signal
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input sync; // sync signal
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input [7:0] dataIn; // data input
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output [7:0] syndrome_0; // syndrome polynom 0
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output [7:0] syndrome_1; // syndrome polynom 1
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output [7:0] syndrome_2; // syndrome polynom 2
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output [7:0] syndrome_3; // syndrome polynom 3
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output [7:0] syndrome_4; // syndrome polynom 4
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output [7:0] syndrome_5; // syndrome polynom 5
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output [7:0] syndrome_6; // syndrome polynom 6
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output [7:0] syndrome_7; // syndrome polynom 7
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output [7:0] syndrome_8; // syndrome polynom 8
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output [7:0] syndrome_9; // syndrome polynom 9
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output [7:0] syndrome_10; // syndrome polynom 10
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output [7:0] syndrome_11; // syndrome polynom 11
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output [7:0] syndrome_12; // syndrome polynom 12
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output [7:0] syndrome_13; // syndrome polynom 13
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output [7:0] syndrome_14; // syndrome polynom 14
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output [7:0] syndrome_15; // syndrome polynom 15
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output [7:0] syndrome_16; // syndrome polynom 16
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output [7:0] syndrome_17; // syndrome polynom 17
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output [7:0] syndrome_18; // syndrome polynom 18
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output [7:0] syndrome_19; // syndrome polynom 19
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output [7:0] syndrome_20; // syndrome polynom 20
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output [7:0] syndrome_21; // syndrome polynom 21
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output done; // done signal
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//------------------------------------------------------------------------
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// + count
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//- Counter
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//------------------------------------------------------------------------
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reg [7:0] count;
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always @(posedge CLK or negedge RESET) begin
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if (~RESET) begin
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count [7:0] <= 8'd0;
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end
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else if (enable == 1'b1) begin
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if (sync == 1'b1) begin
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count[7:0] <= 8'd1;
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end
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else if ( (count[7:0] ==8'd0) || (count[7:0] ==8'd255)) begin
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count[7:0] <= 8'd0;
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end
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else begin
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count[7:0] <= count[7:0] + 8'd1;
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end
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end
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end
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//------------------------------------------------------------------------
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// + done
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//------------------------------------------------------------------------
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reg done;
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always @(count) begin
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if (count ==8'd255) begin
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done = 1'b1;
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end
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else begin
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done = 1'b0;
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end
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end
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//------------------------------------------------------------------------
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// + product_0,..., product_21
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//- Syndrome Generator
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//------------------------------------------------------------------------
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wire [7:0] product_0;
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wire [7:0] product_1;
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wire [7:0] product_2;
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wire [7:0] product_3;
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wire [7:0] product_4;
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wire [7:0] product_5;
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wire [7:0] product_6;
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wire [7:0] product_7;
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wire [7:0] product_8;
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wire [7:0] product_9;
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wire [7:0] product_10;
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wire [7:0] product_11;
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wire [7:0] product_12;
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wire [7:0] product_13;
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wire [7:0] product_14;
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wire [7:0] product_15;
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wire [7:0] product_16;
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wire [7:0] product_17;
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wire [7:0] product_18;
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wire [7:0] product_19;
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wire [7:0] product_20;
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wire [7:0] product_21;
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reg [7:0] reg_0;
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reg [7:0] reg_1;
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reg [7:0] reg_2;
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reg [7:0] reg_3;
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reg [7:0] reg_4;
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reg [7:0] reg_5;
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reg [7:0] reg_6;
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reg [7:0] reg_7;
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reg [7:0] reg_8;
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reg [7:0] reg_9;
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reg [7:0] reg_10;
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reg [7:0] reg_11;
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reg [7:0] reg_12;
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reg [7:0] reg_13;
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reg [7:0] reg_14;
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reg [7:0] reg_15;
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reg [7:0] reg_16;
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reg [7:0] reg_17;
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reg [7:0] reg_18;
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reg [7:0] reg_19;
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reg [7:0] reg_20;
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reg [7:0] reg_21;
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assign product_0 [0] = reg_0[0];
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assign product_0 [1] = reg_0[1];
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assign product_0 [2] = reg_0[2];
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assign product_0 [3] = reg_0[3];
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assign product_0 [4] = reg_0[4];
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assign product_0 [5] = reg_0[5];
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assign product_0 [6] = reg_0[6];
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assign product_0 [7] = reg_0[7];
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assign product_1 [0] = reg_1[7];
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assign product_1 [1] = reg_1[0];
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assign product_1 [2] = reg_1[1] ^ reg_1[7];
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assign product_1 [3] = reg_1[2] ^ reg_1[7];
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assign product_1 [4] = reg_1[3] ^ reg_1[7];
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assign product_1 [5] = reg_1[4];
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assign product_1 [6] = reg_1[5];
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assign product_1 [7] = reg_1[6];
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assign product_2 [0] = reg_2[6];
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assign product_2 [1] = reg_2[7];
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assign product_2 [2] = reg_2[0] ^ reg_2[6];
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assign product_2 [3] = reg_2[1] ^ reg_2[6] ^ reg_2[7];
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assign product_2 [4] = reg_2[2] ^ reg_2[6] ^ reg_2[7];
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assign product_2 [5] = reg_2[3] ^ reg_2[7];
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assign product_2 [6] = reg_2[4];
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assign product_2 [7] = reg_2[5];
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assign product_3 [0] = reg_3[5];
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assign product_3 [1] = reg_3[6];
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assign product_3 [2] = reg_3[5] ^ reg_3[7];
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assign product_3 [3] = reg_3[0] ^ reg_3[5] ^ reg_3[6];
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assign product_3 [4] = reg_3[1] ^ reg_3[5] ^ reg_3[6] ^ reg_3[7];
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assign product_3 [5] = reg_3[2] ^ reg_3[6] ^ reg_3[7];
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assign product_3 [6] = reg_3[3] ^ reg_3[7];
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assign product_3 [7] = reg_3[4];
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assign product_4 [0] = reg_4[4];
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assign product_4 [1] = reg_4[5];
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assign product_4 [2] = reg_4[4] ^ reg_4[6];
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assign product_4 [3] = reg_4[4] ^ reg_4[5] ^ reg_4[7];
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assign product_4 [4] = reg_4[0] ^ reg_4[4] ^ reg_4[5] ^ reg_4[6];
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assign product_4 [5] = reg_4[1] ^ reg_4[5] ^ reg_4[6] ^ reg_4[7];
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assign product_4 [6] = reg_4[2] ^ reg_4[6] ^ reg_4[7];
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assign product_4 [7] = reg_4[3] ^ reg_4[7];
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assign product_5 [0] = reg_5[3] ^ reg_5[7];
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assign product_5 [1] = reg_5[4];
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assign product_5 [2] = reg_5[3] ^ reg_5[5] ^ reg_5[7];
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assign product_5 [3] = reg_5[3] ^ reg_5[4] ^ reg_5[6] ^ reg_5[7];
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assign product_5 [4] = reg_5[3] ^ reg_5[4] ^ reg_5[5];
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assign product_5 [5] = reg_5[0] ^ reg_5[4] ^ reg_5[5] ^ reg_5[6];
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assign product_5 [6] = reg_5[1] ^ reg_5[5] ^ reg_5[6] ^ reg_5[7];
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assign product_5 [7] = reg_5[2] ^ reg_5[6] ^ reg_5[7];
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assign product_6 [0] = reg_6[2] ^ reg_6[6] ^ reg_6[7];
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assign product_6 [1] = reg_6[3] ^ reg_6[7];
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assign product_6 [2] = reg_6[2] ^ reg_6[4] ^ reg_6[6] ^ reg_6[7];
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assign product_6 [3] = reg_6[2] ^ reg_6[3] ^ reg_6[5] ^ reg_6[6];
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assign product_6 [4] = reg_6[2] ^ reg_6[3] ^ reg_6[4];
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assign product_6 [5] = reg_6[3] ^ reg_6[4] ^ reg_6[5];
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assign product_6 [6] = reg_6[0] ^ reg_6[4] ^ reg_6[5] ^ reg_6[6];
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assign product_6 [7] = reg_6[1] ^ reg_6[5] ^ reg_6[6] ^ reg_6[7];
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assign product_7 [0] = reg_7[1] ^ reg_7[5] ^ reg_7[6] ^ reg_7[7];
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assign product_7 [1] = reg_7[2] ^ reg_7[6] ^ reg_7[7];
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assign product_7 [2] = reg_7[1] ^ reg_7[3] ^ reg_7[5] ^ reg_7[6];
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assign product_7 [3] = reg_7[1] ^ reg_7[2] ^ reg_7[4] ^ reg_7[5];
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assign product_7 [4] = reg_7[1] ^ reg_7[2] ^ reg_7[3] ^ reg_7[7];
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assign product_7 [5] = reg_7[2] ^ reg_7[3] ^ reg_7[4];
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assign product_7 [6] = reg_7[3] ^ reg_7[4] ^ reg_7[5];
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assign product_7 [7] = reg_7[0] ^ reg_7[4] ^ reg_7[5] ^ reg_7[6];
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assign product_8 [0] = reg_8[0] ^ reg_8[4] ^ reg_8[5] ^ reg_8[6];
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assign product_8 [1] = reg_8[1] ^ reg_8[5] ^ reg_8[6] ^ reg_8[7];
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assign product_8 [2] = reg_8[0] ^ reg_8[2] ^ reg_8[4] ^ reg_8[5] ^ reg_8[7];
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assign product_8 [3] = reg_8[0] ^ reg_8[1] ^ reg_8[3] ^ reg_8[4];
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assign product_8 [4] = reg_8[0] ^ reg_8[1] ^ reg_8[2] ^ reg_8[6];
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assign product_8 [5] = reg_8[1] ^ reg_8[2] ^ reg_8[3] ^ reg_8[7];
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assign product_8 [6] = reg_8[2] ^ reg_8[3] ^ reg_8[4];
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assign product_8 [7] = reg_8[3] ^ reg_8[4] ^ reg_8[5];
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assign product_9 [0] = reg_9[3] ^ reg_9[4] ^ reg_9[5];
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assign product_9 [1] = reg_9[0] ^ reg_9[4] ^ reg_9[5] ^ reg_9[6];
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assign product_9 [2] = reg_9[1] ^ reg_9[3] ^ reg_9[4] ^ reg_9[6] ^ reg_9[7];
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assign product_9 [3] = reg_9[0] ^ reg_9[2] ^ reg_9[3] ^ reg_9[7];
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assign product_9 [4] = reg_9[0] ^ reg_9[1] ^ reg_9[5];
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assign product_9 [5] = reg_9[0] ^ reg_9[1] ^ reg_9[2] ^ reg_9[6];
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assign product_9 [6] = reg_9[1] ^ reg_9[2] ^ reg_9[3] ^ reg_9[7];
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assign product_9 [7] = reg_9[2] ^ reg_9[3] ^ reg_9[4];
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assign product_10 [0] = reg_10[2] ^ reg_10[3] ^ reg_10[4];
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assign product_10 [1] = reg_10[3] ^ reg_10[4] ^ reg_10[5];
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assign product_10 [2] = reg_10[0] ^ reg_10[2] ^ reg_10[3] ^ reg_10[5] ^ reg_10[6];
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assign product_10 [3] = reg_10[1] ^ reg_10[2] ^ reg_10[6] ^ reg_10[7];
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assign product_10 [4] = reg_10[0] ^ reg_10[4] ^ reg_10[7];
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assign product_10 [5] = reg_10[0] ^ reg_10[1] ^ reg_10[5];
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assign product_10 [6] = reg_10[0] ^ reg_10[1] ^ reg_10[2] ^ reg_10[6];
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assign product_10 [7] = reg_10[1] ^ reg_10[2] ^ reg_10[3] ^ reg_10[7];
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assign product_11 [0] = reg_11[1] ^ reg_11[2] ^ reg_11[3] ^ reg_11[7];
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assign product_11 [1] = reg_11[2] ^ reg_11[3] ^ reg_11[4];
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assign product_11 [2] = reg_11[1] ^ reg_11[2] ^ reg_11[4] ^ reg_11[5] ^ reg_11[7];
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assign product_11 [3] = reg_11[0] ^ reg_11[1] ^ reg_11[5] ^ reg_11[6] ^ reg_11[7];
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assign product_11 [4] = reg_11[3] ^ reg_11[6];
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assign product_11 [5] = reg_11[0] ^ reg_11[4] ^ reg_11[7];
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assign product_11 [6] = reg_11[0] ^ reg_11[1] ^ reg_11[5];
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assign product_11 [7] = reg_11[0] ^ reg_11[1] ^ reg_11[2] ^ reg_11[6];
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assign product_12 [0] = reg_12[0] ^ reg_12[1] ^ reg_12[2] ^ reg_12[6];
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assign product_12 [1] = reg_12[1] ^ reg_12[2] ^ reg_12[3] ^ reg_12[7];
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assign product_12 [2] = reg_12[0] ^ reg_12[1] ^ reg_12[3] ^ reg_12[4] ^ reg_12[6];
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assign product_12 [3] = reg_12[0] ^ reg_12[4] ^ reg_12[5] ^ reg_12[6] ^ reg_12[7];
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assign product_12 [4] = reg_12[2] ^ reg_12[5] ^ reg_12[7];
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assign product_12 [5] = reg_12[3] ^ reg_12[6];
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assign product_12 [6] = reg_12[0] ^ reg_12[4] ^ reg_12[7];
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assign product_12 [7] = reg_12[0] ^ reg_12[1] ^ reg_12[5];
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270 |
|
|
assign product_13 [0] = reg_13[0] ^ reg_13[1] ^ reg_13[5];
|
271 |
|
|
assign product_13 [1] = reg_13[0] ^ reg_13[1] ^ reg_13[2] ^ reg_13[6];
|
272 |
|
|
assign product_13 [2] = reg_13[0] ^ reg_13[2] ^ reg_13[3] ^ reg_13[5] ^ reg_13[7];
|
273 |
|
|
assign product_13 [3] = reg_13[3] ^ reg_13[4] ^ reg_13[5] ^ reg_13[6];
|
274 |
|
|
assign product_13 [4] = reg_13[1] ^ reg_13[4] ^ reg_13[6] ^ reg_13[7];
|
275 |
|
|
assign product_13 [5] = reg_13[2] ^ reg_13[5] ^ reg_13[7];
|
276 |
|
|
assign product_13 [6] = reg_13[3] ^ reg_13[6];
|
277 |
|
|
assign product_13 [7] = reg_13[0] ^ reg_13[4] ^ reg_13[7];
|
278 |
|
|
assign product_14 [0] = reg_14[0] ^ reg_14[4] ^ reg_14[7];
|
279 |
|
|
assign product_14 [1] = reg_14[0] ^ reg_14[1] ^ reg_14[5];
|
280 |
|
|
assign product_14 [2] = reg_14[1] ^ reg_14[2] ^ reg_14[4] ^ reg_14[6] ^ reg_14[7];
|
281 |
|
|
assign product_14 [3] = reg_14[2] ^ reg_14[3] ^ reg_14[4] ^ reg_14[5];
|
282 |
|
|
assign product_14 [4] = reg_14[0] ^ reg_14[3] ^ reg_14[5] ^ reg_14[6] ^ reg_14[7];
|
283 |
|
|
assign product_14 [5] = reg_14[1] ^ reg_14[4] ^ reg_14[6] ^ reg_14[7];
|
284 |
|
|
assign product_14 [6] = reg_14[2] ^ reg_14[5] ^ reg_14[7];
|
285 |
|
|
assign product_14 [7] = reg_14[3] ^ reg_14[6];
|
286 |
|
|
assign product_15 [0] = reg_15[3] ^ reg_15[6];
|
287 |
|
|
assign product_15 [1] = reg_15[0] ^ reg_15[4] ^ reg_15[7];
|
288 |
|
|
assign product_15 [2] = reg_15[0] ^ reg_15[1] ^ reg_15[3] ^ reg_15[5] ^ reg_15[6];
|
289 |
|
|
assign product_15 [3] = reg_15[1] ^ reg_15[2] ^ reg_15[3] ^ reg_15[4] ^ reg_15[7];
|
290 |
|
|
assign product_15 [4] = reg_15[2] ^ reg_15[4] ^ reg_15[5] ^ reg_15[6];
|
291 |
|
|
assign product_15 [5] = reg_15[0] ^ reg_15[3] ^ reg_15[5] ^ reg_15[6] ^ reg_15[7];
|
292 |
|
|
assign product_15 [6] = reg_15[1] ^ reg_15[4] ^ reg_15[6] ^ reg_15[7];
|
293 |
|
|
assign product_15 [7] = reg_15[2] ^ reg_15[5] ^ reg_15[7];
|
294 |
|
|
assign product_16 [0] = reg_16[2] ^ reg_16[5] ^ reg_16[7];
|
295 |
|
|
assign product_16 [1] = reg_16[3] ^ reg_16[6];
|
296 |
|
|
assign product_16 [2] = reg_16[0] ^ reg_16[2] ^ reg_16[4] ^ reg_16[5];
|
297 |
|
|
assign product_16 [3] = reg_16[0] ^ reg_16[1] ^ reg_16[2] ^ reg_16[3] ^ reg_16[6] ^ reg_16[7];
|
298 |
|
|
assign product_16 [4] = reg_16[1] ^ reg_16[3] ^ reg_16[4] ^ reg_16[5];
|
299 |
|
|
assign product_16 [5] = reg_16[2] ^ reg_16[4] ^ reg_16[5] ^ reg_16[6];
|
300 |
|
|
assign product_16 [6] = reg_16[0] ^ reg_16[3] ^ reg_16[5] ^ reg_16[6] ^ reg_16[7];
|
301 |
|
|
assign product_16 [7] = reg_16[1] ^ reg_16[4] ^ reg_16[6] ^ reg_16[7];
|
302 |
|
|
assign product_17 [0] = reg_17[1] ^ reg_17[4] ^ reg_17[6] ^ reg_17[7];
|
303 |
|
|
assign product_17 [1] = reg_17[2] ^ reg_17[5] ^ reg_17[7];
|
304 |
|
|
assign product_17 [2] = reg_17[1] ^ reg_17[3] ^ reg_17[4] ^ reg_17[7];
|
305 |
|
|
assign product_17 [3] = reg_17[0] ^ reg_17[1] ^ reg_17[2] ^ reg_17[5] ^ reg_17[6] ^ reg_17[7];
|
306 |
|
|
assign product_17 [4] = reg_17[0] ^ reg_17[2] ^ reg_17[3] ^ reg_17[4];
|
307 |
|
|
assign product_17 [5] = reg_17[1] ^ reg_17[3] ^ reg_17[4] ^ reg_17[5];
|
308 |
|
|
assign product_17 [6] = reg_17[2] ^ reg_17[4] ^ reg_17[5] ^ reg_17[6];
|
309 |
|
|
assign product_17 [7] = reg_17[0] ^ reg_17[3] ^ reg_17[5] ^ reg_17[6] ^ reg_17[7];
|
310 |
|
|
assign product_18 [0] = reg_18[0] ^ reg_18[3] ^ reg_18[5] ^ reg_18[6] ^ reg_18[7];
|
311 |
|
|
assign product_18 [1] = reg_18[1] ^ reg_18[4] ^ reg_18[6] ^ reg_18[7];
|
312 |
|
|
assign product_18 [2] = reg_18[0] ^ reg_18[2] ^ reg_18[3] ^ reg_18[6];
|
313 |
|
|
assign product_18 [3] = reg_18[0] ^ reg_18[1] ^ reg_18[4] ^ reg_18[5] ^ reg_18[6];
|
314 |
|
|
assign product_18 [4] = reg_18[1] ^ reg_18[2] ^ reg_18[3];
|
315 |
|
|
assign product_18 [5] = reg_18[0] ^ reg_18[2] ^ reg_18[3] ^ reg_18[4];
|
316 |
|
|
assign product_18 [6] = reg_18[1] ^ reg_18[3] ^ reg_18[4] ^ reg_18[5];
|
317 |
|
|
assign product_18 [7] = reg_18[2] ^ reg_18[4] ^ reg_18[5] ^ reg_18[6];
|
318 |
|
|
assign product_19 [0] = reg_19[2] ^ reg_19[4] ^ reg_19[5] ^ reg_19[6];
|
319 |
|
|
assign product_19 [1] = reg_19[0] ^ reg_19[3] ^ reg_19[5] ^ reg_19[6] ^ reg_19[7];
|
320 |
|
|
assign product_19 [2] = reg_19[1] ^ reg_19[2] ^ reg_19[5] ^ reg_19[7];
|
321 |
|
|
assign product_19 [3] = reg_19[0] ^ reg_19[3] ^ reg_19[4] ^ reg_19[5];
|
322 |
|
|
assign product_19 [4] = reg_19[0] ^ reg_19[1] ^ reg_19[2];
|
323 |
|
|
assign product_19 [5] = reg_19[1] ^ reg_19[2] ^ reg_19[3];
|
324 |
|
|
assign product_19 [6] = reg_19[0] ^ reg_19[2] ^ reg_19[3] ^ reg_19[4];
|
325 |
|
|
assign product_19 [7] = reg_19[1] ^ reg_19[3] ^ reg_19[4] ^ reg_19[5];
|
326 |
|
|
assign product_20 [0] = reg_20[1] ^ reg_20[3] ^ reg_20[4] ^ reg_20[5];
|
327 |
|
|
assign product_20 [1] = reg_20[2] ^ reg_20[4] ^ reg_20[5] ^ reg_20[6];
|
328 |
|
|
assign product_20 [2] = reg_20[0] ^ reg_20[1] ^ reg_20[4] ^ reg_20[6] ^ reg_20[7];
|
329 |
|
|
assign product_20 [3] = reg_20[2] ^ reg_20[3] ^ reg_20[4] ^ reg_20[7];
|
330 |
|
|
assign product_20 [4] = reg_20[0] ^ reg_20[1];
|
331 |
|
|
assign product_20 [5] = reg_20[0] ^ reg_20[1] ^ reg_20[2];
|
332 |
|
|
assign product_20 [6] = reg_20[1] ^ reg_20[2] ^ reg_20[3];
|
333 |
|
|
assign product_20 [7] = reg_20[0] ^ reg_20[2] ^ reg_20[3] ^ reg_20[4];
|
334 |
|
|
assign product_21 [0] = reg_21[0] ^ reg_21[2] ^ reg_21[3] ^ reg_21[4];
|
335 |
|
|
assign product_21 [1] = reg_21[1] ^ reg_21[3] ^ reg_21[4] ^ reg_21[5];
|
336 |
|
|
assign product_21 [2] = reg_21[0] ^ reg_21[3] ^ reg_21[5] ^ reg_21[6];
|
337 |
|
|
assign product_21 [3] = reg_21[1] ^ reg_21[2] ^ reg_21[3] ^ reg_21[6] ^ reg_21[7];
|
338 |
|
|
assign product_21 [4] = reg_21[0] ^ reg_21[7];
|
339 |
|
|
assign product_21 [5] = reg_21[0] ^ reg_21[1];
|
340 |
|
|
assign product_21 [6] = reg_21[0] ^ reg_21[1] ^ reg_21[2];
|
341 |
|
|
assign product_21 [7] = reg_21[1] ^ reg_21[2] ^ reg_21[3];
|
342 |
|
|
|
343 |
|
|
|
344 |
|
|
|
345 |
|
|
//------------------------------------------------------------------------
|
346 |
|
|
// + REG_0,..., REG_21
|
347 |
|
|
//------------------------------------------------------------------------
|
348 |
|
|
always @(posedge CLK or negedge RESET) begin
|
349 |
|
|
if (~RESET) begin
|
350 |
|
|
reg_0 [7:0] <= 8'd0;
|
351 |
|
|
reg_1 [7:0] <= 8'd0;
|
352 |
|
|
reg_2 [7:0] <= 8'd0;
|
353 |
|
|
reg_3 [7:0] <= 8'd0;
|
354 |
|
|
reg_4 [7:0] <= 8'd0;
|
355 |
|
|
reg_5 [7:0] <= 8'd0;
|
356 |
|
|
reg_6 [7:0] <= 8'd0;
|
357 |
|
|
reg_7 [7:0] <= 8'd0;
|
358 |
|
|
reg_8 [7:0] <= 8'd0;
|
359 |
|
|
reg_9 [7:0] <= 8'd0;
|
360 |
|
|
reg_10 [7:0] <= 8'd0;
|
361 |
|
|
reg_11 [7:0] <= 8'd0;
|
362 |
|
|
reg_12 [7:0] <= 8'd0;
|
363 |
|
|
reg_13 [7:0] <= 8'd0;
|
364 |
|
|
reg_14 [7:0] <= 8'd0;
|
365 |
|
|
reg_15 [7:0] <= 8'd0;
|
366 |
|
|
reg_16 [7:0] <= 8'd0;
|
367 |
|
|
reg_17 [7:0] <= 8'd0;
|
368 |
|
|
reg_18 [7:0] <= 8'd0;
|
369 |
|
|
reg_19 [7:0] <= 8'd0;
|
370 |
|
|
reg_20 [7:0] <= 8'd0;
|
371 |
|
|
reg_21 [7:0] <= 8'd0;
|
372 |
|
|
end
|
373 |
|
|
else if (enable == 1'b1) begin
|
374 |
|
|
if (sync == 1'b1) begin
|
375 |
|
|
reg_0 [7:0] <= dataIn[7:0];
|
376 |
|
|
reg_1 [7:0] <= dataIn[7:0];
|
377 |
|
|
reg_2 [7:0] <= dataIn[7:0];
|
378 |
|
|
reg_3 [7:0] <= dataIn[7:0];
|
379 |
|
|
reg_4 [7:0] <= dataIn[7:0];
|
380 |
|
|
reg_5 [7:0] <= dataIn[7:0];
|
381 |
|
|
reg_6 [7:0] <= dataIn[7:0];
|
382 |
|
|
reg_7 [7:0] <= dataIn[7:0];
|
383 |
|
|
reg_8 [7:0] <= dataIn[7:0];
|
384 |
|
|
reg_9 [7:0] <= dataIn[7:0];
|
385 |
|
|
reg_10 [7:0] <= dataIn[7:0];
|
386 |
|
|
reg_11 [7:0] <= dataIn[7:0];
|
387 |
|
|
reg_12 [7:0] <= dataIn[7:0];
|
388 |
|
|
reg_13 [7:0] <= dataIn[7:0];
|
389 |
|
|
reg_14 [7:0] <= dataIn[7:0];
|
390 |
|
|
reg_15 [7:0] <= dataIn[7:0];
|
391 |
|
|
reg_16 [7:0] <= dataIn[7:0];
|
392 |
|
|
reg_17 [7:0] <= dataIn[7:0];
|
393 |
|
|
reg_18 [7:0] <= dataIn[7:0];
|
394 |
|
|
reg_19 [7:0] <= dataIn[7:0];
|
395 |
|
|
reg_20 [7:0] <= dataIn[7:0];
|
396 |
|
|
reg_21 [7:0] <= dataIn[7:0];
|
397 |
|
|
end
|
398 |
|
|
else begin
|
399 |
|
|
reg_0 [7:0] <= dataIn [7:0] ^ product_0[7:0];
|
400 |
|
|
reg_1 [7:0] <= dataIn [7:0] ^ product_1[7:0];
|
401 |
|
|
reg_2 [7:0] <= dataIn [7:0] ^ product_2[7:0];
|
402 |
|
|
reg_3 [7:0] <= dataIn [7:0] ^ product_3[7:0];
|
403 |
|
|
reg_4 [7:0] <= dataIn [7:0] ^ product_4[7:0];
|
404 |
|
|
reg_5 [7:0] <= dataIn [7:0] ^ product_5[7:0];
|
405 |
|
|
reg_6 [7:0] <= dataIn [7:0] ^ product_6[7:0];
|
406 |
|
|
reg_7 [7:0] <= dataIn [7:0] ^ product_7[7:0];
|
407 |
|
|
reg_8 [7:0] <= dataIn [7:0] ^ product_8[7:0];
|
408 |
|
|
reg_9 [7:0] <= dataIn [7:0] ^ product_9[7:0];
|
409 |
|
|
reg_10 [7:0] <= dataIn [7:0] ^ product_10[7:0];
|
410 |
|
|
reg_11 [7:0] <= dataIn [7:0] ^ product_11[7:0];
|
411 |
|
|
reg_12 [7:0] <= dataIn [7:0] ^ product_12[7:0];
|
412 |
|
|
reg_13 [7:0] <= dataIn [7:0] ^ product_13[7:0];
|
413 |
|
|
reg_14 [7:0] <= dataIn [7:0] ^ product_14[7:0];
|
414 |
|
|
reg_15 [7:0] <= dataIn [7:0] ^ product_15[7:0];
|
415 |
|
|
reg_16 [7:0] <= dataIn [7:0] ^ product_16[7:0];
|
416 |
|
|
reg_17 [7:0] <= dataIn [7:0] ^ product_17[7:0];
|
417 |
|
|
reg_18 [7:0] <= dataIn [7:0] ^ product_18[7:0];
|
418 |
|
|
reg_19 [7:0] <= dataIn [7:0] ^ product_19[7:0];
|
419 |
|
|
reg_20 [7:0] <= dataIn [7:0] ^ product_20[7:0];
|
420 |
|
|
reg_21 [7:0] <= dataIn [7:0] ^ product_21[7:0];
|
421 |
|
|
end
|
422 |
|
|
end
|
423 |
|
|
end
|
424 |
|
|
|
425 |
|
|
|
426 |
|
|
|
427 |
|
|
//------------------------------------------------------------------------
|
428 |
|
|
//- Output Ports
|
429 |
|
|
//------------------------------------------------------------------------
|
430 |
|
|
assign syndrome_0[7:0] = reg_0[7:0];
|
431 |
|
|
assign syndrome_1[7:0] = reg_1[7:0];
|
432 |
|
|
assign syndrome_2[7:0] = reg_2[7:0];
|
433 |
|
|
assign syndrome_3[7:0] = reg_3[7:0];
|
434 |
|
|
assign syndrome_4[7:0] = reg_4[7:0];
|
435 |
|
|
assign syndrome_5[7:0] = reg_5[7:0];
|
436 |
|
|
assign syndrome_6[7:0] = reg_6[7:0];
|
437 |
|
|
assign syndrome_7[7:0] = reg_7[7:0];
|
438 |
|
|
assign syndrome_8[7:0] = reg_8[7:0];
|
439 |
|
|
assign syndrome_9[7:0] = reg_9[7:0];
|
440 |
|
|
assign syndrome_10[7:0] = reg_10[7:0];
|
441 |
|
|
assign syndrome_11[7:0] = reg_11[7:0];
|
442 |
|
|
assign syndrome_12[7:0] = reg_12[7:0];
|
443 |
|
|
assign syndrome_13[7:0] = reg_13[7:0];
|
444 |
|
|
assign syndrome_14[7:0] = reg_14[7:0];
|
445 |
|
|
assign syndrome_15[7:0] = reg_15[7:0];
|
446 |
|
|
assign syndrome_16[7:0] = reg_16[7:0];
|
447 |
|
|
assign syndrome_17[7:0] = reg_17[7:0];
|
448 |
|
|
assign syndrome_18[7:0] = reg_18[7:0];
|
449 |
|
|
assign syndrome_19[7:0] = reg_19[7:0];
|
450 |
|
|
assign syndrome_20[7:0] = reg_20[7:0];
|
451 |
|
|
assign syndrome_21[7:0] = reg_21[7:0];
|
452 |
|
|
|
453 |
|
|
endmodule
|