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//===================================================================
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// Module Name : RsDecodeTop
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// File Name : RsDecodeTop.v
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// Function : Rs Decoder Top Module
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//
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// Revision History:
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// Date By Version Change Description
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//===================================================================
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// 2009/02/03 Gael Sapience 1.0 Original
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//
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//===================================================================
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// (C) COPYRIGHT 2009 SYSTEM LSI CO., Ltd.
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//
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module RsDecodeTop(
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// Inputs
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CLK, // system clock
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RESET, // system reset
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enable, // system enable
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startPls, // sync signal
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erasureIn, // erasure input
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dataIn, // data input
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// Outputs
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outEnable, // data out valid signal
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outStartPls, // first decoded symbol trigger
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outDone, // last symbol decoded trigger
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errorNum, // number of errors corrected
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erasureNum, // number of erasure corrected
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fail, // decoding failure signal
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delayedData, // decoding failure signal
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outData // data output
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);
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input CLK; // system clock
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input RESET; // system reset
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input enable; // system enable
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input startPls; // sync signal
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input erasureIn; // erasure input
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input [7:0] dataIn; // data input
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output outEnable; // data out valid signal
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output outStartPls; // first decoded symbol trigger
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output outDone; // last symbol decoded trigger
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output [7:0] errorNum; // number of errors corrected
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output [7:0] erasureNum; // number of erasure corrected
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output fail; // decoding failure signal
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output [7:0] delayedData; // delayed input data
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output [7:0] outData; // data output
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//------------------------------------------------------------------------
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// + dataInCheck
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//- assign to 0 if Erasure
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//------------------------------------------------------------------------
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wire [7:0] dataInCheck;
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assign dataInCheck = (erasureIn == 1'b0) ? dataIn : 8'd0;
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//------------------------------------------------------------------
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// + syndrome_0,...,syndrome_21
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// + doneSyndrome
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//- RS Syndrome calculation
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//------------------------------------------------------------------
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wire [7:0] syndrome_0;
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wire [7:0] syndrome_1;
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wire [7:0] syndrome_2;
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wire [7:0] syndrome_3;
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wire [7:0] syndrome_4;
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wire [7:0] syndrome_5;
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wire [7:0] syndrome_6;
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wire [7:0] syndrome_7;
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wire [7:0] syndrome_8;
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wire [7:0] syndrome_9;
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wire [7:0] syndrome_10;
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wire [7:0] syndrome_11;
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wire [7:0] syndrome_12;
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wire [7:0] syndrome_13;
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wire [7:0] syndrome_14;
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wire [7:0] syndrome_15;
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wire [7:0] syndrome_16;
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wire [7:0] syndrome_17;
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wire [7:0] syndrome_18;
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wire [7:0] syndrome_19;
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wire [7:0] syndrome_20;
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wire [7:0] syndrome_21;
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wire doneSyndrome;
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RsDecodeSyndrome RsDecodeSyndrome(
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// Inputs
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.CLK (CLK),
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.RESET (RESET),
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.enable (enable),
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.sync (startPls),
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.dataIn (dataInCheck),
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// Outputs
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.syndrome_0 (syndrome_0),
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.syndrome_1 (syndrome_1),
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.syndrome_2 (syndrome_2),
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.syndrome_3 (syndrome_3),
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.syndrome_4 (syndrome_4),
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.syndrome_5 (syndrome_5),
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.syndrome_6 (syndrome_6),
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.syndrome_7 (syndrome_7),
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.syndrome_8 (syndrome_8),
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.syndrome_9 (syndrome_9),
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.syndrome_10 (syndrome_10),
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.syndrome_11 (syndrome_11),
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.syndrome_12 (syndrome_12),
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.syndrome_13 (syndrome_13),
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.syndrome_14 (syndrome_14),
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.syndrome_15 (syndrome_15),
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.syndrome_16 (syndrome_16),
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.syndrome_17 (syndrome_17),
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.syndrome_18 (syndrome_18),
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.syndrome_19 (syndrome_19),
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.syndrome_20 (syndrome_20),
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.syndrome_21 (syndrome_21),
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.done (doneSyndrome)
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);
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//------------------------------------------------------------------
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// + epsilon_0,..., epsilon_22
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// + degreeEpsilon, failErasure, doneErasure
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//- RS Erasure calculation
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//------------------------------------------------------------------
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wire [7:0] epsilon_0;
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wire [7:0] epsilon_1;
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wire [7:0] epsilon_2;
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wire [7:0] epsilon_3;
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wire [7:0] epsilon_4;
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wire [7:0] epsilon_5;
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wire [7:0] epsilon_6;
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wire [7:0] epsilon_7;
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wire [7:0] epsilon_8;
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wire [7:0] epsilon_9;
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wire [7:0] epsilon_10;
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wire [7:0] epsilon_11;
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wire [7:0] epsilon_12;
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wire [7:0] epsilon_13;
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wire [7:0] epsilon_14;
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wire [7:0] epsilon_15;
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wire [7:0] epsilon_16;
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wire [7:0] epsilon_17;
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wire [7:0] epsilon_18;
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wire [7:0] epsilon_19;
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wire [7:0] epsilon_20;
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wire [7:0] epsilon_21;
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wire [7:0] epsilon_22;
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wire [4:0] degreeEpsilon;
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wire failErasure;
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wire doneErasure;
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RsDecodeErasure RsDecodeErasure(
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// Inputs
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| 163 |
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.CLK (CLK),
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.RESET (RESET),
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| 165 |
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.enable (enable),
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.sync (startPls),
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.erasureIn (erasureIn),
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| 168 |
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// Outputs
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| 169 |
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.epsilon_0 (epsilon_0),
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.epsilon_1 (epsilon_1),
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.epsilon_2 (epsilon_2),
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.epsilon_3 (epsilon_3),
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.epsilon_4 (epsilon_4),
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.epsilon_5 (epsilon_5),
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.epsilon_6 (epsilon_6),
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.epsilon_7 (epsilon_7),
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.epsilon_8 (epsilon_8),
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.epsilon_9 (epsilon_9),
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.epsilon_10 (epsilon_10),
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.epsilon_11 (epsilon_11),
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.epsilon_12 (epsilon_12),
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.epsilon_13 (epsilon_13),
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.epsilon_14 (epsilon_14),
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.epsilon_15 (epsilon_15),
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.epsilon_16 (epsilon_16),
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.epsilon_17 (epsilon_17),
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.epsilon_18 (epsilon_18),
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.epsilon_19 (epsilon_19),
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.epsilon_20 (epsilon_20),
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.epsilon_21 (epsilon_21),
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.epsilon_22 (epsilon_22),
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.numErasure (degreeEpsilon),
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.fail (failErasure),
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.done (doneErasure)
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);
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//------------------------------------------------------------------
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// + polymulSyndrome_0,..., polymulSyndrome_21
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// + donePolymul
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//- RS Polymul calculation
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//------------------------------------------------------------------
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wire [7:0] polymulSyndrome_0;
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wire [7:0] polymulSyndrome_1;
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wire [7:0] polymulSyndrome_2;
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wire [7:0] polymulSyndrome_3;
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wire [7:0] polymulSyndrome_4;
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wire [7:0] polymulSyndrome_5;
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wire [7:0] polymulSyndrome_6;
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wire [7:0] polymulSyndrome_7;
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wire [7:0] polymulSyndrome_8;
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wire [7:0] polymulSyndrome_9;
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wire [7:0] polymulSyndrome_10;
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wire [7:0] polymulSyndrome_11;
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wire [7:0] polymulSyndrome_12;
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wire [7:0] polymulSyndrome_13;
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wire [7:0] polymulSyndrome_14;
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wire [7:0] polymulSyndrome_15;
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wire [7:0] polymulSyndrome_16;
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wire [7:0] polymulSyndrome_17;
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wire [7:0] polymulSyndrome_18;
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wire [7:0] polymulSyndrome_19;
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wire [7:0] polymulSyndrome_20;
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wire [7:0] polymulSyndrome_21;
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wire donePolymul;
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| 228 |
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| 229 |
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RsDecodePolymul RsDecodePolymul(
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// Inputs
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| 231 |
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.CLK (CLK),
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| 232 |
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.RESET (RESET),
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| 233 |
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.enable (enable),
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| 234 |
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.sync (doneSyndrome),
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| 235 |
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.syndromeIn_0 (syndrome_0),
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| 236 |
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.syndromeIn_1 (syndrome_1),
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| 237 |
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.syndromeIn_2 (syndrome_2),
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| 238 |
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.syndromeIn_3 (syndrome_3),
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| 239 |
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.syndromeIn_4 (syndrome_4),
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| 240 |
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.syndromeIn_5 (syndrome_5),
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| 241 |
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.syndromeIn_6 (syndrome_6),
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| 242 |
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.syndromeIn_7 (syndrome_7),
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| 243 |
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.syndromeIn_8 (syndrome_8),
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| 244 |
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.syndromeIn_9 (syndrome_9),
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| 245 |
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.syndromeIn_10 (syndrome_10),
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| 246 |
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.syndromeIn_11 (syndrome_11),
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| 247 |
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.syndromeIn_12 (syndrome_12),
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| 248 |
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.syndromeIn_13 (syndrome_13),
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| 249 |
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.syndromeIn_14 (syndrome_14),
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| 250 |
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.syndromeIn_15 (syndrome_15),
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| 251 |
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.syndromeIn_16 (syndrome_16),
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| 252 |
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.syndromeIn_17 (syndrome_17),
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| 253 |
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.syndromeIn_18 (syndrome_18),
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| 254 |
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.syndromeIn_19 (syndrome_19),
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| 255 |
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.syndromeIn_20 (syndrome_20),
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| 256 |
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.syndromeIn_21 (syndrome_21),
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| 257 |
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.epsilon_0 (epsilon_0),
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| 258 |
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.epsilon_1 (epsilon_1),
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| 259 |
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.epsilon_2 (epsilon_2),
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| 260 |
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.epsilon_3 (epsilon_3),
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| 261 |
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.epsilon_4 (epsilon_4),
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| 262 |
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.epsilon_5 (epsilon_5),
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| 263 |
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.epsilon_6 (epsilon_6),
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| 264 |
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.epsilon_7 (epsilon_7),
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| 265 |
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.epsilon_8 (epsilon_8),
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| 266 |
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.epsilon_9 (epsilon_9),
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| 267 |
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.epsilon_10 (epsilon_10),
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| 268 |
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.epsilon_11 (epsilon_11),
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| 269 |
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.epsilon_12 (epsilon_12),
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| 270 |
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.epsilon_13 (epsilon_13),
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| 271 |
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.epsilon_14 (epsilon_14),
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| 272 |
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.epsilon_15 (epsilon_15),
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| 273 |
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.epsilon_16 (epsilon_16),
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| 274 |
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.epsilon_17 (epsilon_17),
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| 275 |
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.epsilon_18 (epsilon_18),
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| 276 |
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.epsilon_19 (epsilon_19),
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| 277 |
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.epsilon_20 (epsilon_20),
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| 278 |
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.epsilon_21 (epsilon_21),
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| 279 |
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.epsilon_22 (epsilon_22),
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| 280 |
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// Outputs
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| 281 |
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.syndromeOut_0 (polymulSyndrome_0),
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| 282 |
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.syndromeOut_1 (polymulSyndrome_1),
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| 283 |
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.syndromeOut_2 (polymulSyndrome_2),
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| 284 |
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.syndromeOut_3 (polymulSyndrome_3),
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| 285 |
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.syndromeOut_4 (polymulSyndrome_4),
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| 286 |
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.syndromeOut_5 (polymulSyndrome_5),
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| 287 |
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.syndromeOut_6 (polymulSyndrome_6),
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| 288 |
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.syndromeOut_7 (polymulSyndrome_7),
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| 289 |
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.syndromeOut_8 (polymulSyndrome_8),
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| 290 |
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.syndromeOut_9 (polymulSyndrome_9),
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| 291 |
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.syndromeOut_10 (polymulSyndrome_10),
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| 292 |
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.syndromeOut_11 (polymulSyndrome_11),
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| 293 |
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.syndromeOut_12 (polymulSyndrome_12),
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| 294 |
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.syndromeOut_13 (polymulSyndrome_13),
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| 295 |
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.syndromeOut_14 (polymulSyndrome_14),
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| 296 |
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.syndromeOut_15 (polymulSyndrome_15),
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| 297 |
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.syndromeOut_16 (polymulSyndrome_16),
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| 298 |
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.syndromeOut_17 (polymulSyndrome_17),
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| 299 |
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.syndromeOut_18 (polymulSyndrome_18),
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| 300 |
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.syndromeOut_19 (polymulSyndrome_19),
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| 301 |
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.syndromeOut_20 (polymulSyndrome_20),
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| 302 |
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.syndromeOut_21 (polymulSyndrome_21),
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| 303 |
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.done (donePolymul)
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| 304 |
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);
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| 305 |
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| 306 |
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| 307 |
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| 308 |
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//------------------------------------------------------------------
|
| 309 |
|
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// + lambda_0,..., lambda_21
|
| 310 |
|
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// + omega_0,..., omega_21
|
| 311 |
|
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// + numShifted, doneEuclide
|
| 312 |
|
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//- RS EUCLIDE
|
| 313 |
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//------------------------------------------------------------------
|
| 314 |
|
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wire [7:0] lambda_0;
|
| 315 |
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wire [7:0] lambda_1;
|
| 316 |
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wire [7:0] lambda_2;
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| 317 |
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wire [7:0] lambda_3;
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| 318 |
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wire [7:0] lambda_4;
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| 319 |
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wire [7:0] lambda_5;
|
| 320 |
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wire [7:0] lambda_6;
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| 321 |
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wire [7:0] lambda_7;
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| 322 |
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wire [7:0] lambda_8;
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| 323 |
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wire [7:0] lambda_9;
|
| 324 |
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wire [7:0] lambda_10;
|
| 325 |
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wire [7:0] lambda_11;
|
| 326 |
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wire [7:0] lambda_12;
|
| 327 |
|
|
wire [7:0] lambda_13;
|
| 328 |
|
|
wire [7:0] lambda_14;
|
| 329 |
|
|
wire [7:0] lambda_15;
|
| 330 |
|
|
wire [7:0] lambda_16;
|
| 331 |
|
|
wire [7:0] lambda_17;
|
| 332 |
|
|
wire [7:0] lambda_18;
|
| 333 |
|
|
wire [7:0] lambda_19;
|
| 334 |
|
|
wire [7:0] lambda_20;
|
| 335 |
|
|
wire [7:0] lambda_21;
|
| 336 |
|
|
wire [7:0] omega_0;
|
| 337 |
|
|
wire [7:0] omega_1;
|
| 338 |
|
|
wire [7:0] omega_2;
|
| 339 |
|
|
wire [7:0] omega_3;
|
| 340 |
|
|
wire [7:0] omega_4;
|
| 341 |
|
|
wire [7:0] omega_5;
|
| 342 |
|
|
wire [7:0] omega_6;
|
| 343 |
|
|
wire [7:0] omega_7;
|
| 344 |
|
|
wire [7:0] omega_8;
|
| 345 |
|
|
wire [7:0] omega_9;
|
| 346 |
|
|
wire [7:0] omega_10;
|
| 347 |
|
|
wire [7:0] omega_11;
|
| 348 |
|
|
wire [7:0] omega_12;
|
| 349 |
|
|
wire [7:0] omega_13;
|
| 350 |
|
|
wire [7:0] omega_14;
|
| 351 |
|
|
wire [7:0] omega_15;
|
| 352 |
|
|
wire [7:0] omega_16;
|
| 353 |
|
|
wire [7:0] omega_17;
|
| 354 |
|
|
wire [7:0] omega_18;
|
| 355 |
|
|
wire [7:0] omega_19;
|
| 356 |
|
|
wire [7:0] omega_20;
|
| 357 |
|
|
wire [7:0] omega_21;
|
| 358 |
|
|
wire doneEuclide;
|
| 359 |
|
|
wire [4:0] numShifted;
|
| 360 |
|
|
reg [4:0] degreeEpsilonReg;
|
| 361 |
|
|
|
| 362 |
|
|
|
| 363 |
|
|
RsDecodeEuclide RsDecodeEuclide(
|
| 364 |
|
|
// Inputs
|
| 365 |
|
|
.CLK (CLK),
|
| 366 |
|
|
.RESET (RESET),
|
| 367 |
|
|
.enable (enable),
|
| 368 |
|
|
.sync (donePolymul),
|
| 369 |
|
|
.syndrome_0 (polymulSyndrome_0),
|
| 370 |
|
|
.syndrome_1 (polymulSyndrome_1),
|
| 371 |
|
|
.syndrome_2 (polymulSyndrome_2),
|
| 372 |
|
|
.syndrome_3 (polymulSyndrome_3),
|
| 373 |
|
|
.syndrome_4 (polymulSyndrome_4),
|
| 374 |
|
|
.syndrome_5 (polymulSyndrome_5),
|
| 375 |
|
|
.syndrome_6 (polymulSyndrome_6),
|
| 376 |
|
|
.syndrome_7 (polymulSyndrome_7),
|
| 377 |
|
|
.syndrome_8 (polymulSyndrome_8),
|
| 378 |
|
|
.syndrome_9 (polymulSyndrome_9),
|
| 379 |
|
|
.syndrome_10 (polymulSyndrome_10),
|
| 380 |
|
|
.syndrome_11 (polymulSyndrome_11),
|
| 381 |
|
|
.syndrome_12 (polymulSyndrome_12),
|
| 382 |
|
|
.syndrome_13 (polymulSyndrome_13),
|
| 383 |
|
|
.syndrome_14 (polymulSyndrome_14),
|
| 384 |
|
|
.syndrome_15 (polymulSyndrome_15),
|
| 385 |
|
|
.syndrome_16 (polymulSyndrome_16),
|
| 386 |
|
|
.syndrome_17 (polymulSyndrome_17),
|
| 387 |
|
|
.syndrome_18 (polymulSyndrome_18),
|
| 388 |
|
|
.syndrome_19 (polymulSyndrome_19),
|
| 389 |
|
|
.syndrome_20 (polymulSyndrome_20),
|
| 390 |
|
|
.syndrome_21 (polymulSyndrome_21),
|
| 391 |
|
|
.numErasure (degreeEpsilonReg),
|
| 392 |
|
|
// Outputs
|
| 393 |
|
|
.lambda_0 (lambda_0),
|
| 394 |
|
|
.lambda_1 (lambda_1),
|
| 395 |
|
|
.lambda_2 (lambda_2),
|
| 396 |
|
|
.lambda_3 (lambda_3),
|
| 397 |
|
|
.lambda_4 (lambda_4),
|
| 398 |
|
|
.lambda_5 (lambda_5),
|
| 399 |
|
|
.lambda_6 (lambda_6),
|
| 400 |
|
|
.lambda_7 (lambda_7),
|
| 401 |
|
|
.lambda_8 (lambda_8),
|
| 402 |
|
|
.lambda_9 (lambda_9),
|
| 403 |
|
|
.lambda_10 (lambda_10),
|
| 404 |
|
|
.lambda_11 (lambda_11),
|
| 405 |
|
|
.lambda_12 (lambda_12),
|
| 406 |
|
|
.lambda_13 (lambda_13),
|
| 407 |
|
|
.lambda_14 (lambda_14),
|
| 408 |
|
|
.lambda_15 (lambda_15),
|
| 409 |
|
|
.lambda_16 (lambda_16),
|
| 410 |
|
|
.lambda_17 (lambda_17),
|
| 411 |
|
|
.lambda_18 (lambda_18),
|
| 412 |
|
|
.lambda_19 (lambda_19),
|
| 413 |
|
|
.lambda_20 (lambda_20),
|
| 414 |
|
|
.lambda_21 (lambda_21),
|
| 415 |
|
|
.omega_0 (omega_0),
|
| 416 |
|
|
.omega_1 (omega_1),
|
| 417 |
|
|
.omega_2 (omega_2),
|
| 418 |
|
|
.omega_3 (omega_3),
|
| 419 |
|
|
.omega_4 (omega_4),
|
| 420 |
|
|
.omega_5 (omega_5),
|
| 421 |
|
|
.omega_6 (omega_6),
|
| 422 |
|
|
.omega_7 (omega_7),
|
| 423 |
|
|
.omega_8 (omega_8),
|
| 424 |
|
|
.omega_9 (omega_9),
|
| 425 |
|
|
.omega_10 (omega_10),
|
| 426 |
|
|
.omega_11 (omega_11),
|
| 427 |
|
|
.omega_12 (omega_12),
|
| 428 |
|
|
.omega_13 (omega_13),
|
| 429 |
|
|
.omega_14 (omega_14),
|
| 430 |
|
|
.omega_15 (omega_15),
|
| 431 |
|
|
.omega_16 (omega_16),
|
| 432 |
|
|
.omega_17 (omega_17),
|
| 433 |
|
|
.omega_18 (omega_18),
|
| 434 |
|
|
.omega_19 (omega_19),
|
| 435 |
|
|
.omega_20 (omega_20),
|
| 436 |
|
|
.omega_21 (omega_21),
|
| 437 |
|
|
.numShifted (numShifted),
|
| 438 |
|
|
.done (doneEuclide)
|
| 439 |
|
|
);
|
| 440 |
|
|
|
| 441 |
|
|
|
| 442 |
|
|
|
| 443 |
|
|
//------------------------------------------------------------------
|
| 444 |
|
|
// + epsilonReg_0, ..., epsilonReg_22
|
| 445 |
|
|
//-
|
| 446 |
|
|
//------------------------------------------------------------------
|
| 447 |
|
|
reg [7:0] epsilonReg_0;
|
| 448 |
|
|
reg [7:0] epsilonReg_1;
|
| 449 |
|
|
reg [7:0] epsilonReg_2;
|
| 450 |
|
|
reg [7:0] epsilonReg_3;
|
| 451 |
|
|
reg [7:0] epsilonReg_4;
|
| 452 |
|
|
reg [7:0] epsilonReg_5;
|
| 453 |
|
|
reg [7:0] epsilonReg_6;
|
| 454 |
|
|
reg [7:0] epsilonReg_7;
|
| 455 |
|
|
reg [7:0] epsilonReg_8;
|
| 456 |
|
|
reg [7:0] epsilonReg_9;
|
| 457 |
|
|
reg [7:0] epsilonReg_10;
|
| 458 |
|
|
reg [7:0] epsilonReg_11;
|
| 459 |
|
|
reg [7:0] epsilonReg_12;
|
| 460 |
|
|
reg [7:0] epsilonReg_13;
|
| 461 |
|
|
reg [7:0] epsilonReg_14;
|
| 462 |
|
|
reg [7:0] epsilonReg_15;
|
| 463 |
|
|
reg [7:0] epsilonReg_16;
|
| 464 |
|
|
reg [7:0] epsilonReg_17;
|
| 465 |
|
|
reg [7:0] epsilonReg_18;
|
| 466 |
|
|
reg [7:0] epsilonReg_19;
|
| 467 |
|
|
reg [7:0] epsilonReg_20;
|
| 468 |
|
|
reg [7:0] epsilonReg_21;
|
| 469 |
|
|
reg [7:0] epsilonReg_22;
|
| 470 |
|
|
|
| 471 |
|
|
|
| 472 |
|
|
always @(posedge CLK or negedge RESET) begin
|
| 473 |
|
|
if (~RESET) begin
|
| 474 |
|
|
epsilonReg_0 [7:0] <= 8'd0;
|
| 475 |
|
|
epsilonReg_1 [7:0] <= 8'd0;
|
| 476 |
|
|
epsilonReg_2 [7:0] <= 8'd0;
|
| 477 |
|
|
epsilonReg_3 [7:0] <= 8'd0;
|
| 478 |
|
|
epsilonReg_4 [7:0] <= 8'd0;
|
| 479 |
|
|
epsilonReg_5 [7:0] <= 8'd0;
|
| 480 |
|
|
epsilonReg_6 [7:0] <= 8'd0;
|
| 481 |
|
|
epsilonReg_7 [7:0] <= 8'd0;
|
| 482 |
|
|
epsilonReg_8 [7:0] <= 8'd0;
|
| 483 |
|
|
epsilonReg_9 [7:0] <= 8'd0;
|
| 484 |
|
|
epsilonReg_10 [7:0] <= 8'd0;
|
| 485 |
|
|
epsilonReg_11 [7:0] <= 8'd0;
|
| 486 |
|
|
epsilonReg_12 [7:0] <= 8'd0;
|
| 487 |
|
|
epsilonReg_13 [7:0] <= 8'd0;
|
| 488 |
|
|
epsilonReg_14 [7:0] <= 8'd0;
|
| 489 |
|
|
epsilonReg_15 [7:0] <= 8'd0;
|
| 490 |
|
|
epsilonReg_16 [7:0] <= 8'd0;
|
| 491 |
|
|
epsilonReg_17 [7:0] <= 8'd0;
|
| 492 |
|
|
epsilonReg_18 [7:0] <= 8'd0;
|
| 493 |
|
|
epsilonReg_19 [7:0] <= 8'd0;
|
| 494 |
|
|
epsilonReg_20 [7:0] <= 8'd0;
|
| 495 |
|
|
epsilonReg_21 [7:0] <= 8'd0;
|
| 496 |
|
|
epsilonReg_22 [7:0] <= 8'd0;
|
| 497 |
|
|
end
|
| 498 |
|
|
else if ((enable == 1'b1) && (doneErasure == 1'b1)) begin
|
| 499 |
|
|
epsilonReg_0 [7:0] <= epsilon_0 [7:0];
|
| 500 |
|
|
epsilonReg_1 [7:0] <= epsilon_1 [7:0];
|
| 501 |
|
|
epsilonReg_2 [7:0] <= epsilon_2 [7:0];
|
| 502 |
|
|
epsilonReg_3 [7:0] <= epsilon_3 [7:0];
|
| 503 |
|
|
epsilonReg_4 [7:0] <= epsilon_4 [7:0];
|
| 504 |
|
|
epsilonReg_5 [7:0] <= epsilon_5 [7:0];
|
| 505 |
|
|
epsilonReg_6 [7:0] <= epsilon_6 [7:0];
|
| 506 |
|
|
epsilonReg_7 [7:0] <= epsilon_7 [7:0];
|
| 507 |
|
|
epsilonReg_8 [7:0] <= epsilon_8 [7:0];
|
| 508 |
|
|
epsilonReg_9 [7:0] <= epsilon_9 [7:0];
|
| 509 |
|
|
epsilonReg_10 [7:0] <= epsilon_10 [7:0];
|
| 510 |
|
|
epsilonReg_11 [7:0] <= epsilon_11 [7:0];
|
| 511 |
|
|
epsilonReg_12 [7:0] <= epsilon_12 [7:0];
|
| 512 |
|
|
epsilonReg_13 [7:0] <= epsilon_13 [7:0];
|
| 513 |
|
|
epsilonReg_14 [7:0] <= epsilon_14 [7:0];
|
| 514 |
|
|
epsilonReg_15 [7:0] <= epsilon_15 [7:0];
|
| 515 |
|
|
epsilonReg_16 [7:0] <= epsilon_16 [7:0];
|
| 516 |
|
|
epsilonReg_17 [7:0] <= epsilon_17 [7:0];
|
| 517 |
|
|
epsilonReg_18 [7:0] <= epsilon_18 [7:0];
|
| 518 |
|
|
epsilonReg_19 [7:0] <= epsilon_19 [7:0];
|
| 519 |
|
|
epsilonReg_20 [7:0] <= epsilon_20 [7:0];
|
| 520 |
|
|
epsilonReg_21 [7:0] <= epsilon_21 [7:0];
|
| 521 |
|
|
epsilonReg_22 [7:0] <= epsilon_22 [7:0];
|
| 522 |
|
|
end
|
| 523 |
|
|
end
|
| 524 |
|
|
|
| 525 |
|
|
|
| 526 |
|
|
|
| 527 |
|
|
//------------------------------------------------------------------
|
| 528 |
|
|
// + epsilonReg2_0,..., epsilonReg2_22
|
| 529 |
|
|
//-
|
| 530 |
|
|
//------------------------------------------------------------------
|
| 531 |
|
|
reg [7:0] epsilonReg2_0;
|
| 532 |
|
|
reg [7:0] epsilonReg2_1;
|
| 533 |
|
|
reg [7:0] epsilonReg2_2;
|
| 534 |
|
|
reg [7:0] epsilonReg2_3;
|
| 535 |
|
|
reg [7:0] epsilonReg2_4;
|
| 536 |
|
|
reg [7:0] epsilonReg2_5;
|
| 537 |
|
|
reg [7:0] epsilonReg2_6;
|
| 538 |
|
|
reg [7:0] epsilonReg2_7;
|
| 539 |
|
|
reg [7:0] epsilonReg2_8;
|
| 540 |
|
|
reg [7:0] epsilonReg2_9;
|
| 541 |
|
|
reg [7:0] epsilonReg2_10;
|
| 542 |
|
|
reg [7:0] epsilonReg2_11;
|
| 543 |
|
|
reg [7:0] epsilonReg2_12;
|
| 544 |
|
|
reg [7:0] epsilonReg2_13;
|
| 545 |
|
|
reg [7:0] epsilonReg2_14;
|
| 546 |
|
|
reg [7:0] epsilonReg2_15;
|
| 547 |
|
|
reg [7:0] epsilonReg2_16;
|
| 548 |
|
|
reg [7:0] epsilonReg2_17;
|
| 549 |
|
|
reg [7:0] epsilonReg2_18;
|
| 550 |
|
|
reg [7:0] epsilonReg2_19;
|
| 551 |
|
|
reg [7:0] epsilonReg2_20;
|
| 552 |
|
|
reg [7:0] epsilonReg2_21;
|
| 553 |
|
|
reg [7:0] epsilonReg2_22;
|
| 554 |
|
|
|
| 555 |
|
|
|
| 556 |
|
|
always @(posedge CLK or negedge RESET) begin
|
| 557 |
|
|
if (~RESET) begin
|
| 558 |
|
|
epsilonReg2_0 [7:0] <= 8'd0;
|
| 559 |
|
|
epsilonReg2_1 [7:0] <= 8'd0;
|
| 560 |
|
|
epsilonReg2_2 [7:0] <= 8'd0;
|
| 561 |
|
|
epsilonReg2_3 [7:0] <= 8'd0;
|
| 562 |
|
|
epsilonReg2_4 [7:0] <= 8'd0;
|
| 563 |
|
|
epsilonReg2_5 [7:0] <= 8'd0;
|
| 564 |
|
|
epsilonReg2_6 [7:0] <= 8'd0;
|
| 565 |
|
|
epsilonReg2_7 [7:0] <= 8'd0;
|
| 566 |
|
|
epsilonReg2_8 [7:0] <= 8'd0;
|
| 567 |
|
|
epsilonReg2_9 [7:0] <= 8'd0;
|
| 568 |
|
|
epsilonReg2_10 [7:0] <= 8'd0;
|
| 569 |
|
|
epsilonReg2_11 [7:0] <= 8'd0;
|
| 570 |
|
|
epsilonReg2_12 [7:0] <= 8'd0;
|
| 571 |
|
|
epsilonReg2_13 [7:0] <= 8'd0;
|
| 572 |
|
|
epsilonReg2_14 [7:0] <= 8'd0;
|
| 573 |
|
|
epsilonReg2_15 [7:0] <= 8'd0;
|
| 574 |
|
|
epsilonReg2_16 [7:0] <= 8'd0;
|
| 575 |
|
|
epsilonReg2_17 [7:0] <= 8'd0;
|
| 576 |
|
|
epsilonReg2_18 [7:0] <= 8'd0;
|
| 577 |
|
|
epsilonReg2_19 [7:0] <= 8'd0;
|
| 578 |
|
|
epsilonReg2_20 [7:0] <= 8'd0;
|
| 579 |
|
|
epsilonReg2_21 [7:0] <= 8'd0;
|
| 580 |
|
|
epsilonReg2_22 [7:0] <= 8'd0;
|
| 581 |
|
|
end
|
| 582 |
|
|
else if ((enable == 1'b1) && (donePolymul == 1'b1)) begin
|
| 583 |
|
|
epsilonReg2_0 [7:0] <= epsilonReg_0 [7:0];
|
| 584 |
|
|
epsilonReg2_1 [7:0] <= epsilonReg_1 [7:0];
|
| 585 |
|
|
epsilonReg2_2 [7:0] <= epsilonReg_2 [7:0];
|
| 586 |
|
|
epsilonReg2_3 [7:0] <= epsilonReg_3 [7:0];
|
| 587 |
|
|
epsilonReg2_4 [7:0] <= epsilonReg_4 [7:0];
|
| 588 |
|
|
epsilonReg2_5 [7:0] <= epsilonReg_5 [7:0];
|
| 589 |
|
|
epsilonReg2_6 [7:0] <= epsilonReg_6 [7:0];
|
| 590 |
|
|
epsilonReg2_7 [7:0] <= epsilonReg_7 [7:0];
|
| 591 |
|
|
epsilonReg2_8 [7:0] <= epsilonReg_8 [7:0];
|
| 592 |
|
|
epsilonReg2_9 [7:0] <= epsilonReg_9 [7:0];
|
| 593 |
|
|
epsilonReg2_10 [7:0] <= epsilonReg_10 [7:0];
|
| 594 |
|
|
epsilonReg2_11 [7:0] <= epsilonReg_11 [7:0];
|
| 595 |
|
|
epsilonReg2_12 [7:0] <= epsilonReg_12 [7:0];
|
| 596 |
|
|
epsilonReg2_13 [7:0] <= epsilonReg_13 [7:0];
|
| 597 |
|
|
epsilonReg2_14 [7:0] <= epsilonReg_14 [7:0];
|
| 598 |
|
|
epsilonReg2_15 [7:0] <= epsilonReg_15 [7:0];
|
| 599 |
|
|
epsilonReg2_16 [7:0] <= epsilonReg_16 [7:0];
|
| 600 |
|
|
epsilonReg2_17 [7:0] <= epsilonReg_17 [7:0];
|
| 601 |
|
|
epsilonReg2_18 [7:0] <= epsilonReg_18 [7:0];
|
| 602 |
|
|
epsilonReg2_19 [7:0] <= epsilonReg_19 [7:0];
|
| 603 |
|
|
epsilonReg2_20 [7:0] <= epsilonReg_20 [7:0];
|
| 604 |
|
|
epsilonReg2_21 [7:0] <= epsilonReg_21 [7:0];
|
| 605 |
|
|
epsilonReg2_22 [7:0] <= epsilonReg_22 [7:0];
|
| 606 |
|
|
end
|
| 607 |
|
|
end
|
| 608 |
|
|
|
| 609 |
|
|
|
| 610 |
|
|
|
| 611 |
|
|
//------------------------------------------------------------------
|
| 612 |
|
|
// + epsilonReg3_0, ..., epsilonReg3_22
|
| 613 |
|
|
//-
|
| 614 |
|
|
//------------------------------------------------------------------
|
| 615 |
|
|
reg [7:0] epsilonReg3_0;
|
| 616 |
|
|
reg [7:0] epsilonReg3_1;
|
| 617 |
|
|
reg [7:0] epsilonReg3_2;
|
| 618 |
|
|
reg [7:0] epsilonReg3_3;
|
| 619 |
|
|
reg [7:0] epsilonReg3_4;
|
| 620 |
|
|
reg [7:0] epsilonReg3_5;
|
| 621 |
|
|
reg [7:0] epsilonReg3_6;
|
| 622 |
|
|
reg [7:0] epsilonReg3_7;
|
| 623 |
|
|
reg [7:0] epsilonReg3_8;
|
| 624 |
|
|
reg [7:0] epsilonReg3_9;
|
| 625 |
|
|
reg [7:0] epsilonReg3_10;
|
| 626 |
|
|
reg [7:0] epsilonReg3_11;
|
| 627 |
|
|
reg [7:0] epsilonReg3_12;
|
| 628 |
|
|
reg [7:0] epsilonReg3_13;
|
| 629 |
|
|
reg [7:0] epsilonReg3_14;
|
| 630 |
|
|
reg [7:0] epsilonReg3_15;
|
| 631 |
|
|
reg [7:0] epsilonReg3_16;
|
| 632 |
|
|
reg [7:0] epsilonReg3_17;
|
| 633 |
|
|
reg [7:0] epsilonReg3_18;
|
| 634 |
|
|
reg [7:0] epsilonReg3_19;
|
| 635 |
|
|
reg [7:0] epsilonReg3_20;
|
| 636 |
|
|
reg [7:0] epsilonReg3_21;
|
| 637 |
|
|
reg [7:0] epsilonReg3_22;
|
| 638 |
|
|
|
| 639 |
|
|
|
| 640 |
|
|
always @(posedge CLK or negedge RESET) begin
|
| 641 |
|
|
if (~RESET) begin
|
| 642 |
|
|
epsilonReg3_0 [7:0] <= 8'd0;
|
| 643 |
|
|
epsilonReg3_1 [7:0] <= 8'd0;
|
| 644 |
|
|
epsilonReg3_2 [7:0] <= 8'd0;
|
| 645 |
|
|
epsilonReg3_3 [7:0] <= 8'd0;
|
| 646 |
|
|
epsilonReg3_4 [7:0] <= 8'd0;
|
| 647 |
|
|
epsilonReg3_5 [7:0] <= 8'd0;
|
| 648 |
|
|
epsilonReg3_6 [7:0] <= 8'd0;
|
| 649 |
|
|
epsilonReg3_7 [7:0] <= 8'd0;
|
| 650 |
|
|
epsilonReg3_8 [7:0] <= 8'd0;
|
| 651 |
|
|
epsilonReg3_9 [7:0] <= 8'd0;
|
| 652 |
|
|
epsilonReg3_10 [7:0] <= 8'd0;
|
| 653 |
|
|
epsilonReg3_11 [7:0] <= 8'd0;
|
| 654 |
|
|
epsilonReg3_12 [7:0] <= 8'd0;
|
| 655 |
|
|
epsilonReg3_13 [7:0] <= 8'd0;
|
| 656 |
|
|
epsilonReg3_14 [7:0] <= 8'd0;
|
| 657 |
|
|
epsilonReg3_15 [7:0] <= 8'd0;
|
| 658 |
|
|
epsilonReg3_16 [7:0] <= 8'd0;
|
| 659 |
|
|
epsilonReg3_17 [7:0] <= 8'd0;
|
| 660 |
|
|
epsilonReg3_18 [7:0] <= 8'd0;
|
| 661 |
|
|
epsilonReg3_19 [7:0] <= 8'd0;
|
| 662 |
|
|
epsilonReg3_20 [7:0] <= 8'd0;
|
| 663 |
|
|
epsilonReg3_21 [7:0] <= 8'd0;
|
| 664 |
|
|
epsilonReg3_22 [7:0] <= 8'd0;
|
| 665 |
|
|
end
|
| 666 |
|
|
else if ((enable == 1'b1) && (doneEuclide == 1'b1)) begin
|
| 667 |
|
|
epsilonReg3_0 [7:0] <= epsilonReg2_0 [7:0];
|
| 668 |
|
|
epsilonReg3_1 [7:0] <= epsilonReg2_1 [7:0];
|
| 669 |
|
|
epsilonReg3_2 [7:0] <= epsilonReg2_2 [7:0];
|
| 670 |
|
|
epsilonReg3_3 [7:0] <= epsilonReg2_3 [7:0];
|
| 671 |
|
|
epsilonReg3_4 [7:0] <= epsilonReg2_4 [7:0];
|
| 672 |
|
|
epsilonReg3_5 [7:0] <= epsilonReg2_5 [7:0];
|
| 673 |
|
|
epsilonReg3_6 [7:0] <= epsilonReg2_6 [7:0];
|
| 674 |
|
|
epsilonReg3_7 [7:0] <= epsilonReg2_7 [7:0];
|
| 675 |
|
|
epsilonReg3_8 [7:0] <= epsilonReg2_8 [7:0];
|
| 676 |
|
|
epsilonReg3_9 [7:0] <= epsilonReg2_9 [7:0];
|
| 677 |
|
|
epsilonReg3_10 [7:0] <= epsilonReg2_10 [7:0];
|
| 678 |
|
|
epsilonReg3_11 [7:0] <= epsilonReg2_11 [7:0];
|
| 679 |
|
|
epsilonReg3_12 [7:0] <= epsilonReg2_12 [7:0];
|
| 680 |
|
|
epsilonReg3_13 [7:0] <= epsilonReg2_13 [7:0];
|
| 681 |
|
|
epsilonReg3_14 [7:0] <= epsilonReg2_14 [7:0];
|
| 682 |
|
|
epsilonReg3_15 [7:0] <= epsilonReg2_15 [7:0];
|
| 683 |
|
|
epsilonReg3_16 [7:0] <= epsilonReg2_16 [7:0];
|
| 684 |
|
|
epsilonReg3_17 [7:0] <= epsilonReg2_17 [7:0];
|
| 685 |
|
|
epsilonReg3_18 [7:0] <= epsilonReg2_18 [7:0];
|
| 686 |
|
|
epsilonReg3_19 [7:0] <= epsilonReg2_19 [7:0];
|
| 687 |
|
|
epsilonReg3_20 [7:0] <= epsilonReg2_20 [7:0];
|
| 688 |
|
|
epsilonReg3_21 [7:0] <= epsilonReg2_21 [7:0];
|
| 689 |
|
|
epsilonReg3_22 [7:0] <= epsilonReg2_22 [7:0];
|
| 690 |
|
|
end
|
| 691 |
|
|
end
|
| 692 |
|
|
|
| 693 |
|
|
|
| 694 |
|
|
|
| 695 |
|
|
//------------------------------------------------------------------
|
| 696 |
|
|
// + degreeEpsilonReg
|
| 697 |
|
|
//-
|
| 698 |
|
|
//------------------------------------------------------------------
|
| 699 |
|
|
always @(posedge CLK or negedge RESET) begin
|
| 700 |
|
|
if (~RESET) begin
|
| 701 |
|
|
degreeEpsilonReg [4:0] <= 5'd0;
|
| 702 |
|
|
end
|
| 703 |
|
|
else if ((enable == 1'b1) && (doneErasure == 1'b1)) begin
|
| 704 |
|
|
degreeEpsilonReg <= degreeEpsilon;
|
| 705 |
|
|
end
|
| 706 |
|
|
end
|
| 707 |
|
|
|
| 708 |
|
|
|
| 709 |
|
|
|
| 710 |
|
|
//------------------------------------------------------------------
|
| 711 |
|
|
// + degreeEpsilonReg2
|
| 712 |
|
|
//-
|
| 713 |
|
|
//------------------------------------------------------------------
|
| 714 |
|
|
reg [4:0] degreeEpsilonReg2;
|
| 715 |
|
|
always @(posedge CLK or negedge RESET) begin
|
| 716 |
|
|
if (~RESET) begin
|
| 717 |
|
|
degreeEpsilonReg2 [4:0] <= 5'd0;
|
| 718 |
|
|
end
|
| 719 |
|
|
else if ((enable == 1'b1) && (donePolymul == 1'b1)) begin
|
| 720 |
|
|
degreeEpsilonReg2 <= degreeEpsilonReg;
|
| 721 |
|
|
end
|
| 722 |
|
|
end
|
| 723 |
|
|
|
| 724 |
|
|
|
| 725 |
|
|
|
| 726 |
|
|
//------------------------------------------------------------------
|
| 727 |
|
|
// + degreeEpsilonReg3
|
| 728 |
|
|
//-
|
| 729 |
|
|
//------------------------------------------------------------------
|
| 730 |
|
|
reg [4:0] degreeEpsilonReg3;
|
| 731 |
|
|
always @(posedge CLK or negedge RESET) begin
|
| 732 |
|
|
if (~RESET) begin
|
| 733 |
|
|
degreeEpsilonReg3 [4:0] <= 5'd0;
|
| 734 |
|
|
end
|
| 735 |
|
|
else if ((enable == 1'b1) && (doneEuclide == 1'b1)) begin
|
| 736 |
|
|
degreeEpsilonReg3 <= degreeEpsilonReg2;
|
| 737 |
|
|
end
|
| 738 |
|
|
end
|
| 739 |
|
|
|
| 740 |
|
|
|
| 741 |
|
|
|
| 742 |
|
|
reg doneShiftReg;
|
| 743 |
|
|
//------------------------------------------------------------------
|
| 744 |
|
|
// + degreeEpsilonReg4
|
| 745 |
|
|
//-
|
| 746 |
|
|
//------------------------------------------------------------------
|
| 747 |
|
|
reg [4:0] degreeEpsilonReg4;
|
| 748 |
|
|
always @(posedge CLK or negedge RESET) begin
|
| 749 |
|
|
if (~RESET) begin
|
| 750 |
|
|
degreeEpsilonReg4 [4:0] <= 5'd0;
|
| 751 |
|
|
end
|
| 752 |
|
|
else if ((enable == 1'b1) && (doneShiftReg == 1'b1)) begin
|
| 753 |
|
|
degreeEpsilonReg4 <= degreeEpsilonReg3;
|
| 754 |
|
|
end
|
| 755 |
|
|
end
|
| 756 |
|
|
|
| 757 |
|
|
|
| 758 |
|
|
|
| 759 |
|
|
wire doneChien;
|
| 760 |
|
|
//------------------------------------------------------------------
|
| 761 |
|
|
// + degreeEpsilonReg5
|
| 762 |
|
|
//-
|
| 763 |
|
|
//------------------------------------------------------------------
|
| 764 |
|
|
reg [4:0] degreeEpsilonReg5;
|
| 765 |
|
|
always @(posedge CLK or negedge RESET) begin
|
| 766 |
|
|
if (~RESET) begin
|
| 767 |
|
|
degreeEpsilonReg5 [4:0] <= 5'd0;
|
| 768 |
|
|
end
|
| 769 |
|
|
else if ((enable == 1'b1) && (doneChien == 1'b1)) begin
|
| 770 |
|
|
degreeEpsilonReg5 <= degreeEpsilonReg4;
|
| 771 |
|
|
end
|
| 772 |
|
|
end
|
| 773 |
|
|
|
| 774 |
|
|
|
| 775 |
|
|
|
| 776 |
|
|
reg [2:0] doneReg;
|
| 777 |
|
|
//------------------------------------------------------------------
|
| 778 |
|
|
// + numErasureReg
|
| 779 |
|
|
//-
|
| 780 |
|
|
//------------------------------------------------------------------
|
| 781 |
|
|
reg [4:0] numErasureReg;
|
| 782 |
|
|
always @(posedge CLK or negedge RESET) begin
|
| 783 |
|
|
if (~RESET) begin
|
| 784 |
|
|
numErasureReg <= 5'd0;
|
| 785 |
|
|
end
|
| 786 |
|
|
else if ((enable == 1'b1) && (doneReg[0] == 1'b1)) begin
|
| 787 |
|
|
numErasureReg <= degreeEpsilonReg5;
|
| 788 |
|
|
end
|
| 789 |
|
|
end
|
| 790 |
|
|
|
| 791 |
|
|
|
| 792 |
|
|
|
| 793 |
|
|
//------------------------------------------------------------------------
|
| 794 |
|
|
// + doneShift
|
| 795 |
|
|
//------------------------------------------------------------------------
|
| 796 |
|
|
reg doneShift;
|
| 797 |
|
|
always @(posedge CLK or negedge RESET) begin
|
| 798 |
|
|
if (~RESET) begin
|
| 799 |
|
|
doneShift <= 1'b0;
|
| 800 |
|
|
end
|
| 801 |
|
|
else if (enable == 1'b1) begin
|
| 802 |
|
|
doneShift <= doneEuclide;
|
| 803 |
|
|
end
|
| 804 |
|
|
end
|
| 805 |
|
|
|
| 806 |
|
|
|
| 807 |
|
|
|
| 808 |
|
|
//------------------------------------------------------------------
|
| 809 |
|
|
// + numShiftedReg
|
| 810 |
|
|
//------------------------------------------------------------------
|
| 811 |
|
|
reg [4:0] numShiftedReg;
|
| 812 |
|
|
always @(posedge CLK or negedge RESET) begin
|
| 813 |
|
|
if (~RESET) begin
|
| 814 |
|
|
numShiftedReg <= 5'd0;
|
| 815 |
|
|
end
|
| 816 |
|
|
else if ((enable == 1'b1) && (doneEuclide == 1'b1)) begin
|
| 817 |
|
|
numShiftedReg <= numShifted;
|
| 818 |
|
|
end
|
| 819 |
|
|
end
|
| 820 |
|
|
|
| 821 |
|
|
|
| 822 |
|
|
|
| 823 |
|
|
//------------------------------------------------------------------
|
| 824 |
|
|
// + lambdaReg_0,..., lambdaReg_21
|
| 825 |
|
|
//------------------------------------------------------------------
|
| 826 |
|
|
reg [7:0] lambdaReg_0;
|
| 827 |
|
|
reg [7:0] lambdaReg_1;
|
| 828 |
|
|
reg [7:0] lambdaReg_2;
|
| 829 |
|
|
reg [7:0] lambdaReg_3;
|
| 830 |
|
|
reg [7:0] lambdaReg_4;
|
| 831 |
|
|
reg [7:0] lambdaReg_5;
|
| 832 |
|
|
reg [7:0] lambdaReg_6;
|
| 833 |
|
|
reg [7:0] lambdaReg_7;
|
| 834 |
|
|
reg [7:0] lambdaReg_8;
|
| 835 |
|
|
reg [7:0] lambdaReg_9;
|
| 836 |
|
|
reg [7:0] lambdaReg_10;
|
| 837 |
|
|
reg [7:0] lambdaReg_11;
|
| 838 |
|
|
reg [7:0] lambdaReg_12;
|
| 839 |
|
|
reg [7:0] lambdaReg_13;
|
| 840 |
|
|
reg [7:0] lambdaReg_14;
|
| 841 |
|
|
reg [7:0] lambdaReg_15;
|
| 842 |
|
|
reg [7:0] lambdaReg_16;
|
| 843 |
|
|
reg [7:0] lambdaReg_17;
|
| 844 |
|
|
reg [7:0] lambdaReg_18;
|
| 845 |
|
|
reg [7:0] lambdaReg_19;
|
| 846 |
|
|
reg [7:0] lambdaReg_20;
|
| 847 |
|
|
reg [7:0] lambdaReg_21;
|
| 848 |
|
|
|
| 849 |
|
|
|
| 850 |
|
|
always @(posedge CLK or negedge RESET) begin
|
| 851 |
|
|
if (~RESET) begin
|
| 852 |
|
|
lambdaReg_0 [7:0] <= 8'd0;
|
| 853 |
|
|
lambdaReg_1 [7:0] <= 8'd0;
|
| 854 |
|
|
lambdaReg_2 [7:0] <= 8'd0;
|
| 855 |
|
|
lambdaReg_3 [7:0] <= 8'd0;
|
| 856 |
|
|
lambdaReg_4 [7:0] <= 8'd0;
|
| 857 |
|
|
lambdaReg_5 [7:0] <= 8'd0;
|
| 858 |
|
|
lambdaReg_6 [7:0] <= 8'd0;
|
| 859 |
|
|
lambdaReg_7 [7:0] <= 8'd0;
|
| 860 |
|
|
lambdaReg_8 [7:0] <= 8'd0;
|
| 861 |
|
|
lambdaReg_9 [7:0] <= 8'd0;
|
| 862 |
|
|
lambdaReg_10 [7:0] <= 8'd0;
|
| 863 |
|
|
lambdaReg_11 [7:0] <= 8'd0;
|
| 864 |
|
|
lambdaReg_12 [7:0] <= 8'd0;
|
| 865 |
|
|
lambdaReg_13 [7:0] <= 8'd0;
|
| 866 |
|
|
lambdaReg_14 [7:0] <= 8'd0;
|
| 867 |
|
|
lambdaReg_15 [7:0] <= 8'd0;
|
| 868 |
|
|
lambdaReg_16 [7:0] <= 8'd0;
|
| 869 |
|
|
lambdaReg_17 [7:0] <= 8'd0;
|
| 870 |
|
|
lambdaReg_18 [7:0] <= 8'd0;
|
| 871 |
|
|
lambdaReg_19 [7:0] <= 8'd0;
|
| 872 |
|
|
lambdaReg_20 [7:0] <= 8'd0;
|
| 873 |
|
|
lambdaReg_21 [7:0] <= 8'd0;
|
| 874 |
|
|
end
|
| 875 |
|
|
else if ((enable == 1'b1) && (doneEuclide == 1'b1)) begin
|
| 876 |
|
|
lambdaReg_0 [7:0] <= lambda_0 [7:0];
|
| 877 |
|
|
lambdaReg_1 [7:0] <= lambda_1 [7:0];
|
| 878 |
|
|
lambdaReg_2 [7:0] <= lambda_2 [7:0];
|
| 879 |
|
|
lambdaReg_3 [7:0] <= lambda_3 [7:0];
|
| 880 |
|
|
lambdaReg_4 [7:0] <= lambda_4 [7:0];
|
| 881 |
|
|
lambdaReg_5 [7:0] <= lambda_5 [7:0];
|
| 882 |
|
|
lambdaReg_6 [7:0] <= lambda_6 [7:0];
|
| 883 |
|
|
lambdaReg_7 [7:0] <= lambda_7 [7:0];
|
| 884 |
|
|
lambdaReg_8 [7:0] <= lambda_8 [7:0];
|
| 885 |
|
|
lambdaReg_9 [7:0] <= lambda_9 [7:0];
|
| 886 |
|
|
lambdaReg_10 [7:0] <= lambda_10 [7:0];
|
| 887 |
|
|
lambdaReg_11 [7:0] <= lambda_11 [7:0];
|
| 888 |
|
|
lambdaReg_12 [7:0] <= lambda_12 [7:0];
|
| 889 |
|
|
lambdaReg_13 [7:0] <= lambda_13 [7:0];
|
| 890 |
|
|
lambdaReg_14 [7:0] <= lambda_14 [7:0];
|
| 891 |
|
|
lambdaReg_15 [7:0] <= lambda_15 [7:0];
|
| 892 |
|
|
lambdaReg_16 [7:0] <= lambda_16 [7:0];
|
| 893 |
|
|
lambdaReg_17 [7:0] <= lambda_17 [7:0];
|
| 894 |
|
|
lambdaReg_18 [7:0] <= lambda_18 [7:0];
|
| 895 |
|
|
lambdaReg_19 [7:0] <= lambda_19 [7:0];
|
| 896 |
|
|
lambdaReg_20 [7:0] <= lambda_20 [7:0];
|
| 897 |
|
|
lambdaReg_21 [7:0] <= lambda_21 [7:0];
|
| 898 |
|
|
end
|
| 899 |
|
|
end
|
| 900 |
|
|
|
| 901 |
|
|
|
| 902 |
|
|
|
| 903 |
|
|
//------------------------------------------------------------------
|
| 904 |
|
|
// + omegaReg_0,..., omegaReg_21
|
| 905 |
|
|
//------------------------------------------------------------------
|
| 906 |
|
|
reg [7:0] omegaReg_0;
|
| 907 |
|
|
reg [7:0] omegaReg_1;
|
| 908 |
|
|
reg [7:0] omegaReg_2;
|
| 909 |
|
|
reg [7:0] omegaReg_3;
|
| 910 |
|
|
reg [7:0] omegaReg_4;
|
| 911 |
|
|
reg [7:0] omegaReg_5;
|
| 912 |
|
|
reg [7:0] omegaReg_6;
|
| 913 |
|
|
reg [7:0] omegaReg_7;
|
| 914 |
|
|
reg [7:0] omegaReg_8;
|
| 915 |
|
|
reg [7:0] omegaReg_9;
|
| 916 |
|
|
reg [7:0] omegaReg_10;
|
| 917 |
|
|
reg [7:0] omegaReg_11;
|
| 918 |
|
|
reg [7:0] omegaReg_12;
|
| 919 |
|
|
reg [7:0] omegaReg_13;
|
| 920 |
|
|
reg [7:0] omegaReg_14;
|
| 921 |
|
|
reg [7:0] omegaReg_15;
|
| 922 |
|
|
reg [7:0] omegaReg_16;
|
| 923 |
|
|
reg [7:0] omegaReg_17;
|
| 924 |
|
|
reg [7:0] omegaReg_18;
|
| 925 |
|
|
reg [7:0] omegaReg_19;
|
| 926 |
|
|
reg [7:0] omegaReg_20;
|
| 927 |
|
|
reg [7:0] omegaReg_21;
|
| 928 |
|
|
|
| 929 |
|
|
|
| 930 |
|
|
always @(posedge CLK or negedge RESET) begin
|
| 931 |
|
|
if (~RESET) begin
|
| 932 |
|
|
omegaReg_0 [7:0] <= 8'd0;
|
| 933 |
|
|
omegaReg_1 [7:0] <= 8'd0;
|
| 934 |
|
|
omegaReg_2 [7:0] <= 8'd0;
|
| 935 |
|
|
omegaReg_3 [7:0] <= 8'd0;
|
| 936 |
|
|
omegaReg_4 [7:0] <= 8'd0;
|
| 937 |
|
|
omegaReg_5 [7:0] <= 8'd0;
|
| 938 |
|
|
omegaReg_6 [7:0] <= 8'd0;
|
| 939 |
|
|
omegaReg_7 [7:0] <= 8'd0;
|
| 940 |
|
|
omegaReg_8 [7:0] <= 8'd0;
|
| 941 |
|
|
omegaReg_9 [7:0] <= 8'd0;
|
| 942 |
|
|
omegaReg_10 [7:0] <= 8'd0;
|
| 943 |
|
|
omegaReg_11 [7:0] <= 8'd0;
|
| 944 |
|
|
omegaReg_12 [7:0] <= 8'd0;
|
| 945 |
|
|
omegaReg_13 [7:0] <= 8'd0;
|
| 946 |
|
|
omegaReg_14 [7:0] <= 8'd0;
|
| 947 |
|
|
omegaReg_15 [7:0] <= 8'd0;
|
| 948 |
|
|
omegaReg_16 [7:0] <= 8'd0;
|
| 949 |
|
|
omegaReg_17 [7:0] <= 8'd0;
|
| 950 |
|
|
omegaReg_18 [7:0] <= 8'd0;
|
| 951 |
|
|
omegaReg_19 [7:0] <= 8'd0;
|
| 952 |
|
|
omegaReg_20 [7:0] <= 8'd0;
|
| 953 |
|
|
omegaReg_21 [7:0] <= 8'd0;
|
| 954 |
|
|
end
|
| 955 |
|
|
else if ((enable == 1'b1) && (doneEuclide == 1'b1)) begin
|
| 956 |
|
|
omegaReg_0 [7:0] <= omega_0 [7:0];
|
| 957 |
|
|
omegaReg_1 [7:0] <= omega_1 [7:0];
|
| 958 |
|
|
omegaReg_2 [7:0] <= omega_2 [7:0];
|
| 959 |
|
|
omegaReg_3 [7:0] <= omega_3 [7:0];
|
| 960 |
|
|
omegaReg_4 [7:0] <= omega_4 [7:0];
|
| 961 |
|
|
omegaReg_5 [7:0] <= omega_5 [7:0];
|
| 962 |
|
|
omegaReg_6 [7:0] <= omega_6 [7:0];
|
| 963 |
|
|
omegaReg_7 [7:0] <= omega_7 [7:0];
|
| 964 |
|
|
omegaReg_8 [7:0] <= omega_8 [7:0];
|
| 965 |
|
|
omegaReg_9 [7:0] <= omega_9 [7:0];
|
| 966 |
|
|
omegaReg_10 [7:0] <= omega_10 [7:0];
|
| 967 |
|
|
omegaReg_11 [7:0] <= omega_11 [7:0];
|
| 968 |
|
|
omegaReg_12 [7:0] <= omega_12 [7:0];
|
| 969 |
|
|
omegaReg_13 [7:0] <= omega_13 [7:0];
|
| 970 |
|
|
omegaReg_14 [7:0] <= omega_14 [7:0];
|
| 971 |
|
|
omegaReg_15 [7:0] <= omega_15 [7:0];
|
| 972 |
|
|
omegaReg_16 [7:0] <= omega_16 [7:0];
|
| 973 |
|
|
omegaReg_17 [7:0] <= omega_17 [7:0];
|
| 974 |
|
|
omegaReg_18 [7:0] <= omega_18 [7:0];
|
| 975 |
|
|
omegaReg_19 [7:0] <= omega_19 [7:0];
|
| 976 |
|
|
omegaReg_20 [7:0] <= omega_20 [7:0];
|
| 977 |
|
|
omegaReg_21 [7:0] <= omega_21 [7:0];
|
| 978 |
|
|
end
|
| 979 |
|
|
end
|
| 980 |
|
|
|
| 981 |
|
|
|
| 982 |
|
|
|
| 983 |
|
|
//------------------------------------------------------------------
|
| 984 |
|
|
// + omegaShifted_0, ..., omegaShifted_21
|
| 985 |
|
|
//- Rs Shift Omega
|
| 986 |
|
|
//------------------------------------------------------------------
|
| 987 |
|
|
wire [7:0] omegaShifted_0;
|
| 988 |
|
|
wire [7:0] omegaShifted_1;
|
| 989 |
|
|
wire [7:0] omegaShifted_2;
|
| 990 |
|
|
wire [7:0] omegaShifted_3;
|
| 991 |
|
|
wire [7:0] omegaShifted_4;
|
| 992 |
|
|
wire [7:0] omegaShifted_5;
|
| 993 |
|
|
wire [7:0] omegaShifted_6;
|
| 994 |
|
|
wire [7:0] omegaShifted_7;
|
| 995 |
|
|
wire [7:0] omegaShifted_8;
|
| 996 |
|
|
wire [7:0] omegaShifted_9;
|
| 997 |
|
|
wire [7:0] omegaShifted_10;
|
| 998 |
|
|
wire [7:0] omegaShifted_11;
|
| 999 |
|
|
wire [7:0] omegaShifted_12;
|
| 1000 |
|
|
wire [7:0] omegaShifted_13;
|
| 1001 |
|
|
wire [7:0] omegaShifted_14;
|
| 1002 |
|
|
wire [7:0] omegaShifted_15;
|
| 1003 |
|
|
wire [7:0] omegaShifted_16;
|
| 1004 |
|
|
wire [7:0] omegaShifted_17;
|
| 1005 |
|
|
wire [7:0] omegaShifted_18;
|
| 1006 |
|
|
wire [7:0] omegaShifted_19;
|
| 1007 |
|
|
wire [7:0] omegaShifted_20;
|
| 1008 |
|
|
wire [7:0] omegaShifted_21;
|
| 1009 |
|
|
|
| 1010 |
|
|
|
| 1011 |
|
|
RsDecodeShiftOmega RsDecodeShiftOmega(
|
| 1012 |
|
|
// Inputs
|
| 1013 |
|
|
.omega_0 (omegaReg_0),
|
| 1014 |
|
|
.omega_1 (omegaReg_1),
|
| 1015 |
|
|
.omega_2 (omegaReg_2),
|
| 1016 |
|
|
.omega_3 (omegaReg_3),
|
| 1017 |
|
|
.omega_4 (omegaReg_4),
|
| 1018 |
|
|
.omega_5 (omegaReg_5),
|
| 1019 |
|
|
.omega_6 (omegaReg_6),
|
| 1020 |
|
|
.omega_7 (omegaReg_7),
|
| 1021 |
|
|
.omega_8 (omegaReg_8),
|
| 1022 |
|
|
.omega_9 (omegaReg_9),
|
| 1023 |
|
|
.omega_10 (omegaReg_10),
|
| 1024 |
|
|
.omega_11 (omegaReg_11),
|
| 1025 |
|
|
.omega_12 (omegaReg_12),
|
| 1026 |
|
|
.omega_13 (omegaReg_13),
|
| 1027 |
|
|
.omega_14 (omegaReg_14),
|
| 1028 |
|
|
.omega_15 (omegaReg_15),
|
| 1029 |
|
|
.omega_16 (omegaReg_16),
|
| 1030 |
|
|
.omega_17 (omegaReg_17),
|
| 1031 |
|
|
.omega_18 (omegaReg_18),
|
| 1032 |
|
|
.omega_19 (omegaReg_19),
|
| 1033 |
|
|
.omega_20 (omegaReg_20),
|
| 1034 |
|
|
.omega_21 (omegaReg_21),
|
| 1035 |
|
|
// Outputs
|
| 1036 |
|
|
.omegaShifted_0 (omegaShifted_0),
|
| 1037 |
|
|
.omegaShifted_1 (omegaShifted_1),
|
| 1038 |
|
|
.omegaShifted_2 (omegaShifted_2),
|
| 1039 |
|
|
.omegaShifted_3 (omegaShifted_3),
|
| 1040 |
|
|
.omegaShifted_4 (omegaShifted_4),
|
| 1041 |
|
|
.omegaShifted_5 (omegaShifted_5),
|
| 1042 |
|
|
.omegaShifted_6 (omegaShifted_6),
|
| 1043 |
|
|
.omegaShifted_7 (omegaShifted_7),
|
| 1044 |
|
|
.omegaShifted_8 (omegaShifted_8),
|
| 1045 |
|
|
.omegaShifted_9 (omegaShifted_9),
|
| 1046 |
|
|
.omegaShifted_10 (omegaShifted_10),
|
| 1047 |
|
|
.omegaShifted_11 (omegaShifted_11),
|
| 1048 |
|
|
.omegaShifted_12 (omegaShifted_12),
|
| 1049 |
|
|
.omegaShifted_13 (omegaShifted_13),
|
| 1050 |
|
|
.omegaShifted_14 (omegaShifted_14),
|
| 1051 |
|
|
.omegaShifted_15 (omegaShifted_15),
|
| 1052 |
|
|
.omegaShifted_16 (omegaShifted_16),
|
| 1053 |
|
|
.omegaShifted_17 (omegaShifted_17),
|
| 1054 |
|
|
.omegaShifted_18 (omegaShifted_18),
|
| 1055 |
|
|
.omegaShifted_19 (omegaShifted_19),
|
| 1056 |
|
|
.omegaShifted_20 (omegaShifted_20),
|
| 1057 |
|
|
.omegaShifted_21 (omegaShifted_21),
|
| 1058 |
|
|
// Inputs
|
| 1059 |
|
|
.numShifted (numShiftedReg)
|
| 1060 |
|
|
);
|
| 1061 |
|
|
|
| 1062 |
|
|
|
| 1063 |
|
|
|
| 1064 |
|
|
//------------------------------------------------------------------
|
| 1065 |
|
|
// + omegaShiftedReg_0,.., omegaShiftedReg_21
|
| 1066 |
|
|
//------------------------------------------------------------------
|
| 1067 |
|
|
reg [7:0] omegaShiftedReg_0;
|
| 1068 |
|
|
reg [7:0] omegaShiftedReg_1;
|
| 1069 |
|
|
reg [7:0] omegaShiftedReg_2;
|
| 1070 |
|
|
reg [7:0] omegaShiftedReg_3;
|
| 1071 |
|
|
reg [7:0] omegaShiftedReg_4;
|
| 1072 |
|
|
reg [7:0] omegaShiftedReg_5;
|
| 1073 |
|
|
reg [7:0] omegaShiftedReg_6;
|
| 1074 |
|
|
reg [7:0] omegaShiftedReg_7;
|
| 1075 |
|
|
reg [7:0] omegaShiftedReg_8;
|
| 1076 |
|
|
reg [7:0] omegaShiftedReg_9;
|
| 1077 |
|
|
reg [7:0] omegaShiftedReg_10;
|
| 1078 |
|
|
reg [7:0] omegaShiftedReg_11;
|
| 1079 |
|
|
reg [7:0] omegaShiftedReg_12;
|
| 1080 |
|
|
reg [7:0] omegaShiftedReg_13;
|
| 1081 |
|
|
reg [7:0] omegaShiftedReg_14;
|
| 1082 |
|
|
reg [7:0] omegaShiftedReg_15;
|
| 1083 |
|
|
reg [7:0] omegaShiftedReg_16;
|
| 1084 |
|
|
reg [7:0] omegaShiftedReg_17;
|
| 1085 |
|
|
reg [7:0] omegaShiftedReg_18;
|
| 1086 |
|
|
reg [7:0] omegaShiftedReg_19;
|
| 1087 |
|
|
reg [7:0] omegaShiftedReg_20;
|
| 1088 |
|
|
reg [7:0] omegaShiftedReg_21;
|
| 1089 |
|
|
|
| 1090 |
|
|
|
| 1091 |
|
|
always @(posedge CLK or negedge RESET) begin
|
| 1092 |
|
|
if (~RESET) begin
|
| 1093 |
|
|
omegaShiftedReg_0 [7:0] <= 8'd0;
|
| 1094 |
|
|
omegaShiftedReg_1 [7:0] <= 8'd0;
|
| 1095 |
|
|
omegaShiftedReg_2 [7:0] <= 8'd0;
|
| 1096 |
|
|
omegaShiftedReg_3 [7:0] <= 8'd0;
|
| 1097 |
|
|
omegaShiftedReg_4 [7:0] <= 8'd0;
|
| 1098 |
|
|
omegaShiftedReg_5 [7:0] <= 8'd0;
|
| 1099 |
|
|
omegaShiftedReg_6 [7:0] <= 8'd0;
|
| 1100 |
|
|
omegaShiftedReg_7 [7:0] <= 8'd0;
|
| 1101 |
|
|
omegaShiftedReg_8 [7:0] <= 8'd0;
|
| 1102 |
|
|
omegaShiftedReg_9 [7:0] <= 8'd0;
|
| 1103 |
|
|
omegaShiftedReg_10 [7:0] <= 8'd0;
|
| 1104 |
|
|
omegaShiftedReg_11 [7:0] <= 8'd0;
|
| 1105 |
|
|
omegaShiftedReg_12 [7:0] <= 8'd0;
|
| 1106 |
|
|
omegaShiftedReg_13 [7:0] <= 8'd0;
|
| 1107 |
|
|
omegaShiftedReg_14 [7:0] <= 8'd0;
|
| 1108 |
|
|
omegaShiftedReg_15 [7:0] <= 8'd0;
|
| 1109 |
|
|
omegaShiftedReg_16 [7:0] <= 8'd0;
|
| 1110 |
|
|
omegaShiftedReg_17 [7:0] <= 8'd0;
|
| 1111 |
|
|
omegaShiftedReg_18 [7:0] <= 8'd0;
|
| 1112 |
|
|
omegaShiftedReg_19 [7:0] <= 8'd0;
|
| 1113 |
|
|
omegaShiftedReg_20 [7:0] <= 8'd0;
|
| 1114 |
|
|
omegaShiftedReg_21 [7:0] <= 8'd0;
|
| 1115 |
|
|
end
|
| 1116 |
|
|
else if (enable == 1'b1) begin
|
| 1117 |
|
|
omegaShiftedReg_0 [7:0] <= omegaShifted_0 [7:0];
|
| 1118 |
|
|
omegaShiftedReg_1 [7:0] <= omegaShifted_1 [7:0];
|
| 1119 |
|
|
omegaShiftedReg_2 [7:0] <= omegaShifted_2 [7:0];
|
| 1120 |
|
|
omegaShiftedReg_3 [7:0] <= omegaShifted_3 [7:0];
|
| 1121 |
|
|
omegaShiftedReg_4 [7:0] <= omegaShifted_4 [7:0];
|
| 1122 |
|
|
omegaShiftedReg_5 [7:0] <= omegaShifted_5 [7:0];
|
| 1123 |
|
|
omegaShiftedReg_6 [7:0] <= omegaShifted_6 [7:0];
|
| 1124 |
|
|
omegaShiftedReg_7 [7:0] <= omegaShifted_7 [7:0];
|
| 1125 |
|
|
omegaShiftedReg_8 [7:0] <= omegaShifted_8 [7:0];
|
| 1126 |
|
|
omegaShiftedReg_9 [7:0] <= omegaShifted_9 [7:0];
|
| 1127 |
|
|
omegaShiftedReg_10 [7:0] <= omegaShifted_10 [7:0];
|
| 1128 |
|
|
omegaShiftedReg_11 [7:0] <= omegaShifted_11 [7:0];
|
| 1129 |
|
|
omegaShiftedReg_12 [7:0] <= omegaShifted_12 [7:0];
|
| 1130 |
|
|
omegaShiftedReg_13 [7:0] <= omegaShifted_13 [7:0];
|
| 1131 |
|
|
omegaShiftedReg_14 [7:0] <= omegaShifted_14 [7:0];
|
| 1132 |
|
|
omegaShiftedReg_15 [7:0] <= omegaShifted_15 [7:0];
|
| 1133 |
|
|
omegaShiftedReg_16 [7:0] <= omegaShifted_16 [7:0];
|
| 1134 |
|
|
omegaShiftedReg_17 [7:0] <= omegaShifted_17 [7:0];
|
| 1135 |
|
|
omegaShiftedReg_18 [7:0] <= omegaShifted_18 [7:0];
|
| 1136 |
|
|
omegaShiftedReg_19 [7:0] <= omegaShifted_19 [7:0];
|
| 1137 |
|
|
omegaShiftedReg_20 [7:0] <= omegaShifted_20 [7:0];
|
| 1138 |
|
|
omegaShiftedReg_21 [7:0] <= omegaShifted_21 [7:0];
|
| 1139 |
|
|
end
|
| 1140 |
|
|
end
|
| 1141 |
|
|
|
| 1142 |
|
|
|
| 1143 |
|
|
|
| 1144 |
|
|
//------------------------------------------------------------------
|
| 1145 |
|
|
// + degreeOmega
|
| 1146 |
|
|
//------------------------------------------------------------------
|
| 1147 |
|
|
wire [4:0] degreeOmega;
|
| 1148 |
|
|
|
| 1149 |
|
|
|
| 1150 |
|
|
RsDecodeDegree RsDecodeDegree_1(
|
| 1151 |
|
|
// Inputs
|
| 1152 |
|
|
.polynom_0 (omegaShiftedReg_0),
|
| 1153 |
|
|
.polynom_1 (omegaShiftedReg_1),
|
| 1154 |
|
|
.polynom_2 (omegaShiftedReg_2),
|
| 1155 |
|
|
.polynom_3 (omegaShiftedReg_3),
|
| 1156 |
|
|
.polynom_4 (omegaShiftedReg_4),
|
| 1157 |
|
|
.polynom_5 (omegaShiftedReg_5),
|
| 1158 |
|
|
.polynom_6 (omegaShiftedReg_6),
|
| 1159 |
|
|
.polynom_7 (omegaShiftedReg_7),
|
| 1160 |
|
|
.polynom_8 (omegaShiftedReg_8),
|
| 1161 |
|
|
.polynom_9 (omegaShiftedReg_9),
|
| 1162 |
|
|
.polynom_10 (omegaShiftedReg_10),
|
| 1163 |
|
|
.polynom_11 (omegaShiftedReg_11),
|
| 1164 |
|
|
.polynom_12 (omegaShiftedReg_12),
|
| 1165 |
|
|
.polynom_13 (omegaShiftedReg_13),
|
| 1166 |
|
|
.polynom_14 (omegaShiftedReg_14),
|
| 1167 |
|
|
.polynom_15 (omegaShiftedReg_15),
|
| 1168 |
|
|
.polynom_16 (omegaShiftedReg_16),
|
| 1169 |
|
|
.polynom_17 (omegaShiftedReg_17),
|
| 1170 |
|
|
.polynom_18 (omegaShiftedReg_18),
|
| 1171 |
|
|
.polynom_19 (omegaShiftedReg_19),
|
| 1172 |
|
|
.polynom_20 (omegaShiftedReg_20),
|
| 1173 |
|
|
.polynom_21 (omegaShiftedReg_21),
|
| 1174 |
|
|
// Outputs
|
| 1175 |
|
|
.degree (degreeOmega)
|
| 1176 |
|
|
);
|
| 1177 |
|
|
|
| 1178 |
|
|
|
| 1179 |
|
|
|
| 1180 |
|
|
//------------------------------------------------------------------
|
| 1181 |
|
|
// + lambdaReg2_0,.., lambdaReg2_21
|
| 1182 |
|
|
//------------------------------------------------------------------
|
| 1183 |
|
|
reg [7:0] lambdaReg2_0;
|
| 1184 |
|
|
reg [7:0] lambdaReg2_1;
|
| 1185 |
|
|
reg [7:0] lambdaReg2_2;
|
| 1186 |
|
|
reg [7:0] lambdaReg2_3;
|
| 1187 |
|
|
reg [7:0] lambdaReg2_4;
|
| 1188 |
|
|
reg [7:0] lambdaReg2_5;
|
| 1189 |
|
|
reg [7:0] lambdaReg2_6;
|
| 1190 |
|
|
reg [7:0] lambdaReg2_7;
|
| 1191 |
|
|
reg [7:0] lambdaReg2_8;
|
| 1192 |
|
|
reg [7:0] lambdaReg2_9;
|
| 1193 |
|
|
reg [7:0] lambdaReg2_10;
|
| 1194 |
|
|
reg [7:0] lambdaReg2_11;
|
| 1195 |
|
|
reg [7:0] lambdaReg2_12;
|
| 1196 |
|
|
reg [7:0] lambdaReg2_13;
|
| 1197 |
|
|
reg [7:0] lambdaReg2_14;
|
| 1198 |
|
|
reg [7:0] lambdaReg2_15;
|
| 1199 |
|
|
reg [7:0] lambdaReg2_16;
|
| 1200 |
|
|
reg [7:0] lambdaReg2_17;
|
| 1201 |
|
|
reg [7:0] lambdaReg2_18;
|
| 1202 |
|
|
reg [7:0] lambdaReg2_19;
|
| 1203 |
|
|
reg [7:0] lambdaReg2_20;
|
| 1204 |
|
|
reg [7:0] lambdaReg2_21;
|
| 1205 |
|
|
|
| 1206 |
|
|
|
| 1207 |
|
|
always @(posedge CLK or negedge RESET) begin
|
| 1208 |
|
|
if (~RESET) begin
|
| 1209 |
|
|
lambdaReg2_0 [7:0] <= 8'd0;
|
| 1210 |
|
|
lambdaReg2_1 [7:0] <= 8'd0;
|
| 1211 |
|
|
lambdaReg2_2 [7:0] <= 8'd0;
|
| 1212 |
|
|
lambdaReg2_3 [7:0] <= 8'd0;
|
| 1213 |
|
|
lambdaReg2_4 [7:0] <= 8'd0;
|
| 1214 |
|
|
lambdaReg2_5 [7:0] <= 8'd0;
|
| 1215 |
|
|
lambdaReg2_6 [7:0] <= 8'd0;
|
| 1216 |
|
|
lambdaReg2_7 [7:0] <= 8'd0;
|
| 1217 |
|
|
lambdaReg2_8 [7:0] <= 8'd0;
|
| 1218 |
|
|
lambdaReg2_9 [7:0] <= 8'd0;
|
| 1219 |
|
|
lambdaReg2_10 [7:0] <= 8'd0;
|
| 1220 |
|
|
lambdaReg2_11 [7:0] <= 8'd0;
|
| 1221 |
|
|
lambdaReg2_12 [7:0] <= 8'd0;
|
| 1222 |
|
|
lambdaReg2_13 [7:0] <= 8'd0;
|
| 1223 |
|
|
lambdaReg2_14 [7:0] <= 8'd0;
|
| 1224 |
|
|
lambdaReg2_15 [7:0] <= 8'd0;
|
| 1225 |
|
|
lambdaReg2_16 [7:0] <= 8'd0;
|
| 1226 |
|
|
lambdaReg2_17 [7:0] <= 8'd0;
|
| 1227 |
|
|
lambdaReg2_18 [7:0] <= 8'd0;
|
| 1228 |
|
|
lambdaReg2_19 [7:0] <= 8'd0;
|
| 1229 |
|
|
lambdaReg2_20 [7:0] <= 8'd0;
|
| 1230 |
|
|
lambdaReg2_21 [7:0] <= 8'd0;
|
| 1231 |
|
|
end
|
| 1232 |
|
|
else if (enable == 1'b1) begin
|
| 1233 |
|
|
lambdaReg2_0 [7:0] <= lambdaReg_0 [7:0];
|
| 1234 |
|
|
lambdaReg2_1 [7:0] <= lambdaReg_1 [7:0];
|
| 1235 |
|
|
lambdaReg2_2 [7:0] <= lambdaReg_2 [7:0];
|
| 1236 |
|
|
lambdaReg2_3 [7:0] <= lambdaReg_3 [7:0];
|
| 1237 |
|
|
lambdaReg2_4 [7:0] <= lambdaReg_4 [7:0];
|
| 1238 |
|
|
lambdaReg2_5 [7:0] <= lambdaReg_5 [7:0];
|
| 1239 |
|
|
lambdaReg2_6 [7:0] <= lambdaReg_6 [7:0];
|
| 1240 |
|
|
lambdaReg2_7 [7:0] <= lambdaReg_7 [7:0];
|
| 1241 |
|
|
lambdaReg2_8 [7:0] <= lambdaReg_8 [7:0];
|
| 1242 |
|
|
lambdaReg2_9 [7:0] <= lambdaReg_9 [7:0];
|
| 1243 |
|
|
lambdaReg2_10 [7:0] <= lambdaReg_10 [7:0];
|
| 1244 |
|
|
lambdaReg2_11 [7:0] <= lambdaReg_11 [7:0];
|
| 1245 |
|
|
lambdaReg2_12 [7:0] <= lambdaReg_12 [7:0];
|
| 1246 |
|
|
lambdaReg2_13 [7:0] <= lambdaReg_13 [7:0];
|
| 1247 |
|
|
lambdaReg2_14 [7:0] <= lambdaReg_14 [7:0];
|
| 1248 |
|
|
lambdaReg2_15 [7:0] <= lambdaReg_15 [7:0];
|
| 1249 |
|
|
lambdaReg2_16 [7:0] <= lambdaReg_16 [7:0];
|
| 1250 |
|
|
lambdaReg2_17 [7:0] <= lambdaReg_17 [7:0];
|
| 1251 |
|
|
lambdaReg2_18 [7:0] <= lambdaReg_18 [7:0];
|
| 1252 |
|
|
lambdaReg2_19 [7:0] <= lambdaReg_19 [7:0];
|
| 1253 |
|
|
lambdaReg2_20 [7:0] <= lambdaReg_20 [7:0];
|
| 1254 |
|
|
lambdaReg2_21 [7:0] <= lambdaReg_21 [7:0];
|
| 1255 |
|
|
end
|
| 1256 |
|
|
end
|
| 1257 |
|
|
|
| 1258 |
|
|
|
| 1259 |
|
|
|
| 1260 |
|
|
//------------------------------------------------------------------
|
| 1261 |
|
|
// + degreeLambda
|
| 1262 |
|
|
//------------------------------------------------------------------
|
| 1263 |
|
|
wire [4:0] degreeLambda;
|
| 1264 |
|
|
RsDecodeDegree RsDecodeDegree_2(
|
| 1265 |
|
|
// Inputs
|
| 1266 |
|
|
.polynom_0 (lambdaReg2_0),
|
| 1267 |
|
|
.polynom_1 (lambdaReg2_1),
|
| 1268 |
|
|
.polynom_2 (lambdaReg2_2),
|
| 1269 |
|
|
.polynom_3 (lambdaReg2_3),
|
| 1270 |
|
|
.polynom_4 (lambdaReg2_4),
|
| 1271 |
|
|
.polynom_5 (lambdaReg2_5),
|
| 1272 |
|
|
.polynom_6 (lambdaReg2_6),
|
| 1273 |
|
|
.polynom_7 (lambdaReg2_7),
|
| 1274 |
|
|
.polynom_8 (lambdaReg2_8),
|
| 1275 |
|
|
.polynom_9 (lambdaReg2_9),
|
| 1276 |
|
|
.polynom_10 (lambdaReg2_10),
|
| 1277 |
|
|
.polynom_11 (lambdaReg2_11),
|
| 1278 |
|
|
.polynom_12 (lambdaReg2_12),
|
| 1279 |
|
|
.polynom_13 (lambdaReg2_13),
|
| 1280 |
|
|
.polynom_14 (lambdaReg2_14),
|
| 1281 |
|
|
.polynom_15 (lambdaReg2_15),
|
| 1282 |
|
|
.polynom_16 (lambdaReg2_16),
|
| 1283 |
|
|
.polynom_17 (lambdaReg2_17),
|
| 1284 |
|
|
.polynom_18 (lambdaReg2_18),
|
| 1285 |
|
|
.polynom_19 (lambdaReg2_19),
|
| 1286 |
|
|
.polynom_20 (lambdaReg2_20),
|
| 1287 |
|
|
.polynom_21 (lambdaReg2_21),
|
| 1288 |
|
|
// Outputs
|
| 1289 |
|
|
.degree (degreeLambda)
|
| 1290 |
|
|
);
|
| 1291 |
|
|
|
| 1292 |
|
|
|
| 1293 |
|
|
|
| 1294 |
|
|
//------------------------------------------------------------------
|
| 1295 |
|
|
// + degreeOmegaReg
|
| 1296 |
|
|
// + degreeLambdaReg
|
| 1297 |
|
|
//------------------------------------------------------------------
|
| 1298 |
|
|
reg [4:0] degreeOmegaReg;
|
| 1299 |
|
|
reg [4:0] degreeLambdaReg;
|
| 1300 |
|
|
always @(posedge CLK or negedge RESET) begin
|
| 1301 |
|
|
if (~RESET) begin
|
| 1302 |
|
|
degreeOmegaReg <= 5'd0;
|
| 1303 |
|
|
degreeLambdaReg <= 5'd0;
|
| 1304 |
|
|
end
|
| 1305 |
|
|
else if ((enable == 1'b1) && (doneShiftReg == 1'b1)) begin
|
| 1306 |
|
|
degreeOmegaReg <= degreeOmega;
|
| 1307 |
|
|
degreeLambdaReg <= degreeLambda;
|
| 1308 |
|
|
end
|
| 1309 |
|
|
end
|
| 1310 |
|
|
|
| 1311 |
|
|
|
| 1312 |
|
|
|
| 1313 |
|
|
//------------------------------------------------------------------
|
| 1314 |
|
|
// + doneShiftReg
|
| 1315 |
|
|
//------------------------------------------------------------------
|
| 1316 |
|
|
always @(posedge CLK or negedge RESET) begin
|
| 1317 |
|
|
if (~RESET) begin
|
| 1318 |
|
|
doneShiftReg <= 1'b0;
|
| 1319 |
|
|
end
|
| 1320 |
|
|
else if (enable == 1'b1) begin
|
| 1321 |
|
|
doneShiftReg <= doneShift;
|
| 1322 |
|
|
end
|
| 1323 |
|
|
end
|
| 1324 |
|
|
|
| 1325 |
|
|
|
| 1326 |
|
|
|
| 1327 |
|
|
//------------------------------------------------------------------
|
| 1328 |
|
|
// +
|
| 1329 |
|
|
//- RS Chien Search Algorithm
|
| 1330 |
|
|
//------------------------------------------------------------------
|
| 1331 |
|
|
wire [4:0] numErrorChien;
|
| 1332 |
|
|
wire [7:0] error;
|
| 1333 |
|
|
wire delayedErasureIn;
|
| 1334 |
|
|
|
| 1335 |
|
|
|
| 1336 |
|
|
RsDecodeChien RsDecodeChien(
|
| 1337 |
|
|
// Inputs
|
| 1338 |
|
|
.CLK (CLK),
|
| 1339 |
|
|
.RESET (RESET),
|
| 1340 |
|
|
.enable (enable),
|
| 1341 |
|
|
.sync (doneShiftReg),
|
| 1342 |
|
|
.erasureIn (delayedErasureIn),
|
| 1343 |
|
|
.lambdaIn_0 (lambdaReg2_0),
|
| 1344 |
|
|
.lambdaIn_1 (lambdaReg2_1),
|
| 1345 |
|
|
.lambdaIn_2 (lambdaReg2_2),
|
| 1346 |
|
|
.lambdaIn_3 (lambdaReg2_3),
|
| 1347 |
|
|
.lambdaIn_4 (lambdaReg2_4),
|
| 1348 |
|
|
.lambdaIn_5 (lambdaReg2_5),
|
| 1349 |
|
|
.lambdaIn_6 (lambdaReg2_6),
|
| 1350 |
|
|
.lambdaIn_7 (lambdaReg2_7),
|
| 1351 |
|
|
.lambdaIn_8 (lambdaReg2_8),
|
| 1352 |
|
|
.lambdaIn_9 (lambdaReg2_9),
|
| 1353 |
|
|
.lambdaIn_10 (lambdaReg2_10),
|
| 1354 |
|
|
.lambdaIn_11 (lambdaReg2_11),
|
| 1355 |
|
|
.lambdaIn_12 (lambdaReg2_12),
|
| 1356 |
|
|
.lambdaIn_13 (lambdaReg2_13),
|
| 1357 |
|
|
.lambdaIn_14 (lambdaReg2_14),
|
| 1358 |
|
|
.lambdaIn_15 (lambdaReg2_15),
|
| 1359 |
|
|
.lambdaIn_16 (lambdaReg2_16),
|
| 1360 |
|
|
.lambdaIn_17 (lambdaReg2_17),
|
| 1361 |
|
|
.lambdaIn_18 (lambdaReg2_18),
|
| 1362 |
|
|
.lambdaIn_19 (lambdaReg2_19),
|
| 1363 |
|
|
.lambdaIn_20 (lambdaReg2_20),
|
| 1364 |
|
|
.lambdaIn_21 (lambdaReg2_21),
|
| 1365 |
|
|
.omegaIn_0 (omegaShiftedReg_0),
|
| 1366 |
|
|
.omegaIn_1 (omegaShiftedReg_1),
|
| 1367 |
|
|
.omegaIn_2 (omegaShiftedReg_2),
|
| 1368 |
|
|
.omegaIn_3 (omegaShiftedReg_3),
|
| 1369 |
|
|
.omegaIn_4 (omegaShiftedReg_4),
|
| 1370 |
|
|
.omegaIn_5 (omegaShiftedReg_5),
|
| 1371 |
|
|
.omegaIn_6 (omegaShiftedReg_6),
|
| 1372 |
|
|
.omegaIn_7 (omegaShiftedReg_7),
|
| 1373 |
|
|
.omegaIn_8 (omegaShiftedReg_8),
|
| 1374 |
|
|
.omegaIn_9 (omegaShiftedReg_9),
|
| 1375 |
|
|
.omegaIn_10 (omegaShiftedReg_10),
|
| 1376 |
|
|
.omegaIn_11 (omegaShiftedReg_11),
|
| 1377 |
|
|
.omegaIn_12 (omegaShiftedReg_12),
|
| 1378 |
|
|
.omegaIn_13 (omegaShiftedReg_13),
|
| 1379 |
|
|
.omegaIn_14 (omegaShiftedReg_14),
|
| 1380 |
|
|
.omegaIn_15 (omegaShiftedReg_15),
|
| 1381 |
|
|
.omegaIn_16 (omegaShiftedReg_16),
|
| 1382 |
|
|
.omegaIn_17 (omegaShiftedReg_17),
|
| 1383 |
|
|
.omegaIn_18 (omegaShiftedReg_18),
|
| 1384 |
|
|
.omegaIn_19 (omegaShiftedReg_19),
|
| 1385 |
|
|
.omegaIn_20 (omegaShiftedReg_20),
|
| 1386 |
|
|
.omegaIn_21 (omegaShiftedReg_21),
|
| 1387 |
|
|
.epsilonIn_0 (epsilonReg3_0),
|
| 1388 |
|
|
.epsilonIn_1 (epsilonReg3_1),
|
| 1389 |
|
|
.epsilonIn_2 (epsilonReg3_2),
|
| 1390 |
|
|
.epsilonIn_3 (epsilonReg3_3),
|
| 1391 |
|
|
.epsilonIn_4 (epsilonReg3_4),
|
| 1392 |
|
|
.epsilonIn_5 (epsilonReg3_5),
|
| 1393 |
|
|
.epsilonIn_6 (epsilonReg3_6),
|
| 1394 |
|
|
.epsilonIn_7 (epsilonReg3_7),
|
| 1395 |
|
|
.epsilonIn_8 (epsilonReg3_8),
|
| 1396 |
|
|
.epsilonIn_9 (epsilonReg3_9),
|
| 1397 |
|
|
.epsilonIn_10 (epsilonReg3_10),
|
| 1398 |
|
|
.epsilonIn_11 (epsilonReg3_11),
|
| 1399 |
|
|
.epsilonIn_12 (epsilonReg3_12),
|
| 1400 |
|
|
.epsilonIn_13 (epsilonReg3_13),
|
| 1401 |
|
|
.epsilonIn_14 (epsilonReg3_14),
|
| 1402 |
|
|
.epsilonIn_15 (epsilonReg3_15),
|
| 1403 |
|
|
.epsilonIn_16 (epsilonReg3_16),
|
| 1404 |
|
|
.epsilonIn_17 (epsilonReg3_17),
|
| 1405 |
|
|
.epsilonIn_18 (epsilonReg3_18),
|
| 1406 |
|
|
.epsilonIn_19 (epsilonReg3_19),
|
| 1407 |
|
|
.epsilonIn_20 (epsilonReg3_20),
|
| 1408 |
|
|
.epsilonIn_21 (epsilonReg3_21),
|
| 1409 |
|
|
.epsilonIn_22 (epsilonReg3_22),
|
| 1410 |
|
|
// Outputs
|
| 1411 |
|
|
.errorOut (error),
|
| 1412 |
|
|
.numError (numErrorChien),
|
| 1413 |
|
|
.done (doneChien)
|
| 1414 |
|
|
);
|
| 1415 |
|
|
|
| 1416 |
|
|
|
| 1417 |
|
|
|
| 1418 |
|
|
//------------------------------------------------------------------
|
| 1419 |
|
|
// + delayOut
|
| 1420 |
|
|
//- Rs Decode Delay
|
| 1421 |
|
|
//------------------------------------------------------------------
|
| 1422 |
|
|
wire [8:0] delayOut;
|
| 1423 |
|
|
wire [8:0] delayIn;
|
| 1424 |
|
|
|
| 1425 |
|
|
|
| 1426 |
|
|
RsDecodeDelay RsDecodeDelay(
|
| 1427 |
|
|
// Inputs
|
| 1428 |
|
|
.CLK (CLK),
|
| 1429 |
|
|
.RESET (RESET),
|
| 1430 |
|
|
.enable (enable),
|
| 1431 |
|
|
.dataIn (delayIn),
|
| 1432 |
|
|
// Outputs
|
| 1433 |
|
|
.dataOut (delayOut)
|
| 1434 |
|
|
);
|
| 1435 |
|
|
|
| 1436 |
|
|
|
| 1437 |
|
|
|
| 1438 |
|
|
//------------------------------------------------------------------
|
| 1439 |
|
|
// + delayIn, delayedErasureIn, delayedDataIn
|
| 1440 |
|
|
//------------------------------------------------------------------
|
| 1441 |
|
|
wire [7:0] delayedDataIn;
|
| 1442 |
|
|
assign delayIn = {erasureIn, dataInCheck};
|
| 1443 |
|
|
assign delayedErasureIn = delayOut[8];
|
| 1444 |
|
|
assign delayedDataIn = delayOut[7:0];
|
| 1445 |
|
|
|
| 1446 |
|
|
|
| 1447 |
|
|
|
| 1448 |
|
|
//------------------------------------------------------------------------
|
| 1449 |
|
|
// + OutputValidReg
|
| 1450 |
|
|
//------------------------------------------------------------------------
|
| 1451 |
|
|
reg OutputValidReg;
|
| 1452 |
|
|
reg [3:0] startReg;
|
| 1453 |
|
|
|
| 1454 |
|
|
always @(posedge CLK or negedge RESET) begin
|
| 1455 |
|
|
if (~RESET) begin
|
| 1456 |
|
|
OutputValidReg <= 1'b0;
|
| 1457 |
|
|
end
|
| 1458 |
|
|
else if (enable == 1'b1) begin
|
| 1459 |
|
|
if (startReg[1] == 1'b1) begin
|
| 1460 |
|
|
OutputValidReg <= 1'b1;
|
| 1461 |
|
|
end
|
| 1462 |
|
|
else if (doneReg[0] == 1'b1) begin
|
| 1463 |
|
|
OutputValidReg <= 1'b0;
|
| 1464 |
|
|
end
|
| 1465 |
|
|
end
|
| 1466 |
|
|
end
|
| 1467 |
|
|
|
| 1468 |
|
|
|
| 1469 |
|
|
|
| 1470 |
|
|
//------------------------------------------------------------------
|
| 1471 |
|
|
// + startReg, doneReg
|
| 1472 |
|
|
//------------------------------------------------------------------
|
| 1473 |
|
|
always @(posedge CLK or negedge RESET) begin
|
| 1474 |
|
|
if (~RESET) begin
|
| 1475 |
|
|
startReg [3:0] <= 4'd0;
|
| 1476 |
|
|
doneReg [2:0] <= 3'd0;
|
| 1477 |
|
|
end
|
| 1478 |
|
|
else if (enable == 1'b1) begin
|
| 1479 |
|
|
startReg [3:0] <= {doneShiftReg, startReg[3:1]};
|
| 1480 |
|
|
doneReg [2:0] <= {doneChien, doneReg[2:1]};
|
| 1481 |
|
|
end
|
| 1482 |
|
|
end
|
| 1483 |
|
|
|
| 1484 |
|
|
|
| 1485 |
|
|
|
| 1486 |
|
|
//------------------------------------------------------------------
|
| 1487 |
|
|
// + numErrorLambdaReg
|
| 1488 |
|
|
//------------------------------------------------------------------
|
| 1489 |
|
|
reg [4:0] numErrorLambdaReg;
|
| 1490 |
|
|
always @(posedge CLK or negedge RESET) begin
|
| 1491 |
|
|
if (~RESET) begin
|
| 1492 |
|
|
numErrorLambdaReg [4:0] <= 5'd0;
|
| 1493 |
|
|
end
|
| 1494 |
|
|
else if ((enable == 1'b1) && (startReg[1] == 1'b1)) begin
|
| 1495 |
|
|
numErrorLambdaReg <= degreeLambdaReg;
|
| 1496 |
|
|
end
|
| 1497 |
|
|
end
|
| 1498 |
|
|
|
| 1499 |
|
|
|
| 1500 |
|
|
|
| 1501 |
|
|
//------------------------------------------------------------------
|
| 1502 |
|
|
// + degreeErrorReg
|
| 1503 |
|
|
//------------------------------------------------------------------
|
| 1504 |
|
|
reg degreeErrorReg;
|
| 1505 |
|
|
always @(posedge CLK or negedge RESET) begin
|
| 1506 |
|
|
if (~RESET) begin
|
| 1507 |
|
|
degreeErrorReg <= 1'b0;
|
| 1508 |
|
|
end
|
| 1509 |
|
|
else if ((enable == 1'b1) && (startReg[1] == 1'b1)) begin
|
| 1510 |
|
|
if (({1'b0, degreeOmegaReg}) <= ({1'b0, degreeLambdaReg}) + ({1'b0, degreeEpsilonReg4})) begin
|
| 1511 |
|
|
degreeErrorReg <= 1'b0;
|
| 1512 |
|
|
end
|
| 1513 |
|
|
else begin
|
| 1514 |
|
|
degreeErrorReg <= 1'b1;
|
| 1515 |
|
|
end
|
| 1516 |
|
|
end
|
| 1517 |
|
|
end
|
| 1518 |
|
|
|
| 1519 |
|
|
|
| 1520 |
|
|
|
| 1521 |
|
|
//------------------------------------------------------------------
|
| 1522 |
|
|
// + numErrorReg
|
| 1523 |
|
|
//------------------------------------------------------------------
|
| 1524 |
|
|
reg [4:0] numErrorReg;
|
| 1525 |
|
|
always @(posedge CLK or negedge RESET) begin
|
| 1526 |
|
|
if (~RESET) begin
|
| 1527 |
|
|
numErrorReg [4:0] <= 5'd0;
|
| 1528 |
|
|
end
|
| 1529 |
|
|
else if ((enable == 1'b1) && (doneReg[0] == 1'b1)) begin
|
| 1530 |
|
|
numErrorReg [4:0] <= numErrorChien[4:0];
|
| 1531 |
|
|
end
|
| 1532 |
|
|
end
|
| 1533 |
|
|
|
| 1534 |
|
|
|
| 1535 |
|
|
|
| 1536 |
|
|
//------------------------------------------------------------------
|
| 1537 |
|
|
// + failErasureReg
|
| 1538 |
|
|
//-
|
| 1539 |
|
|
//------------------------------------------------------------------
|
| 1540 |
|
|
reg failErasureReg;
|
| 1541 |
|
|
always @(posedge CLK or negedge RESET) begin
|
| 1542 |
|
|
if (~RESET) begin
|
| 1543 |
|
|
failErasureReg <= 1'b0;
|
| 1544 |
|
|
end
|
| 1545 |
|
|
else if ((enable == 1'b1) && (doneErasure == 1'b1)) begin
|
| 1546 |
|
|
failErasureReg <= failErasure;
|
| 1547 |
|
|
end
|
| 1548 |
|
|
end
|
| 1549 |
|
|
|
| 1550 |
|
|
|
| 1551 |
|
|
|
| 1552 |
|
|
//------------------------------------------------------------------
|
| 1553 |
|
|
// + failErasureReg2
|
| 1554 |
|
|
//-
|
| 1555 |
|
|
//------------------------------------------------------------------
|
| 1556 |
|
|
reg failErasureReg2;
|
| 1557 |
|
|
always @(posedge CLK or negedge RESET) begin
|
| 1558 |
|
|
if (~RESET) begin
|
| 1559 |
|
|
failErasureReg2 <= 1'b0;
|
| 1560 |
|
|
end
|
| 1561 |
|
|
else if ((enable == 1'b1) && (donePolymul == 1'b1)) begin
|
| 1562 |
|
|
failErasureReg2 <= failErasureReg;
|
| 1563 |
|
|
end
|
| 1564 |
|
|
end
|
| 1565 |
|
|
|
| 1566 |
|
|
|
| 1567 |
|
|
|
| 1568 |
|
|
//------------------------------------------------------------------
|
| 1569 |
|
|
// + failErasureReg3
|
| 1570 |
|
|
//-
|
| 1571 |
|
|
//------------------------------------------------------------------
|
| 1572 |
|
|
reg failErasureReg3;
|
| 1573 |
|
|
always @(posedge CLK or negedge RESET) begin
|
| 1574 |
|
|
if (~RESET) begin
|
| 1575 |
|
|
failErasureReg3 <= 1'b0;
|
| 1576 |
|
|
end
|
| 1577 |
|
|
else if ((enable == 1'b1) && (doneEuclide == 1'b1)) begin
|
| 1578 |
|
|
failErasureReg3 <= failErasureReg2;
|
| 1579 |
|
|
end
|
| 1580 |
|
|
end
|
| 1581 |
|
|
|
| 1582 |
|
|
|
| 1583 |
|
|
|
| 1584 |
|
|
//------------------------------------------------------------------
|
| 1585 |
|
|
// + failErasureReg4
|
| 1586 |
|
|
//-
|
| 1587 |
|
|
//------------------------------------------------------------------
|
| 1588 |
|
|
reg failErasureReg4;
|
| 1589 |
|
|
always @(posedge CLK or negedge RESET) begin
|
| 1590 |
|
|
if (~RESET) begin
|
| 1591 |
|
|
failErasureReg4 <= 1'b0;
|
| 1592 |
|
|
end
|
| 1593 |
|
|
else if ((enable == 1'b1) && (doneShiftReg == 1'b1)) begin
|
| 1594 |
|
|
failErasureReg4 <= failErasureReg3;
|
| 1595 |
|
|
end
|
| 1596 |
|
|
end
|
| 1597 |
|
|
|
| 1598 |
|
|
|
| 1599 |
|
|
|
| 1600 |
|
|
//------------------------------------------------------------------
|
| 1601 |
|
|
// + failErasureReg5
|
| 1602 |
|
|
//-
|
| 1603 |
|
|
//------------------------------------------------------------------
|
| 1604 |
|
|
reg failErasureReg5;
|
| 1605 |
|
|
always @(posedge CLK or negedge RESET) begin
|
| 1606 |
|
|
if (~RESET) begin
|
| 1607 |
|
|
failErasureReg5 <= 1'b0;
|
| 1608 |
|
|
end
|
| 1609 |
|
|
else if ((enable == 1'b1) && (startReg[1] == 1'b1)) begin
|
| 1610 |
|
|
failErasureReg5 <= failErasureReg4;
|
| 1611 |
|
|
end
|
| 1612 |
|
|
end
|
| 1613 |
|
|
|
| 1614 |
|
|
|
| 1615 |
|
|
|
| 1616 |
|
|
//------------------------------------------------------------------
|
| 1617 |
|
|
// + failReg
|
| 1618 |
|
|
//------------------------------------------------------------------
|
| 1619 |
|
|
reg failReg;
|
| 1620 |
|
|
|
| 1621 |
|
|
always @(posedge CLK or negedge RESET) begin
|
| 1622 |
|
|
if (~RESET) begin
|
| 1623 |
|
|
failReg <= 1'b0;
|
| 1624 |
|
|
end
|
| 1625 |
|
|
else if ((enable == 1'b1) && (doneReg[0] == 1'b1)) begin
|
| 1626 |
|
|
if ((numErrorLambdaReg == numErrorChien) && (degreeErrorReg == 1'b0) && (failErasureReg5 == 1'b0)) begin
|
| 1627 |
|
|
failReg <= 1'b0;
|
| 1628 |
|
|
end
|
| 1629 |
|
|
else begin
|
| 1630 |
|
|
failReg <= 1'b1;
|
| 1631 |
|
|
end
|
| 1632 |
|
|
end
|
| 1633 |
|
|
end
|
| 1634 |
|
|
|
| 1635 |
|
|
|
| 1636 |
|
|
|
| 1637 |
|
|
//------------------------------------------------------------------
|
| 1638 |
|
|
// + DataOutInner
|
| 1639 |
|
|
//------------------------------------------------------------------
|
| 1640 |
|
|
reg [7:0] DataOutInner;
|
| 1641 |
|
|
always @(posedge CLK or negedge RESET) begin
|
| 1642 |
|
|
if (~RESET) begin
|
| 1643 |
|
|
DataOutInner <= 8'd0;
|
| 1644 |
|
|
end
|
| 1645 |
|
|
else begin
|
| 1646 |
|
|
DataOutInner <= delayedDataIn ^ error;
|
| 1647 |
|
|
end
|
| 1648 |
|
|
end
|
| 1649 |
|
|
|
| 1650 |
|
|
|
| 1651 |
|
|
|
| 1652 |
|
|
//------------------------------------------------------------------
|
| 1653 |
|
|
// + DelayedDataOutInner
|
| 1654 |
|
|
//------------------------------------------------------------------
|
| 1655 |
|
|
reg [7:0] DelayedDataOutInner;
|
| 1656 |
|
|
always @(posedge CLK or negedge RESET) begin
|
| 1657 |
|
|
if (~RESET) begin
|
| 1658 |
|
|
DelayedDataOutInner <= 8'd0;
|
| 1659 |
|
|
end
|
| 1660 |
|
|
else begin
|
| 1661 |
|
|
DelayedDataOutInner <= delayedDataIn;
|
| 1662 |
|
|
end
|
| 1663 |
|
|
end
|
| 1664 |
|
|
|
| 1665 |
|
|
|
| 1666 |
|
|
|
| 1667 |
|
|
//------------------------------------------------------------------
|
| 1668 |
|
|
// - enableFF
|
| 1669 |
|
|
//------------------------------------------------------------------
|
| 1670 |
|
|
reg enableFF;
|
| 1671 |
|
|
|
| 1672 |
|
|
|
| 1673 |
|
|
always @(posedge CLK or negedge RESET) begin
|
| 1674 |
|
|
if (~RESET) begin
|
| 1675 |
|
|
enableFF <= 1'b0;
|
| 1676 |
|
|
end
|
| 1677 |
|
|
else begin
|
| 1678 |
|
|
enableFF <= enable;
|
| 1679 |
|
|
end
|
| 1680 |
|
|
end
|
| 1681 |
|
|
|
| 1682 |
|
|
|
| 1683 |
|
|
|
| 1684 |
|
|
//------------------------------------------------------------------
|
| 1685 |
|
|
// - FF for Outputs
|
| 1686 |
|
|
//------------------------------------------------------------------
|
| 1687 |
|
|
reg startRegInner;
|
| 1688 |
|
|
reg doneRegInner;
|
| 1689 |
|
|
reg [7:0] numErrorRegInner;
|
| 1690 |
|
|
reg [7:0] numErasureRegInner;
|
| 1691 |
|
|
reg failRegInner;
|
| 1692 |
|
|
|
| 1693 |
|
|
|
| 1694 |
|
|
always @(posedge CLK or negedge RESET) begin
|
| 1695 |
|
|
if (~RESET) begin
|
| 1696 |
|
|
startRegInner <= 1'b0;
|
| 1697 |
|
|
doneRegInner <= 1'b0;
|
| 1698 |
|
|
numErrorRegInner <= 8'd0;
|
| 1699 |
|
|
numErasureRegInner <= 8'd0;
|
| 1700 |
|
|
failRegInner <= 1'b0;
|
| 1701 |
|
|
end
|
| 1702 |
|
|
else begin
|
| 1703 |
|
|
startRegInner <= startReg[0];
|
| 1704 |
|
|
doneRegInner <= doneReg[0];
|
| 1705 |
|
|
numErrorRegInner <= { 3'd0, numErrorReg[4:0]};
|
| 1706 |
|
|
numErasureRegInner <= { 3'd0, numErasureReg[4:0]};
|
| 1707 |
|
|
failRegInner <= failReg;
|
| 1708 |
|
|
end
|
| 1709 |
|
|
end
|
| 1710 |
|
|
|
| 1711 |
|
|
|
| 1712 |
|
|
|
| 1713 |
|
|
//------------------------------------------------------------------
|
| 1714 |
|
|
// - OutputValidRegInner
|
| 1715 |
|
|
//------------------------------------------------------------------
|
| 1716 |
|
|
reg OutputValidRegInner;
|
| 1717 |
|
|
|
| 1718 |
|
|
always @(posedge CLK or negedge RESET) begin
|
| 1719 |
|
|
if (~RESET) begin
|
| 1720 |
|
|
OutputValidRegInner <= 1'b0;
|
| 1721 |
|
|
end
|
| 1722 |
|
|
else if (enableFF == 1'b1) begin
|
| 1723 |
|
|
OutputValidRegInner <= OutputValidReg;
|
| 1724 |
|
|
end
|
| 1725 |
|
|
else begin
|
| 1726 |
|
|
OutputValidRegInner <= 1'b0;
|
| 1727 |
|
|
end
|
| 1728 |
|
|
end
|
| 1729 |
|
|
|
| 1730 |
|
|
|
| 1731 |
|
|
|
| 1732 |
|
|
//------------------------------------------------------------------
|
| 1733 |
|
|
// - Output Ports
|
| 1734 |
|
|
//------------------------------------------------------------------
|
| 1735 |
|
|
assign outEnable = OutputValidRegInner;
|
| 1736 |
|
|
assign outStartPls = startRegInner;
|
| 1737 |
|
|
assign outDone = doneRegInner;
|
| 1738 |
|
|
assign outData = DataOutInner;
|
| 1739 |
|
|
assign errorNum = numErrorRegInner;
|
| 1740 |
|
|
assign erasureNum = numErasureRegInner;
|
| 1741 |
|
|
assign delayedData = DelayedDataOutInner;
|
| 1742 |
|
|
assign fail = failRegInner;
|
| 1743 |
|
|
|
| 1744 |
|
|
|
| 1745 |
|
|
endmodule
|
