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[/] [reed_solomon_codec_generator/] [trunk/] [example/] [rtl/] [RsEncodeTop.v] - Blame information for rev 4

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1 4 issei 
//===================================================================
2 
// Module Name : RsEncodeTop
3 
// File Name   : RsEncodeTop.v
4 
// Function    : Rs Encoder Top Module
5 
//
6 
// Revision History:
7 
// Date          By           Version    Change Description
8 
//===================================================================
9 
// 2009/02/03  Gael Sapience     1.0       Original
10 
//
11 
//===================================================================
12 
// (C) COPYRIGHT 2009 SYSTEM LSI CO., Ltd.
13 
//
14 
 
15 
 
16 
module RsEncodeTop(
17 
   CLK,        // system clock
18 
   RESET,      // system reset
19 
   enable,     // rs encoder enable signal
20 
   startPls,   // rs encoder sync signal
21 
   dataIn,     // rs encoder data in
22 
   dataOut     // rs encoder data out
23 
);
24 
 
25 
 
26 
   input          CLK;        // system clock
27 
   input          RESET;      // system reset
28 
   input          enable;     // rs encoder enable signal
29 
   input          startPls;   // rs encoder sync signal
30 
   input  [7:0]   dataIn;     // rs encoder data in
31 
   output [7:0]   dataOut;    // rs encoder data out
32 
 
33 
 
34 
 
35 
   //---------------------------------------------------------------
36 
   //- registers
37 
   //---------------------------------------------------------------
38 
   reg  [7:0]   count;
39 
   reg          dataValid;
40 
   reg  [7:0]   feedbackReg;
41 
   wire [7:0]   mult_0;
42 
   wire [7:0]   mult_1;
43 
   wire [7:0]   mult_2;
44 
   wire [7:0]   mult_3;
45 
   wire [7:0]   mult_4;
46 
   wire [7:0]   mult_5;
47 
   wire [7:0]   mult_6;
48 
   wire [7:0]   mult_7;
49 
   wire [7:0]   mult_8;
50 
   wire [7:0]   mult_9;
51 
   wire [7:0]   mult_10;
52 
   wire [7:0]   mult_11;
53 
   wire [7:0]   mult_12;
54 
   wire [7:0]   mult_13;
55 
   wire [7:0]   mult_14;
56 
   wire [7:0]   mult_15;
57 
   wire [7:0]   mult_16;
58 
   wire [7:0]   mult_17;
59 
   wire [7:0]   mult_18;
60 
   wire [7:0]   mult_19;
61 
   wire [7:0]   mult_20;
62 
   wire [7:0]   mult_21;
63 
   reg  [7:0]   syndromeReg_0;
64 
   reg  [7:0]   syndromeReg_1;
65 
   reg  [7:0]   syndromeReg_2;
66 
   reg  [7:0]   syndromeReg_3;
67 
   reg  [7:0]   syndromeReg_4;
68 
   reg  [7:0]   syndromeReg_5;
69 
   reg  [7:0]   syndromeReg_6;
70 
   reg  [7:0]   syndromeReg_7;
71 
   reg  [7:0]   syndromeReg_8;
72 
   reg  [7:0]   syndromeReg_9;
73 
   reg  [7:0]   syndromeReg_10;
74 
   reg  [7:0]   syndromeReg_11;
75 
   reg  [7:0]   syndromeReg_12;
76 
   reg  [7:0]   syndromeReg_13;
77 
   reg  [7:0]   syndromeReg_14;
78 
   reg  [7:0]   syndromeReg_15;
79 
   reg  [7:0]   syndromeReg_16;
80 
   reg  [7:0]   syndromeReg_17;
81 
   reg  [7:0]   syndromeReg_18;
82 
   reg  [7:0]   syndromeReg_19;
83 
   reg  [7:0]   syndromeReg_20;
84 
   reg  [7:0]   syndromeReg_21;
85 
   reg  [7:0]   dataReg;
86 
   reg  [7:0]   syndromeRegFF;
87 
   reg  [7:0]   wireOut;
88 
 
89 
 
90 
 
91 
   //---------------------------------------------------------------
92 
   //- count
93 
   //---------------------------------------------------------------
94 
   always @(posedge CLK or negedge RESET) begin
95 
      if (~RESET) begin
96 
         count [7:0] <= 8'd0;
97 
      end
98 
      else if (enable == 1'b1) begin
99 
         if (startPls == 1'b1) begin
100 
            count[7:0] <= 8'd1;
101 
         end
102 
         else if ((count[7:0] ==8'd0) || (count[7:0] ==8'd255)) begin
103 
            count[7:0] <= 8'd0;
104 
         end
105 
         else begin
106 
            count[7:0] <= count[7:0] + 8'd1;
107 
         end
108 
      end
109 
   end
110 
 
111 
 
112 
 
113 
   //---------------------------------------------------------------
114 
   //- dataValid
115 
   //---------------------------------------------------------------
116 
   always @(count or startPls) begin
117 
      if (startPls == 1'b1 || (count[7:0] < 8'd233)) begin
118 
         dataValid = 1'b1;
119 
      end
120 
      else begin
121 
         dataValid = 1'b0;
122 
      end
123 
   end
124 
 
125 
 
126 
 
127 
 
128 
   //---------------------------------------------------------------
129 
   //- Multipliers
130 
   //---------------------------------------------------------------
131 
   assign mult_9[0] =  feedbackReg[0] ^ feedbackReg[4] ^ feedbackReg[5] ^ feedbackReg[6];
132 
   assign mult_9[1] =  feedbackReg[1] ^ feedbackReg[5] ^ feedbackReg[6] ^ feedbackReg[7];
133 
   assign mult_9[2] =  feedbackReg[0] ^ feedbackReg[2] ^ feedbackReg[4] ^ feedbackReg[5] ^ feedbackReg[7];
134 
   assign mult_9[3] =  feedbackReg[0] ^ feedbackReg[1] ^ feedbackReg[3] ^ feedbackReg[4];
135 
   assign mult_9[4] =  feedbackReg[0] ^ feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[6];
136 
   assign mult_9[5] =  feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[7];
137 
   assign mult_9[6] =  feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[4];
138 
   assign mult_9[7] =  feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[5];
139 
   assign mult_15[0] =  feedbackReg[0] ^ feedbackReg[4] ^ feedbackReg[7];
140 
   assign mult_15[1] =  feedbackReg[0] ^ feedbackReg[1] ^ feedbackReg[5];
141 
   assign mult_15[2] =  feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[4] ^ feedbackReg[6] ^ feedbackReg[7];
142 
   assign mult_15[3] =  feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[5];
143 
   assign mult_15[4] =  feedbackReg[0] ^ feedbackReg[3] ^ feedbackReg[5] ^ feedbackReg[6] ^ feedbackReg[7];
144 
   assign mult_15[5] =  feedbackReg[1] ^ feedbackReg[4] ^ feedbackReg[6] ^ feedbackReg[7];
145 
   assign mult_15[6] =  feedbackReg[2] ^ feedbackReg[5] ^ feedbackReg[7];
146 
   assign mult_15[7] =  feedbackReg[3] ^ feedbackReg[6];
147 
   assign mult_12[0] =  feedbackReg[3] ^ feedbackReg[5] ^ feedbackReg[7];
148 
   assign mult_12[1] =  feedbackReg[4] ^ feedbackReg[6];
149 
   assign mult_12[2] =  feedbackReg[3];
150 
   assign mult_12[3] =  feedbackReg[0] ^ feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[5] ^ feedbackReg[7];
151 
   assign mult_12[4] =  feedbackReg[1] ^ feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[6] ^ feedbackReg[7];
152 
   assign mult_12[5] =  feedbackReg[0] ^ feedbackReg[2] ^ feedbackReg[4] ^ feedbackReg[5] ^ feedbackReg[7];
153 
   assign mult_12[6] =  feedbackReg[1] ^ feedbackReg[3] ^ feedbackReg[5] ^ feedbackReg[6];
154 
   assign mult_12[7] =  feedbackReg[2] ^ feedbackReg[4] ^ feedbackReg[6] ^ feedbackReg[7];
155 
   assign mult_10[0] =  feedbackReg[0] ^ feedbackReg[1] ^ feedbackReg[6] ^ feedbackReg[7];
156 
   assign mult_10[1] =  feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[7];
157 
   assign mult_10[2] =  feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[6] ^ feedbackReg[7];
158 
   assign mult_10[3] =  feedbackReg[0] ^ feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[6];
159 
   assign mult_10[4] =  feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[5] ^ feedbackReg[6];
160 
   assign mult_10[5] =  feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[5] ^ feedbackReg[6] ^ feedbackReg[7];
161 
   assign mult_10[6] =  feedbackReg[4] ^ feedbackReg[5] ^ feedbackReg[6] ^ feedbackReg[7];
162 
   assign mult_10[7] =  feedbackReg[0] ^ feedbackReg[5] ^ feedbackReg[6] ^ feedbackReg[7];
163 
   assign mult_6[0] =  feedbackReg[0] ^ feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[6] ^ feedbackReg[7];
164 
   assign mult_6[1] =  feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[5] ^ feedbackReg[7];
165 
   assign mult_6[2] =  feedbackReg[0] ^ feedbackReg[1] ^ feedbackReg[5] ^ feedbackReg[7];
166 
   assign mult_6[3] =  feedbackReg[0] ^ feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[7];
167 
   assign mult_6[4] =  feedbackReg[0] ^ feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[5] ^ feedbackReg[6] ^ feedbackReg[7];
168 
   assign mult_6[5] =  feedbackReg[0] ^ feedbackReg[1] ^ feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[6] ^ feedbackReg[7];
169 
   assign mult_6[6] =  feedbackReg[0] ^ feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[4] ^ feedbackReg[5] ^ feedbackReg[7];
170 
   assign mult_6[7] =  feedbackReg[0] ^ feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[5] ^ feedbackReg[6];
171 
   assign mult_17[0] =  feedbackReg[1] ^ feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[5] ^ feedbackReg[7];
172 
   assign mult_17[1] =  feedbackReg[0] ^ feedbackReg[2] ^ feedbackReg[4] ^ feedbackReg[5] ^ feedbackReg[6];
173 
   assign mult_17[2] =  feedbackReg[0] ^ feedbackReg[4] ^ feedbackReg[6];
174 
   assign mult_17[3] =  feedbackReg[3] ^ feedbackReg[4];
175 
   assign mult_17[4] =  feedbackReg[0] ^ feedbackReg[1] ^ feedbackReg[3] ^ feedbackReg[7];
176 
   assign mult_17[5] =  feedbackReg[0] ^ feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[4];
177 
   assign mult_17[6] =  feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[5];
178 
   assign mult_17[7] =  feedbackReg[0] ^ feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[6];
179 
   assign mult_7[0] =  feedbackReg[0] ^ feedbackReg[2] ^ feedbackReg[6];
180 
   assign mult_7[1] =  feedbackReg[0] ^ feedbackReg[1] ^ feedbackReg[3] ^ feedbackReg[7];
181 
   assign mult_7[2] =  feedbackReg[1] ^ feedbackReg[4] ^ feedbackReg[6];
182 
   assign mult_7[3] =  feedbackReg[5] ^ feedbackReg[6] ^ feedbackReg[7];
183 
   assign mult_7[4] =  feedbackReg[2] ^ feedbackReg[7];
184 
   assign mult_7[5] =  feedbackReg[3];
185 
   assign mult_7[6] =  feedbackReg[0] ^ feedbackReg[4];
186 
   assign mult_7[7] =  feedbackReg[1] ^ feedbackReg[5];
187 
   assign mult_2[0] =  feedbackReg[4] ^ feedbackReg[5] ^ feedbackReg[7];
188 
   assign mult_2[1] =  feedbackReg[0] ^ feedbackReg[5] ^ feedbackReg[6];
189 
   assign mult_2[2] =  feedbackReg[1] ^ feedbackReg[4] ^ feedbackReg[5] ^ feedbackReg[6];
190 
   assign mult_2[3] =  feedbackReg[0] ^ feedbackReg[2] ^ feedbackReg[4] ^ feedbackReg[6];
191 
   assign mult_2[4] =  feedbackReg[0] ^ feedbackReg[1] ^ feedbackReg[3] ^ feedbackReg[4];
192 
   assign mult_2[5] =  feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[4] ^ feedbackReg[5];
193 
   assign mult_2[6] =  feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[5] ^ feedbackReg[6];
194 
   assign mult_2[7] =  feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[6] ^ feedbackReg[7];
195 
   assign mult_14[0] =  feedbackReg[0] ^ feedbackReg[1] ^ feedbackReg[3] ^ feedbackReg[4];
196 
   assign mult_14[1] =  feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[4] ^ feedbackReg[5];
197 
   assign mult_14[2] =  feedbackReg[0] ^ feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[4] ^ feedbackReg[5] ^ feedbackReg[6];
198 
   assign mult_14[3] =  feedbackReg[0] ^ feedbackReg[2] ^ feedbackReg[4] ^ feedbackReg[5] ^ feedbackReg[6] ^ feedbackReg[7];
199 
   assign mult_14[4] =  feedbackReg[0] ^ feedbackReg[4] ^ feedbackReg[5] ^ feedbackReg[6] ^ feedbackReg[7];
200 
   assign mult_14[5] =  feedbackReg[0] ^ feedbackReg[1] ^ feedbackReg[5] ^ feedbackReg[6] ^ feedbackReg[7];
201 
   assign mult_14[6] =  feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[6] ^ feedbackReg[7];
202 
   assign mult_14[7] =  feedbackReg[0] ^ feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[7];
203 
   assign mult_4[0] =  feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[4] ^ feedbackReg[7];
204 
   assign mult_4[1] =  feedbackReg[0] ^ feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[5];
205 
   assign mult_4[2] =  feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[6] ^ feedbackReg[7];
206 
   assign mult_4[3] =  feedbackReg[0] ^ feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[3];
207 
   assign mult_4[4] =  feedbackReg[0] ^ feedbackReg[3] ^ feedbackReg[7];
208 
   assign mult_4[5] =  feedbackReg[1] ^ feedbackReg[4];
209 
   assign mult_4[6] =  feedbackReg[0] ^ feedbackReg[2] ^ feedbackReg[5];
210 
   assign mult_4[7] =  feedbackReg[0] ^ feedbackReg[1] ^ feedbackReg[3] ^ feedbackReg[6];
211 
   assign mult_3[0] =  feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[5] ^ feedbackReg[6];
212 
   assign mult_3[1] =  feedbackReg[0] ^ feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[6] ^ feedbackReg[7];
213 
   assign mult_3[2] =  feedbackReg[0] ^ feedbackReg[2] ^ feedbackReg[4] ^ feedbackReg[6] ^ feedbackReg[7];
214 
   assign mult_3[3] =  feedbackReg[2] ^ feedbackReg[6] ^ feedbackReg[7];
215 
   assign mult_3[4] =  feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[5] ^ feedbackReg[6] ^ feedbackReg[7];
216 
   assign mult_3[5] =  feedbackReg[0] ^ feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[6] ^ feedbackReg[7];
217 
   assign mult_3[6] =  feedbackReg[0] ^ feedbackReg[1] ^ feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[7];
218 
   assign mult_3[7] =  feedbackReg[0] ^ feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[4] ^ feedbackReg[5];
219 
   assign mult_1[0] =  feedbackReg[0] ^ feedbackReg[1] ^ feedbackReg[4] ^ feedbackReg[5] ^ feedbackReg[6] ^ feedbackReg[7];
220 
   assign mult_1[1] =  feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[5] ^ feedbackReg[6] ^ feedbackReg[7];
221 
   assign mult_1[2] =  feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[5];
222 
   assign mult_1[3] =  feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[7];
223 
   assign mult_1[4] =  feedbackReg[0] ^ feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[5] ^ feedbackReg[6] ^ feedbackReg[7];
224 
   assign mult_1[5] =  feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[6] ^ feedbackReg[7];
225 
   assign mult_1[6] =  feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[5] ^ feedbackReg[7];
226 
   assign mult_1[7] =  feedbackReg[0] ^ feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[5] ^ feedbackReg[6];
227 
   assign mult_20[0] =  feedbackReg[0] ^ feedbackReg[1] ^ feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[5] ^ feedbackReg[6] ^ feedbackReg[7];
228 
   assign mult_20[1] =  feedbackReg[0] ^ feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[4] ^ feedbackReg[5] ^ feedbackReg[6] ^ feedbackReg[7];
229 
   assign mult_20[2] =  feedbackReg[2] ^ feedbackReg[4];
230 
   assign mult_20[3] =  feedbackReg[1] ^ feedbackReg[4] ^ feedbackReg[6] ^ feedbackReg[7];
231 
   assign mult_20[4] =  feedbackReg[0] ^ feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[6];
232 
   assign mult_20[5] =  feedbackReg[0] ^ feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[5] ^ feedbackReg[7];
233 
   assign mult_20[6] =  feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[5] ^ feedbackReg[6];
234 
   assign mult_20[7] =  feedbackReg[0] ^ feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[5] ^ feedbackReg[6] ^ feedbackReg[7];
235 
   assign mult_8[0] =  feedbackReg[0] ^ feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[5] ^ feedbackReg[6] ^ feedbackReg[7];
236 
   assign mult_8[1] =  feedbackReg[0] ^ feedbackReg[1] ^ feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[5] ^ feedbackReg[6] ^ feedbackReg[7];
237 
   assign mult_8[2] =  feedbackReg[1] ^ feedbackReg[3];
238 
   assign mult_8[3] =  feedbackReg[0] ^ feedbackReg[3] ^ feedbackReg[5] ^ feedbackReg[6] ^ feedbackReg[7];
239 
   assign mult_8[4] =  feedbackReg[0] ^ feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[5];
240 
   assign mult_8[5] =  feedbackReg[0] ^ feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[6];
241 
   assign mult_8[6] =  feedbackReg[0] ^ feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[5] ^ feedbackReg[7];
242 
   assign mult_8[7] =  feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[5] ^ feedbackReg[6];
243 
   assign mult_11[0] =  feedbackReg[4] ^ feedbackReg[5] ^ feedbackReg[6];
244 
   assign mult_11[1] =  feedbackReg[5] ^ feedbackReg[6] ^ feedbackReg[7];
245 
   assign mult_11[2] =  feedbackReg[0] ^ feedbackReg[4] ^ feedbackReg[5] ^ feedbackReg[7];
246 
   assign mult_11[3] =  feedbackReg[0] ^ feedbackReg[1] ^ feedbackReg[4];
247 
   assign mult_11[4] =  feedbackReg[0] ^ feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[4] ^ feedbackReg[6];
248 
   assign mult_11[5] =  feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[5] ^ feedbackReg[7];
249 
   assign mult_11[6] =  feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[6];
250 
   assign mult_11[7] =  feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[5] ^ feedbackReg[7];
251 
   assign mult_21[0] =  feedbackReg[0] ^ feedbackReg[2] ^ feedbackReg[4] ^ feedbackReg[5] ^ feedbackReg[6] ^ feedbackReg[7];
252 
   assign mult_21[1] =  feedbackReg[1] ^ feedbackReg[3] ^ feedbackReg[5] ^ feedbackReg[6] ^ feedbackReg[7];
253 
   assign mult_21[2] =  feedbackReg[5];
254 
   assign mult_21[3] =  feedbackReg[0] ^ feedbackReg[2] ^ feedbackReg[4] ^ feedbackReg[5] ^ feedbackReg[7];
255 
   assign mult_21[4] =  feedbackReg[0] ^ feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[7];
256 
   assign mult_21[5] =  feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[5];
257 
   assign mult_21[6] =  feedbackReg[0] ^ feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[5] ^ feedbackReg[6];
258 
   assign mult_21[7] =  feedbackReg[1] ^ feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[5] ^ feedbackReg[6] ^ feedbackReg[7];
259 
   assign mult_5[0] =  feedbackReg[2] ^ feedbackReg[4];
260 
   assign mult_5[1] =  feedbackReg[0] ^ feedbackReg[3] ^ feedbackReg[5];
261 
   assign mult_5[2] =  feedbackReg[0] ^ feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[6];
262 
   assign mult_5[3] =  feedbackReg[1] ^ feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[7];
263 
   assign mult_5[4] =  feedbackReg[0] ^ feedbackReg[5];
264 
   assign mult_5[5] =  feedbackReg[1] ^ feedbackReg[6];
265 
   assign mult_5[6] =  feedbackReg[0] ^ feedbackReg[2] ^ feedbackReg[7];
266 
   assign mult_5[7] =  feedbackReg[1] ^ feedbackReg[3];
267 
   assign mult_13[0] =  feedbackReg[0] ^ feedbackReg[2] ^ feedbackReg[7];
268 
   assign mult_13[1] =  feedbackReg[1] ^ feedbackReg[3];
269 
   assign mult_13[2] =  feedbackReg[0] ^ feedbackReg[4] ^ feedbackReg[7];
270 
   assign mult_13[3] =  feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[5] ^ feedbackReg[7];
271 
   assign mult_13[4] =  feedbackReg[3] ^ feedbackReg[6] ^ feedbackReg[7];
272 
   assign mult_13[5] =  feedbackReg[4] ^ feedbackReg[7];
273 
   assign mult_13[6] =  feedbackReg[0] ^ feedbackReg[5];
274 
   assign mult_13[7] =  feedbackReg[1] ^ feedbackReg[6];
275 
   assign mult_16[0] =  feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[5] ^ feedbackReg[6] ^ feedbackReg[7];
276 
   assign mult_16[1] =  feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[5] ^ feedbackReg[6] ^ feedbackReg[7];
277 
   assign mult_16[2] =  feedbackReg[0] ^ feedbackReg[1] ^ feedbackReg[2];
278 
   assign mult_16[3] =  feedbackReg[4] ^ feedbackReg[5] ^ feedbackReg[6] ^ feedbackReg[7];
279 
   assign mult_16[4] =  feedbackReg[0] ^ feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[4];
280 
   assign mult_16[5] =  feedbackReg[0] ^ feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[5];
281 
   assign mult_16[6] =  feedbackReg[0] ^ feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[5] ^ feedbackReg[6];
282 
   assign mult_16[7] =  feedbackReg[0] ^ feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[5] ^ feedbackReg[6] ^ feedbackReg[7];
283 
   assign mult_0[0] =  feedbackReg[0] ^ feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[5] ^ feedbackReg[6] ^ feedbackReg[7];
284 
   assign mult_0[1] =  feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[5] ^ feedbackReg[6] ^ feedbackReg[7];
285 
   assign mult_0[2] =  feedbackReg[0] ^ feedbackReg[1];
286 
   assign mult_0[3] =  feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[5] ^ feedbackReg[6] ^ feedbackReg[7];
287 
   assign mult_0[4] =  feedbackReg[0] ^ feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[3];
288 
   assign mult_0[5] =  feedbackReg[0] ^ feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[4];
289 
   assign mult_0[6] =  feedbackReg[0] ^ feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[5];
290 
   assign mult_0[7] =  feedbackReg[0] ^ feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[5] ^ feedbackReg[6];
291 
   assign mult_18[0] =  feedbackReg[1] ^ feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[5] ^ feedbackReg[6];
292 
   assign mult_18[1] =  feedbackReg[2] ^ feedbackReg[4] ^ feedbackReg[5] ^ feedbackReg[6] ^ feedbackReg[7];
293 
   assign mult_18[2] =  feedbackReg[1] ^ feedbackReg[4] ^ feedbackReg[7];
294 
   assign mult_18[3] =  feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[6];
295 
   assign mult_18[4] =  feedbackReg[0] ^ feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[6] ^ feedbackReg[7];
296 
   assign mult_18[5] =  feedbackReg[0] ^ feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[7];
297 
   assign mult_18[6] =  feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[4];
298 
   assign mult_18[7] =  feedbackReg[0] ^ feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[5];
299 
   assign mult_19[0] =  feedbackReg[0] ^ feedbackReg[1] ^ feedbackReg[5] ^ feedbackReg[6];
300 
   assign mult_19[1] =  feedbackReg[0] ^ feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[6] ^ feedbackReg[7];
301 
   assign mult_19[2] =  feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[5] ^ feedbackReg[6] ^ feedbackReg[7];
302 
   assign mult_19[3] =  feedbackReg[1] ^ feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[5] ^ feedbackReg[7];
303 
   assign mult_19[4] =  feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[4];
304 
   assign mult_19[5] =  feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[5];
305 
   assign mult_19[6] =  feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[6];
306 
   assign mult_19[7] =  feedbackReg[0] ^ feedbackReg[4] ^ feedbackReg[5] ^ feedbackReg[7];
307 
 
308 
 
309 
 
310 
   //---------------------------------------------------------------
311 
   //- syndromeReg
312 
   //---------------------------------------------------------------
313 
   always @(posedge CLK or negedge RESET) begin
314 
      if (~RESET) begin
315 
         syndromeReg_0 [7:0]  <= 8'd0;
316 
         syndromeReg_1 [7:0]  <= 8'd0;
317 
         syndromeReg_2 [7:0]  <= 8'd0;
318 
         syndromeReg_3 [7:0]  <= 8'd0;
319 
         syndromeReg_4 [7:0]  <= 8'd0;
320 
         syndromeReg_5 [7:0]  <= 8'd0;
321 
         syndromeReg_6 [7:0]  <= 8'd0;
322 
         syndromeReg_7 [7:0]  <= 8'd0;
323 
         syndromeReg_8 [7:0]  <= 8'd0;
324 
         syndromeReg_9 [7:0]  <= 8'd0;
325 
         syndromeReg_10 [7:0] <= 8'd0;
326 
         syndromeReg_11 [7:0] <= 8'd0;
327 
         syndromeReg_12 [7:0] <= 8'd0;
328 
         syndromeReg_13 [7:0] <= 8'd0;
329 
         syndromeReg_14 [7:0] <= 8'd0;
330 
         syndromeReg_15 [7:0] <= 8'd0;
331 
         syndromeReg_16 [7:0] <= 8'd0;
332 
         syndromeReg_17 [7:0] <= 8'd0;
333 
         syndromeReg_18 [7:0] <= 8'd0;
334 
         syndromeReg_19 [7:0] <= 8'd0;
335 
         syndromeReg_20 [7:0] <= 8'd0;
336 
         syndromeReg_21 [7:0] <= 8'd0;
337 
      end
338 
      else if (enable == 1'b1) begin
339 
         if (startPls == 1'b1) begin
340 
            syndromeReg_0 [7:0]  <= mult_0 [7:0];
341 
            syndromeReg_1 [7:0]  <= mult_1 [7:0];
342 
            syndromeReg_2 [7:0]  <= mult_2 [7:0];
343 
            syndromeReg_3 [7:0]  <= mult_3 [7:0];
344 
            syndromeReg_4 [7:0]  <= mult_4 [7:0];
345 
            syndromeReg_5 [7:0]  <= mult_5 [7:0];
346 
            syndromeReg_6 [7:0]  <= mult_6 [7:0];
347 
            syndromeReg_7 [7:0]  <= mult_7 [7:0];
348 
            syndromeReg_8 [7:0]  <= mult_8 [7:0];
349 
            syndromeReg_9 [7:0]  <= mult_9 [7:0];
350 
            syndromeReg_10 [7:0] <= mult_10 [7:0];
351 
            syndromeReg_11 [7:0] <= mult_11 [7:0];
352 
            syndromeReg_12 [7:0] <= mult_12 [7:0];
353 
            syndromeReg_13 [7:0] <= mult_13 [7:0];
354 
            syndromeReg_14 [7:0] <= mult_14 [7:0];
355 
            syndromeReg_15 [7:0] <= mult_15 [7:0];
356 
            syndromeReg_16 [7:0] <= mult_16 [7:0];
357 
            syndromeReg_17 [7:0] <= mult_17 [7:0];
358 
            syndromeReg_18 [7:0] <= mult_18 [7:0];
359 
            syndromeReg_19 [7:0] <= mult_19 [7:0];
360 
            syndromeReg_20 [7:0] <= mult_20 [7:0];
361 
            syndromeReg_21 [7:0] <= mult_21 [7:0];
362 
         end
363 
         else begin
364 
            syndromeReg_0 [7:0]  <= mult_0 [7:0];
365 
            syndromeReg_1 [7:0]  <= (syndromeReg_0 [7:0] ^ mult_1 [7:0]);
366 
            syndromeReg_2 [7:0]  <= (syndromeReg_1 [7:0] ^ mult_2 [7:0]);
367 
            syndromeReg_3 [7:0]  <= (syndromeReg_2 [7:0] ^ mult_3 [7:0]);
368 
            syndromeReg_4 [7:0]  <= (syndromeReg_3 [7:0] ^ mult_4 [7:0]);
369 
            syndromeReg_5 [7:0]  <= (syndromeReg_4 [7:0] ^ mult_5 [7:0]);
370 
            syndromeReg_6 [7:0]  <= (syndromeReg_5 [7:0] ^ mult_6 [7:0]);
371 
            syndromeReg_7 [7:0]  <= (syndromeReg_6 [7:0] ^ mult_7 [7:0]);
372 
            syndromeReg_8 [7:0]  <= (syndromeReg_7 [7:0] ^ mult_8 [7:0]);
373 
            syndromeReg_9 [7:0]  <= (syndromeReg_8 [7:0] ^ mult_9 [7:0]);
374 
            syndromeReg_10 [7:0] <= (syndromeReg_9 [7:0] ^ mult_10 [7:0]);
375 
            syndromeReg_11 [7:0] <= (syndromeReg_10 [7:0] ^ mult_11 [7:0]);
376 
            syndromeReg_12 [7:0] <= (syndromeReg_11 [7:0] ^ mult_12 [7:0]);
377 
            syndromeReg_13 [7:0] <= (syndromeReg_12 [7:0] ^ mult_13 [7:0]);
378 
            syndromeReg_14 [7:0] <= (syndromeReg_13 [7:0] ^ mult_14 [7:0]);
379 
            syndromeReg_15 [7:0] <= (syndromeReg_14 [7:0] ^ mult_15 [7:0]);
380 
            syndromeReg_16 [7:0] <= (syndromeReg_15 [7:0] ^ mult_16 [7:0]);
381 
            syndromeReg_17 [7:0] <= (syndromeReg_16 [7:0] ^ mult_17 [7:0]);
382 
            syndromeReg_18 [7:0] <= (syndromeReg_17 [7:0] ^ mult_18 [7:0]);
383 
            syndromeReg_19 [7:0] <= (syndromeReg_18 [7:0] ^ mult_19 [7:0]);
384 
            syndromeReg_20 [7:0] <= (syndromeReg_19 [7:0] ^ mult_20 [7:0]);
385 
            syndromeReg_21 [7:0] <= (syndromeReg_20 [7:0] ^ mult_21 [7:0]);
386 
         end
387 
      end
388 
   end
389 
 
390 
 
391 
 
392 
   //---------------------------------------------------------------
393 
   //- feedbackReg
394 
   //---------------------------------------------------------------
395 
   always @( startPls, dataValid, dataIn, syndromeReg_21 ) begin
396 
      if (startPls == 1'b1) begin
397 
         feedbackReg[7:0] = dataIn[7:0];
398 
      end
399 
      else if (dataValid == 1'b1) begin
400 
         feedbackReg [7:0] = dataIn[7:0] ^  syndromeReg_21 [7:0];
401 
      end
402 
      else begin
403 
         feedbackReg [7:0] =  8'd0;
404 
      end
405 
   end
406 
 
407 
 
408 
 
409 
   //---------------------------------------------------------------
410 
   //- dataReg syndromeRegFF
411 
   //---------------------------------------------------------------
412 
   always @(posedge CLK, negedge RESET) begin
413 
      if (~RESET) begin
414 
         dataReg [7:0] <= 8'd0;
415 
         syndromeRegFF  [7:0] <= 8'd0;
416 
      end
417 
      else if (enable == 1'b1) begin
418 
         dataReg [7:0] <=  dataIn [7:0];
419 
         syndromeRegFF  [7:0] <=  syndromeReg_21 [7:0];
420 
      end
421 
   end
422 
 
423 
 
424 
 
425 
   //---------------------------------------------------------------
426 
   //- wireOut
427 
   //---------------------------------------------------------------
428 
   always @( count, dataReg, syndromeRegFF) begin
429 
      if (count [7:0]<= 8'd233) begin
430 
         wireOut[7:0] = dataReg[7:0];
431 
      end
432 
      else begin
433 
         wireOut[7:0] = syndromeRegFF[7:0];
434 
      end
435 
   end
436 
 
437 
 
438 
 
439 
   //---------------------------------------------------------------
440 
   //- dataOutInner
441 
   //---------------------------------------------------------------
442 
   reg [7:0]   dataOutInner;
443 
   always @(posedge CLK, negedge RESET) begin
444 
      if (~RESET) begin
445 
         dataOutInner <= 8'd0;
446 
      end
447 
      else begin
448 
         dataOutInner <= wireOut;
449 
      end
450 
   end
451 
 
452 
 
453 
 
454 
   //---------------------------------------------------------------
455 
   //- Output ports
456 
   //---------------------------------------------------------------
457 
   assign dataOut = dataOutInner;
458 
 
459 
 
460 
 
461 
endmodule

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