OpenCores
URL https://opencores.org/ocsvn/reed_solomon_codec_generator/reed_solomon_codec_generator/trunk

Subversion Repositories reed_solomon_codec_generator

[/] [reed_solomon_codec_generator/] [trunk/] [example/] [sim/] [simReedSolomon.v] - Blame information for rev 10

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 4 issei 
//===================================================================
2 
// Module Name : simReedSolomon
3 
// File Name   : simReedSolomon.v
4 
// Function    : Rs bench Module
5 
//
6 
// Revision History:
7 
// Date          By           Version    Change Description
8 
//===================================================================
9 
// 2009/02/03  Gael Sapience     1.0       Original
10 
//
11 
//===================================================================
12 
// (C) COPYRIGHT 2009 SYSTEM LSI CO., Ltd.
13 
//
14 
 
15 
 
16 
module simReedSolomon;
17 
 
18 
 
19 
   //------------------------------------------------------------------------
20 
   // global registers
21 
   //------------------------------------------------------------------------
22 
   reg          CLK;       // RSenc && RSdec system clock signal
23 
   reg          RESET;     // RSenc && RSdec system reset
24 
 
25 
 
26 
   //------------------------------------------------------------------------
27 
   // RS decoder registers & wires
28 
   //------------------------------------------------------------------------
29 
   reg          rsdecEnable;        // RSdec system enable
30 
   reg          rsdecSync;          // RSdec sync signal
31 
   reg          rsdecErasureIn;     // RSdec erasure Input signal
32 
   reg  [7:0]   rsdecDataIn;        // Rsdec Data Input signal
33 
 
34 
 
35 
   wire         rsdecOutStartPls;   // RSdec first decoded symbol trigger
36 
   wire         rsdecOutDone;       // RSdec last decoder symbol trigger
37 
   wire [7:0]   rsdecOutData;       // RSdec output data signal
38 
   wire [7:0]   rsdecErrorNum;      // RSdec Error amount statistics
39 
   wire [7:0]   rsdecErasureNum;    // RSdec Erasure amount statistics
40 
   wire         rsdecFail;          // RSdec Pass/Fail output flag
41 
   wire         rsdecOutEnable;     // RSdec output enable
42 
   wire [7:0]   rsdecDelayedData;   // RSdec delayed data
43 
 
44 
 
45 
   //------------------------------------------------------------------------
46 
   // RS encoder registers & wires
47 
   //------------------------------------------------------------------------
48 
   reg          rsencEnable;     // RSenc data enable input
49 
   reg          rsencStartPls;   // RSenc Start Pulse input
50 
   reg  [7:0]   rsencDataIn;     // RSenc data in
51 
   wire [7:0]   rsencDataOut;    // RSenc data out
52 
 
53 
 
54 
   //------------------------------------------------------------------------
55 
   //RS  Decoder Top module Instantiation
56 
   //------------------------------------------------------------------------
57 
   RsDecodeTop RsDecodeTop(
58 
      // Inputs
59 
      .CLK          (CLK),               // system clock
60 
      .RESET        (RESET),             // system reset
61 
      .enable       (rsdecEnable),       // RSdec enable in
62 
      .startPls     (rsdecSync),         // RSdec sync signal
63 
      .erasureIn    (rsdecErasureIn),    // RSdec erasure in
64 
      .dataIn       (rsdecDataIn),       // RSdec data in
65 
      // Outputs
66 
      .outEnable    (rsdecOutEnable),    // RSdec enable out
67 
      .outStartPls  (rsdecOutStartPls),  // RSdec start pulse out
68 
      .outDone      (rsdecOutDone),      // RSdec done out
69 
      .errorNum     (rsdecErrorNum),     // RSdec error number
70 
      .erasureNum   (rsdecErasureNum),   // RSdec Erasure number
71 
      .fail         (rsdecFail),         // RSdec Pass/Fail flag
72 
      .delayedData  (rsdecDelayedData),  // RSdec delayed data
73 
      .outData      (rsdecOutData)       // Rsdec data out
74 
   );
75 
 
76 
 
77 
   //------------------------------------------------------------------------
78 
   // RS Encoder Top module Instantiation
79 
   //------------------------------------------------------------------------
80 
   RsEncodeTop RsEncodeTop(
81 
      // Inputs
82 
      .CLK      (CLK),           // system clock
83 
      .RESET    (RESET),         // system reset
84 
      .enable   (rsencEnable),   // RSenc enable signal
85 
      .startPls (rsencStartPls), // RSenc sync signal
86 
      // Outputs
87 
      .dataIn   (rsencDataIn),   // RSenc data in
88 
      .dataOut  (rsencDataOut)   // RSenc data out
89 
   );
90 
 
91 
 
92 
   //------------------------------------------------------------------------
93 
   // clock CLK generation
94 
   //------------------------------------------------------------------------
95 
   parameter period = 10;
96 
   always # (period) CLK =~CLK;
97 
 
98 
 
99 
   //------------------------------------------------------------------------
100 
   // log file
101 
   //------------------------------------------------------------------------
102 
   reg           simStart;
103 
   integer  handleA;
104 
   initial begin
105 
      handleA = $fopen("result.out", "w");
106 
   end
107 
 
108 
 
109 
   //------------------------------------------------------------------------
110 
   //- RSdec Input && Output Data files
111 
   //------------------------------------------------------------------------
112 
   reg  [23:0]   rsdecInputBank  [2902:0];
113 
   reg  [87:0]   rsdecOutputBank [2549:0];
114 
 
115 
   initial $readmemh("./RsDecIn.hex", rsdecInputBank);
116 
   initial $readmemh("./RsDecOut.hex", rsdecOutputBank);
117 
 
118 
 
119 
   //------------------------------------------------------------------------
120 
   //- RSenc Input && Output Data files
121 
   //------------------------------------------------------------------------
122 
   reg  [15:0]   rsencInputBank  [764:0];
123 
   reg  [7:0]   rsencOutputBank  [764:0];
124 
   initial $readmemh("./RsEncIn.hex", rsencInputBank);
125 
   initial $readmemh("./RsEncOut.hex", rsencOutputBank);
126 
 
127 
 
128 
   //--------------------------------------------------------------------------
129 
   //- simStartFF1, simStartFF2, simStartFF3
130 
   //--------------------------------------------------------------------------
131 
   reg simStartFF1;
132 
   reg simStartFF2;
133 
   reg simStartFF3;
134 
   always @(posedge CLK or negedge RESET) begin
135 
      if (~RESET) begin
136 
         simStartFF1 <= 1'b0;
137 
         simStartFF2 <= 1'b0;
138 
         simStartFF3 <= 1'b0;
139 
      end
140 
      else begin
141 
         simStartFF1 <= simStart;
142 
         simStartFF2 <= simStartFF1;
143 
         simStartFF3 <= simStartFF2;
144 
      end
145 
   end
146 
 
147 
 
148 
   //------------------------------------------------------------------------
149 
   //+ IBankIndex
150 
   //------------------------------------------------------------------------
151 
   reg [31:0]  IBankIndex;
152 
   always @(posedge CLK or negedge RESET) begin
153 
      if (~RESET) begin
154 
         IBankIndex <= 32'd0;
155 
      end
156 
      else if (simStart == 1'b1) begin
157 
         IBankIndex <= IBankIndex + 32'd1;
158 
      end
159 
   end
160 
 
161 
 
162 
//--------------------------------------------------------------------------
163 
//- RS Decoder Test Bench
164 
//--------------------------------------------------------------------------
165 
   //--------------------------------------------------------------------------
166 
   //- rsdecInput
167 
   //--------------------------------------------------------------------------
168 
   wire  [23:0] rsdecInput;
169 
   assign rsdecInput = (IBankIndex < 32'd2903) ? rsdecInputBank [IBankIndex] : 24'd0;
170 
 
171 
 
172 
   //------------------------------------------------------------------------
173 
   //+ rsdecSync
174 
   //------------------------------------------------------------------------
175 
   always @(posedge CLK or negedge RESET) begin
176 
      if (~RESET) begin
177 
         rsdecSync <= 1'b0;
178 
      end
179 
      else if (simStart == 1'b1) begin
180 
         rsdecSync <= rsdecInput[20];
181 
      end
182 
   end
183 
 
184 
 
185 
   //------------------------------------------------------------------------
186 
   //+ rsdecEnable
187 
   //------------------------------------------------------------------------
188 
   always @(posedge CLK or negedge RESET) begin
189 
      if (~RESET) begin
190 
         rsdecEnable <= 1'b0;
191 
      end
192 
      else if (simStart == 1'b1) begin
193 
         rsdecEnable <= rsdecInput[16];
194 
      end
195 
   end
196 
 
197 
 
198 
   //------------------------------------------------------------------------
199 
   //+ rsdecErasureIn
200 
   //------------------------------------------------------------------------
201 
   always @(posedge CLK or negedge RESET) begin
202 
      if (~RESET) begin
203 
         rsdecErasureIn <= 1'b0;
204 
      end
205 
      else begin
206 
         rsdecErasureIn <= rsdecInput[12];
207 
      end
208 
   end
209 
 
210 
 
211 
   //------------------------------------------------------------------------
212 
   //+ rsdecDataIn
213 
   //------------------------------------------------------------------------
214 
   always @(posedge CLK or negedge RESET) begin
215 
      if (~RESET) begin
216 
         rsdecDataIn <= 8'd0;
217 
      end
218 
      else begin
219 
         rsdecDataIn <= rsdecInput[7:0];
220 
      end
221 
   end
222 
 
223 
 
224 
   //------------------------------------------------------------------------
225 
   //+ rsdecOBankIndex
226 
   //------------------------------------------------------------------------
227 
   reg [31:0]  rsdecOBankIndex;
228 
   always @(posedge CLK or negedge RESET) begin
229 
      if (~RESET) begin
230 
         rsdecOBankIndex <= 32'd0;
231 
      end
232 
      else if (rsdecOutEnable == 1'b1) begin
233 
         rsdecOBankIndex <= rsdecOBankIndex + 32'd1;
234 
      end
235 
   end
236 
 
237 
 
238 
   //--------------------------------------------------------------------------
239 
   //- rsdecOutput
240 
   //--------------------------------------------------------------------------
241 
   wire  [87:0] rsdecOutput;
242 
   assign rsdecOutput = (rsdecOBankIndex < 32'd2550) ? rsdecOutputBank [rsdecOBankIndex] : 48'd0;
243 
 
244 
 
245 
   //--------------------------------------------------------------------------
246 
   //+ rsdecExpNumError
247 
   //--------------------------------------------------------------------------
248 
   reg [7:0]   rsdecExpNumError;
249 
   always @(posedge CLK or negedge RESET) begin
250 
      if (~RESET) begin
251 
         rsdecExpNumError <= 8'd0;
252 
      end
253 
      else if (rsdecOutEnable == 1'b1) begin
254 
         rsdecExpNumError <= rsdecOutput[47:36];
255 
      end
256 
      else begin
257 
         rsdecExpNumError <= 8'd0;
258 
      end
259 
   end
260 
 
261 
 
262 
   //--------------------------------------------------------------------------
263 
   //+ rsdecTheoricalNumError
264 
   //--------------------------------------------------------------------------
265 
   reg [7:0]   rsdecTheoricalNumError;
266 
   always @(posedge CLK or negedge RESET) begin
267 
      if (~RESET) begin
268 
         rsdecTheoricalNumError <= 8'd0;
269 
      end
270 
      else if (rsdecOutEnable == 1'b1) begin
271 
         rsdecTheoricalNumError <= rsdecOutput[75:64];
272 
      end
273 
      else begin
274 
         rsdecTheoricalNumError <= 8'd0;
275 
      end
276 
   end
277 
 
278 
 
279 
   //--------------------------------------------------------------------------
280 
   //+ rsdecExpNumErasure
281 
   //--------------------------------------------------------------------------
282 
   reg [7:0]   rsdecExpNumErasure;
283 
   always @(posedge CLK or negedge RESET) begin
284 
      if (~RESET) begin
285 
         rsdecExpNumErasure <= 8'd0;
286 
      end
287 
      else if (rsdecOutEnable == 1'b1) begin
288 
         rsdecExpNumErasure <= rsdecOutput[31:24];
289 
      end
290 
      else begin
291 
         rsdecExpNumErasure <= 8'd0;
292 
      end
293 
   end
294 
 
295 
 
296 
   //--------------------------------------------------------------------------
297 
   //+ rsdecTheoricalNumErasure
298 
   //--------------------------------------------------------------------------
299 
   reg [7:0]   rsdecTheoricalNumErasure;
300 
   always @(posedge CLK or negedge RESET) begin
301 
      if (~RESET) begin
302 
         rsdecTheoricalNumErasure <= 8'd0;
303 
      end
304 
      else if (rsdecOutEnable == 1'b1) begin
305 
         rsdecTheoricalNumErasure <= rsdecOutput[59:52];
306 
      end
307 
      else begin
308 
         rsdecTheoricalNumErasure <= 8'd0;
309 
      end
310 
   end
311 
 
312 
 
313 
   //--------------------------------------------------------------------------
314 
   //+ rsdecTheoricalSyndromeLength
315 
   //--------------------------------------------------------------------------
316 
   reg [12:0]   rsdecTheoricalSyndromeLength;
317 
   always @(posedge CLK or negedge RESET) begin
318 
      if (~RESET) begin
319 
         rsdecTheoricalSyndromeLength <= 13'd0;
320 
      end
321 
      else if (rsdecOutEnable == 1'b1) begin
322 
         rsdecTheoricalSyndromeLength <= {1'b0, rsdecOutput[87:76]};
323 
      end
324 
      else begin
325 
         rsdecTheoricalSyndromeLength <= 13'd0;
326 
      end
327 
   end
328 
 
329 
 
330 
   //--------------------------------------------------------------------------
331 
   //+ rsdecExpFailFlag
332 
   //--------------------------------------------------------------------------
333 
   reg       rsdecExpFailFlag;
334 
   always @(posedge CLK or negedge RESET) begin
335 
      if (~RESET) begin
336 
         rsdecExpFailFlag <= 1'b0;
337 
      end
338 
      else if (rsdecOutEnable == 1'b1) begin
339 
         rsdecExpFailFlag <= rsdecOutput[48];
340 
      end
341 
   end
342 
   //--------------------------------------------------------------------------
343 
   //+ rsdecExpData
344 
   //--------------------------------------------------------------------------
345 
   reg [7:0]   rsdecExpData;
346 
   always @(posedge CLK or negedge RESET) begin
347 
      if (~RESET) begin
348 
         rsdecExpData <= 8'd0;
349 
      end
350 
      else if (rsdecOutEnable == 1'b1) begin
351 
         rsdecExpData <= rsdecOutput[7:0];
352 
      end
353 
      else begin
354 
         rsdecExpData <= 8'd0;
355 
      end
356 
   end
357 
 
358 
 
359 
   //--------------------------------------------------------------------------
360 
   //+ rsdecExpDelayedData
361 
   //--------------------------------------------------------------------------
362 
   reg [7:0]   rsdecExpDelayedData;
363 
   always @(posedge CLK or negedge RESET) begin
364 
      if (~RESET) begin
365 
         rsdecExpDelayedData <= 8'd0;
366 
      end
367 
      else if (rsdecOutEnable == 1'b1) begin
368 
         rsdecExpDelayedData <= rsdecOutput[19:12];
369 
      end
370 
      else begin
371 
         rsdecExpDelayedData <= 8'd0;
372 
      end
373 
   end
374 
 
375 
 
376 
   //--------------------------------------------------------------------------
377 
   //+ rsdecOutDataFF, rsdecOutEnableFF
378 
   //--------------------------------------------------------------------------
379 
   reg [7:0] rsdecOutDataFF;
380 
   reg       rsdecOutEnableFF;
381 
   reg [7:0]   rsdecErrorNumFF;
382 
   reg [7:0]   rsdecErasureNumFF;
383 
   reg         rsdecFailFF;
384 
   reg [7:0] rsdecDelayedDataFF;
385 
   always @(posedge CLK or negedge RESET) begin
386 
      if (~RESET) begin
387 
         rsdecOutDataFF <= 8'd0;
388 
         rsdecOutEnableFF <= 1'b0;
389 
         rsdecDelayedDataFF <= 8'd0;
390 
         rsdecErrorNumFF <= 8'd0;
391 
         rsdecErasureNumFF <= 8'd0;
392 
         rsdecFailFF <= 1'b0;
393 
      end
394 
      else begin
395 
         rsdecOutDataFF <= rsdecOutData;
396 
         rsdecOutEnableFF <= rsdecOutEnable;
397 
         rsdecDelayedDataFF <= rsdecDelayedData;
398 
         rsdecErrorNumFF <= rsdecErrorNum;
399 
         rsdecErasureNumFF <= rsdecErasureNum;
400 
         rsdecFailFF <= rsdecFail;
401 
      end
402 
   end
403 
 
404 
 
405 
   //--------------------------------------------------------------------------
406 
   //+ rsDecDelayedDataFlag, rsDecNGDelayedDataFlag
407 
   //--------------------------------------------------------------------------
408 
   reg   rsDecDelayedDataFlag;
409 
   reg   rsDecNGDelayedDataFlag;
410 
   always @(posedge CLK or negedge RESET) begin
411 
      if (~RESET) begin
412 
         rsDecDelayedDataFlag <= 1'b0;
413 
         rsDecNGDelayedDataFlag   <= 1'b0;
414 
      end
415 
      else if (rsdecOutEnableFF == 1'b1) begin
416 
         if (rsdecDelayedDataFF == rsdecExpDelayedData) begin
417 
            rsDecDelayedDataFlag <= 1'b0;
418 
         end
419 
         else begin
420 
            rsDecDelayedDataFlag <= 1'b1;
421 
            rsDecNGDelayedDataFlag   <= 1'b1;
422 
            $fdisplay(handleA,"Reed Solomon Decoder: Delayed Data Pin NG!!!!");
423 
         end
424 
      end
425 
      else begin
426 
         rsDecDelayedDataFlag <= 1'b0;
427 
      end
428 
   end
429 
 
430 
 
431 
 
432 
 
433 
 
434 
 
435 
   //--------------------------------------------------------------------------
436 
   //+ rsDecDataFlag, rsDecNGDataFlag
437 
   //--------------------------------------------------------------------------
438 
   reg   rsDecDataFlag;
439 
   reg   rsDecNGDataFlag;
440 
   always @(posedge CLK or negedge RESET) begin
441 
      if (~RESET) begin
442 
         rsDecDataFlag <= 1'b0;
443 
         rsDecNGDataFlag   <= 1'b0;
444 
      end
445 
      else if (rsdecOutEnableFF == 1'b1) begin
446 
         if (rsdecOutDataFF == rsdecExpData) begin
447 
            rsDecDataFlag <= 1'b0;
448 
         end
449 
         else begin
450 
            rsDecDataFlag <= 1'b1;
451 
            rsDecNGDataFlag   <= 1'b1;
452 
            $fdisplay(handleA,"Reed Solomon Decoder Data Out: NG!!!!");
453 
         end
454 
      end
455 
      else begin
456 
         rsDecDataFlag <= 1'b0;
457 
      end
458 
   end
459 
 
460 
 
461 
 
462 
   //--------------------------------------------------------------------------
463 
   //+ rsDecErasureFlag, rsDecNGErasureFlag
464 
   //--------------------------------------------------------------------------
465 
   reg   rsDecErasureFlag;
466 
   reg   rsDecNGErasureFlag;
467 
   always @(posedge CLK or negedge RESET) begin
468 
      if (~RESET) begin
469 
         rsDecErasureFlag <= 1'b0;
470 
         rsDecNGErasureFlag   <= 1'b0;
471 
      end
472 
      else if (rsdecOutEnableFF == 1'b1) begin
473 
         if (rsdecErasureNumFF == rsdecExpNumErasure) begin
474 
            rsDecErasureFlag <= 1'b0;
475 
         end
476 
         else begin
477 
            rsDecErasureFlag <= 1'b1;
478 
            rsDecNGErasureFlag   <= 1'b1;
479 
            $fdisplay(handleA,"Reed Solomon Decoder Erasure Pin: NG!!!!");
480 
         end
481 
      end
482 
      else begin
483 
         rsDecErasureFlag <= 1'b0;
484 
      end
485 
   end
486 
 
487 
 
488 
 
489 
   //--------------------------------------------------------------------------
490 
   //+ rsDecErrorFlag, rsDecNGErrorFlag
491 
   //--------------------------------------------------------------------------
492 
   reg   rsDecErrorFlag;
493 
   reg   rsDecNGErrorFlag;
494 
   always @(posedge CLK or negedge RESET) begin
495 
      if (~RESET) begin
496 
         rsDecErrorFlag <= 1'b0;
497 
         rsDecNGErrorFlag   <= 1'b0;
498 
      end
499 
      else if (rsdecOutEnableFF == 1'b1) begin
500 
         if (rsdecErrorNumFF == rsdecExpNumError) begin
501 
            rsDecErrorFlag <= 1'b0;
502 
         end
503 
         else begin
504 
            rsDecErrorFlag <= 1'b1;
505 
            rsDecNGErrorFlag   <= 1'b1;
506 
            $fdisplay(handleA,"Reed Solomon Decoder Error Pin : NG!!!!");
507 
         end
508 
      end
509 
      else begin
510 
         rsDecErrorFlag <= 1'b0;
511 
      end
512 
   end
513 
 
514 
 
515 
 
516 
   //--------------------------------------------------------------------------
517 
   //+ rsDecFailPinFlag, rsDecNGFailPinFlag
518 
   //--------------------------------------------------------------------------
519 
   reg   rsDecFailPinFlag;
520 
   reg   rsDecNGFailPinFlag;
521 
   always @(posedge CLK or negedge RESET) begin
522 
      if (~RESET) begin
523 
         rsDecFailPinFlag <= 1'b0;
524 
         rsDecNGFailPinFlag   <= 1'b0;
525 
      end
526 
      else if (rsdecOutEnableFF == 1'b1) begin
527 
         if (rsdecFailFF == rsdecExpFailFlag) begin
528 
            rsDecFailPinFlag <= 1'b0;
529 
         end
530 
         else begin
531 
            rsDecFailPinFlag <= 1'b1;
532 
            rsDecNGFailPinFlag   <= 1'b1;
533 
            $fdisplay(handleA,"Reed Solomon Decoder Pass Fail Pin : NG!!!!");
534 
         end
535 
      end
536 
      else begin
537 
         rsDecFailPinFlag <= 1'b0;
538 
      end
539 
   end
540 
 
541 
 
542 
 
543 
   //--------------------------------------------------------------------------
544 
   //+ rsDecCorrectionAmount
545 
   //--------------------------------------------------------------------------
546 
   wire [12:0]  rsDecCorrectionAmount;
547 
   assign rsDecCorrectionAmount = rsdecTheoricalNumErasure + rsdecTheoricalNumError*2;
548 
 
549 
 
550 
   //--------------------------------------------------------------------------
551 
   //+ passFailPinThFlag
552 
   //--------------------------------------------------------------------------
553 
   reg   passFailPinThFlag;
554 
   always @(posedge CLK or negedge RESET) begin
555 
      if (~RESET) begin
556 
         passFailPinThFlag <= 1'b0;
557 
      end
558 
      else if (rsdecOutEnableFF == 1'b1) begin
559 
         if (rsDecCorrectionAmount <=  rsdecTheoricalSyndromeLength) begin
560 
            if (rsdecFailFF==1'b1) begin
561 
               passFailPinThFlag <= 1'b1;
562 
               $fdisplay(handleA,"Reed Solomon Decoder Pass Fail Pin : Th NG!!!!");
563 
            end
564 
         end
565 
      end
566 
   end
567 
   //--------------------------------------------------------------------------
568 
   //+ ErasurePinThFlag
569 
   //--------------------------------------------------------------------------
570 
   reg   ErasurePinThFlag;
571 
   always @(posedge CLK or negedge RESET) begin
572 
      if (~RESET) begin
573 
         ErasurePinThFlag <= 1'b0;
574 
      end
575 
      else if (rsdecOutEnableFF == 1'b1) begin
576 
         if (rsDecCorrectionAmount <=  rsdecTheoricalSyndromeLength) begin
577 
            if (rsdecErasureNumFF != rsdecTheoricalNumErasure) begin
578 
               ErasurePinThFlag <= 1'b1;
579 
               $fdisplay(handleA,"Reed Solomon Decoder Erasure Pin : Th NG!!!!");
580 
            end
581 
         end
582 
      end
583 
   end
584 
   //--------------------------------------------------------------------------
585 
   //+ ErrorPinThFlag
586 
   //--------------------------------------------------------------------------
587 
   reg   ErrorPinThFlag;
588 
   always @(posedge CLK or negedge RESET) begin
589 
      if (~RESET) begin
590 
         ErrorPinThFlag <= 1'b0;
591 
      end
592 
      else if (rsdecOutEnableFF == 1'b1) begin
593 
         if (rsDecCorrectionAmount <=  rsdecTheoricalSyndromeLength) begin
594 
            if (rsdecErrorNumFF != rsdecTheoricalNumError) begin
595 
               ErrorPinThFlag <= 1'b1;
596 
               $fdisplay(handleA,"Reed Solomon Decoder Error Pin : Th NG!!!!");
597 
            end
598 
         end
599 
      end
600 
   end
601 
//--------------------------------------------------------------------------
602 
//- RS Encoder Test Bench
603 
//--------------------------------------------------------------------------
604 
   //--------------------------------------------------------------------------
605 
   //- rsencInput
606 
   //--------------------------------------------------------------------------
607 
   wire  [15:0] rsencInput;
608 
   assign rsencInput = (IBankIndex < 32'd765) ? rsencInputBank [IBankIndex] : 16'd0;
609 
 
610 
 
611 
   //------------------------------------------------------------------------
612 
   //+ rsencStartPls
613 
   //------------------------------------------------------------------------
614 
   always @(posedge CLK or negedge RESET) begin
615 
      if (~RESET) begin
616 
         rsencStartPls <= 1'b0;
617 
      end
618 
      else if (simStart == 1'b1) begin
619 
         rsencStartPls <= rsencInput[12];
620 
      end
621 
   end
622 
 
623 
 
624 
   //------------------------------------------------------------------------
625 
   //+ rsencEnable
626 
   //------------------------------------------------------------------------
627 
   always @(posedge CLK or negedge RESET) begin
628 
      if (~RESET) begin
629 
         rsencEnable <= 1'b0;
630 
      end
631 
      else begin
632 
         rsencEnable <= rsencInput[8];
633 
      end
634 
   end
635 
 
636 
 
637 
   //------------------------------------------------------------------------
638 
   //+ rsencDataIn
639 
   //------------------------------------------------------------------------
640 
   always @(posedge CLK or negedge RESET) begin
641 
      if (~RESET) begin
642 
         rsencDataIn <= 8'd0;
643 
      end
644 
      else begin
645 
         rsencDataIn <= rsencInput[7:0];
646 
      end
647 
   end
648 
 
649 
 
650 
   //------------------------------------------------------------------------
651 
   //+ rsencOBankIndex
652 
   //------------------------------------------------------------------------
653 
   reg [31:0]  rsencOBankIndex;
654 
   always @(posedge CLK or negedge RESET) begin
655 
      if (~RESET) begin
656 
         rsencOBankIndex <= 32'd0;
657 
      end
658 
      else if (simStartFF2 == 1'b1) begin
659 
         rsencOBankIndex <= rsencOBankIndex + 32'd1;
660 
      end
661 
   end
662 
 
663 
 
664 
   //--------------------------------------------------------------------------
665 
   //- rsencOutput
666 
   //--------------------------------------------------------------------------
667 
   wire  [7:0] rsencOutput;
668 
   assign rsencOutput = (rsencOBankIndex < 32'd765) ? rsencOutputBank [rsencOBankIndex] : 8'd0;
669 
 
670 
 
671 
   //--------------------------------------------------------------------------
672 
   //+ rsencExpData
673 
   //--------------------------------------------------------------------------
674 
   reg [7:0]   rsencExpData;
675 
   always @(posedge CLK or negedge RESET) begin
676 
      if (~RESET) begin
677 
         rsencExpData <= 8'd0;
678 
      end
679 
      else if (simStartFF2 == 1'b1) begin
680 
         rsencExpData <= rsencOutput[7:0];
681 
      end
682 
      else begin
683 
         rsencExpData <= 8'd0;
684 
      end
685 
   end
686 
 
687 
 
688 
   //--------------------------------------------------------------------------
689 
   //+ rsEncPassFailFlag, rsEncFailFlag
690 
   //--------------------------------------------------------------------------
691 
   reg   rsEncPassFailFlag;
692 
   reg   rsEncFailFlag;
693 
   always @(posedge CLK or negedge RESET) begin
694 
      if (~RESET) begin
695 
         rsEncPassFailFlag <= 1'b0;
696 
         rsEncFailFlag   <= 1'b0;
697 
      end
698 
      else if ((simStartFF3 == 1'b1) && (rsencOBankIndex < 32'd766)) begin
699 
         if (rsencDataOut == rsencExpData) begin
700 
            rsEncPassFailFlag <= 1'b0;
701 
         end
702 
         else begin
703 
            rsEncPassFailFlag <= 1'b1;
704 
            rsEncFailFlag   <= 1'b1;
705 
            $fdisplay(handleA,"Reed Solomon Encoder: NG!!!!");
706 
         end
707 
      end
708 
      else begin
709 
         rsEncPassFailFlag <= 1'b0;
710 
      end
711 
   end
712 
   //------------------------------------------------------------------------
713 
   // + simOver
714 
   //------------------------------------------------------------------------
715 
   reg simOver;
716 
   always @(posedge CLK or negedge RESET) begin
717 
      if (~RESET) begin
718 
         simOver <= 1'b0;
719 
      end
720 
      else if ((rsencOBankIndex > 32'd766) && (rsdecOBankIndex > 32'd2549)) begin
721 
         simOver <= 1'b1;
722 
         $fclose(handleA);
723 
         $finish;
724 
      end
725 
   end
726 
   //------------------------------------------------------------------------
727 
   //-  TIMING
728 
   //------------------------------------------------------------------------
729 
   initial begin
730 
      simStart = 1'b0;
731 
      CLK = 0;
732 
      RESET = 1;
733 
      #(period*2)       RESET = 0;
734 
      #(period*2)       RESET = 1;
735 
      #(period*20) simStart = 1'b1;
736 
      #(period*99999999);
737 
      #(period*99999999);
738 
      #(period*99999999);
739 
      #(period*99999999);
740 
      #(period*99999999);
741 
      #(period*99999999);
742 
      #(period*99999999);
743 
      #(period*99999999);
744 
      #(period*99999999);
745 
      #(period*99999999);
746 
      #(period*99999999);
747 
      #(period*99999999);
748 
      #(period*99999999);
749 
      #(period*99999999);
750 
      #(period*99999999);
751 
      #(period*99999999);
752 
      #(period*99999999);
753 
      #(period*99999999);
754 
      #(period*99999999);
755 
      #(period*99999999);
756 
      #(period*99999999);
757 
      #(period*99999999);
758 
      #(period*99999999);
759 
      #(period*99999999);
760 
      #(period*99999999);
761 
      #(period*99999999);
762 
      #(period*99999999);
763 
      #(period*99999999);
764 
      #(period*99999999);
765 
      #(period*99999999);
766 
      #(period*99999999);
767 
      #(period*99999999);
768 
      #(period*99999999);
769 
      #(period*99999999);
770 
      #(period*99999999);
771 
      #(period*99999999);
772 
      #(period*99999999);
773 
      #(period*99999999);
774 
      #(period*99999999);
775 
      #(period*99999999);
776 
   end
777 
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.