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//===================================================================
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// Module Name : simReedSolomon
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// File Name : simReedSolomon.v
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// Function : Rs bench Module
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//
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// Revision History:
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// Date By Version Change Description
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//===================================================================
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// 2009/02/03 Gael Sapience 1.0 Original
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//
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//===================================================================
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// (C) COPYRIGHT 2009 SYSTEM LSI CO., Ltd.
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//
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module simReedSolomon;
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//------------------------------------------------------------------------
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// global registers
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//------------------------------------------------------------------------
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reg CLK; // RSenc && RSdec system clock signal
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reg RESET; // RSenc && RSdec system reset
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//------------------------------------------------------------------------
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// RS decoder registers & wires
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//------------------------------------------------------------------------
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reg rsdecEnable; // RSdec system enable
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reg rsdecSync; // RSdec sync signal
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reg rsdecErasureIn; // RSdec erasure Input signal
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reg [7:0] rsdecDataIn; // Rsdec Data Input signal
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wire rsdecOutStartPls; // RSdec first decoded symbol trigger
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wire rsdecOutDone; // RSdec last decoder symbol trigger
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wire [7:0] rsdecOutData; // RSdec output data signal
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wire [7:0] rsdecErrorNum; // RSdec Error amount statistics
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wire [7:0] rsdecErasureNum; // RSdec Erasure amount statistics
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wire rsdecFail; // RSdec Pass/Fail output flag
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wire rsdecOutEnable; // RSdec output enable
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wire [7:0] rsdecDelayedData; // RSdec delayed data
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//------------------------------------------------------------------------
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// RS encoder registers & wires
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//------------------------------------------------------------------------
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reg rsencEnable; // RSenc data enable input
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reg rsencStartPls; // RSenc Start Pulse input
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reg [7:0] rsencDataIn; // RSenc data in
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wire [7:0] rsencDataOut; // RSenc data out
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//------------------------------------------------------------------------
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//RS Decoder Top module Instantiation
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//------------------------------------------------------------------------
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RsDecodeTop RsDecodeTop(
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// Inputs
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.CLK (CLK), // system clock
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.RESET (RESET), // system reset
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.enable (rsdecEnable), // RSdec enable in
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.startPls (rsdecSync), // RSdec sync signal
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.erasureIn (rsdecErasureIn), // RSdec erasure in
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.dataIn (rsdecDataIn), // RSdec data in
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// Outputs
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.outEnable (rsdecOutEnable), // RSdec enable out
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.outStartPls (rsdecOutStartPls), // RSdec start pulse out
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.outDone (rsdecOutDone), // RSdec done out
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.errorNum (rsdecErrorNum), // RSdec error number
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.erasureNum (rsdecErasureNum), // RSdec Erasure number
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.fail (rsdecFail), // RSdec Pass/Fail flag
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.delayedData (rsdecDelayedData), // RSdec delayed data
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.outData (rsdecOutData) // Rsdec data out
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);
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//------------------------------------------------------------------------
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// RS Encoder Top module Instantiation
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//------------------------------------------------------------------------
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RsEncodeTop RsEncodeTop(
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// Inputs
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.CLK (CLK), // system clock
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.RESET (RESET), // system reset
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.enable (rsencEnable), // RSenc enable signal
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.startPls (rsencStartPls), // RSenc sync signal
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// Outputs
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.dataIn (rsencDataIn), // RSenc data in
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.dataOut (rsencDataOut) // RSenc data out
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);
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//------------------------------------------------------------------------
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// clock CLK generation
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//------------------------------------------------------------------------
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parameter period = 10;
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always # (period) CLK =~CLK;
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//------------------------------------------------------------------------
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// log file
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//------------------------------------------------------------------------
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reg simStart;
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integer handleA;
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initial begin
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handleA = $fopen("result.out", "w");
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end
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//------------------------------------------------------------------------
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//- RSdec Input && Output Data files
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//------------------------------------------------------------------------
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reg [23:0] rsdecInputBank [2902:0];
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reg [87:0] rsdecOutputBank [2549:0];
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initial $readmemh("./RsDecIn.hex", rsdecInputBank);
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initial $readmemh("./RsDecOut.hex", rsdecOutputBank);
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//------------------------------------------------------------------------
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//- RSenc Input && Output Data files
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//------------------------------------------------------------------------
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reg [15:0] rsencInputBank [764:0];
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reg [7:0] rsencOutputBank [764:0];
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initial $readmemh("./RsEncIn.hex", rsencInputBank);
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initial $readmemh("./RsEncOut.hex", rsencOutputBank);
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//--------------------------------------------------------------------------
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//- simStartFF1, simStartFF2, simStartFF3
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//--------------------------------------------------------------------------
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reg simStartFF1;
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reg simStartFF2;
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reg simStartFF3;
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always @(posedge CLK or negedge RESET) begin
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if (~RESET) begin
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simStartFF1 <= 1'b0;
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simStartFF2 <= 1'b0;
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simStartFF3 <= 1'b0;
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end
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else begin
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simStartFF1 <= simStart;
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simStartFF2 <= simStartFF1;
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simStartFF3 <= simStartFF2;
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end
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end
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//------------------------------------------------------------------------
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//+ IBankIndex
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//------------------------------------------------------------------------
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reg [31:0] IBankIndex;
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always @(posedge CLK or negedge RESET) begin
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if (~RESET) begin
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IBankIndex <= 32'd0;
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end
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else if (simStart == 1'b1) begin
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IBankIndex <= IBankIndex + 32'd1;
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end
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end
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//--------------------------------------------------------------------------
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//- RS Decoder Test Bench
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//--------------------------------------------------------------------------
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//--------------------------------------------------------------------------
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//- rsdecInput
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//--------------------------------------------------------------------------
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wire [23:0] rsdecInput;
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assign rsdecInput = (IBankIndex < 32'd2903) ? rsdecInputBank [IBankIndex] : 24'd0;
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//------------------------------------------------------------------------
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//+ rsdecSync
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//------------------------------------------------------------------------
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always @(posedge CLK or negedge RESET) begin
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if (~RESET) begin
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rsdecSync <= 1'b0;
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end
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else if (simStart == 1'b1) begin
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rsdecSync <= rsdecInput[20];
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end
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end
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//------------------------------------------------------------------------
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//+ rsdecEnable
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//------------------------------------------------------------------------
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always @(posedge CLK or negedge RESET) begin
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if (~RESET) begin
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rsdecEnable <= 1'b0;
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end
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else if (simStart == 1'b1) begin
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rsdecEnable <= rsdecInput[16];
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end
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end
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//------------------------------------------------------------------------
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//+ rsdecErasureIn
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//------------------------------------------------------------------------
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always @(posedge CLK or negedge RESET) begin
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if (~RESET) begin
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rsdecErasureIn <= 1'b0;
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end
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else begin
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rsdecErasureIn <= rsdecInput[12];
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end
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end
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//------------------------------------------------------------------------
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//+ rsdecDataIn
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//------------------------------------------------------------------------
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always @(posedge CLK or negedge RESET) begin
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if (~RESET) begin
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rsdecDataIn <= 8'd0;
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end
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else begin
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rsdecDataIn <= rsdecInput[7:0];
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end
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end
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//------------------------------------------------------------------------
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//+ rsdecOBankIndex
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//------------------------------------------------------------------------
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reg [31:0] rsdecOBankIndex;
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always @(posedge CLK or negedge RESET) begin
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if (~RESET) begin
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rsdecOBankIndex <= 32'd0;
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end
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else if (rsdecOutEnable == 1'b1) begin
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rsdecOBankIndex <= rsdecOBankIndex + 32'd1;
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end
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end
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//--------------------------------------------------------------------------
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//- rsdecOutput
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//--------------------------------------------------------------------------
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wire [87:0] rsdecOutput;
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assign rsdecOutput = (rsdecOBankIndex < 32'd2550) ? rsdecOutputBank [rsdecOBankIndex] : 48'd0;
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//--------------------------------------------------------------------------
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//+ rsdecExpNumError
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//--------------------------------------------------------------------------
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reg [7:0] rsdecExpNumError;
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always @(posedge CLK or negedge RESET) begin
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if (~RESET) begin
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rsdecExpNumError <= 8'd0;
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end
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else if (rsdecOutEnable == 1'b1) begin
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rsdecExpNumError <= rsdecOutput[47:36];
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end
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else begin
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rsdecExpNumError <= 8'd0;
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end
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end
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//--------------------------------------------------------------------------
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//+ rsdecTheoricalNumError
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//--------------------------------------------------------------------------
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reg [7:0] rsdecTheoricalNumError;
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always @(posedge CLK or negedge RESET) begin
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if (~RESET) begin
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rsdecTheoricalNumError <= 8'd0;
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end
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else if (rsdecOutEnable == 1'b1) begin
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rsdecTheoricalNumError <= rsdecOutput[75:64];
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end
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else begin
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rsdecTheoricalNumError <= 8'd0;
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end
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end
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//--------------------------------------------------------------------------
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//+ rsdecExpNumErasure
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//--------------------------------------------------------------------------
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reg [7:0] rsdecExpNumErasure;
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always @(posedge CLK or negedge RESET) begin
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if (~RESET) begin
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rsdecExpNumErasure <= 8'd0;
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end
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else if (rsdecOutEnable == 1'b1) begin
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rsdecExpNumErasure <= rsdecOutput[31:24];
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end
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else begin
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rsdecExpNumErasure <= 8'd0;
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end
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end
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//--------------------------------------------------------------------------
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//+ rsdecTheoricalNumErasure
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//--------------------------------------------------------------------------
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reg [7:0] rsdecTheoricalNumErasure;
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always @(posedge CLK or negedge RESET) begin
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if (~RESET) begin
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rsdecTheoricalNumErasure <= 8'd0;
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end
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else if (rsdecOutEnable == 1'b1) begin
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rsdecTheoricalNumErasure <= rsdecOutput[59:52];
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end
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else begin
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rsdecTheoricalNumErasure <= 8'd0;
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end
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end
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//--------------------------------------------------------------------------
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//+ rsdecTheoricalSyndromeLength
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//--------------------------------------------------------------------------
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reg [12:0] rsdecTheoricalSyndromeLength;
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always @(posedge CLK or negedge RESET) begin
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if (~RESET) begin
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rsdecTheoricalSyndromeLength <= 13'd0;
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end
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else if (rsdecOutEnable == 1'b1) begin
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rsdecTheoricalSyndromeLength <= {1'b0, rsdecOutput[87:76]};
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end
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else begin
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rsdecTheoricalSyndromeLength <= 13'd0;
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end
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end
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//--------------------------------------------------------------------------
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//+ rsdecExpFailFlag
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//--------------------------------------------------------------------------
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reg rsdecExpFailFlag;
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always @(posedge CLK or negedge RESET) begin
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if (~RESET) begin
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rsdecExpFailFlag <= 1'b0;
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end
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else if (rsdecOutEnable == 1'b1) begin
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rsdecExpFailFlag <= rsdecOutput[48];
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end
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end
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//--------------------------------------------------------------------------
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//+ rsdecExpData
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//--------------------------------------------------------------------------
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reg [7:0] rsdecExpData;
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always @(posedge CLK or negedge RESET) begin
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if (~RESET) begin
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rsdecExpData <= 8'd0;
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end
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else if (rsdecOutEnable == 1'b1) begin
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rsdecExpData <= rsdecOutput[7:0];
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end
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else begin
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rsdecExpData <= 8'd0;
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end
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end
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//--------------------------------------------------------------------------
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//+ rsdecExpDelayedData
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//--------------------------------------------------------------------------
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reg [7:0] rsdecExpDelayedData;
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always @(posedge CLK or negedge RESET) begin
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if (~RESET) begin
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rsdecExpDelayedData <= 8'd0;
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end
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else if (rsdecOutEnable == 1'b1) begin
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rsdecExpDelayedData <= rsdecOutput[19:12];
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end
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else begin
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rsdecExpDelayedData <= 8'd0;
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end
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end
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//--------------------------------------------------------------------------
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//+ rsdecOutDataFF, rsdecOutEnableFF
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//--------------------------------------------------------------------------
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reg [7:0] rsdecOutDataFF;
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reg rsdecOutEnableFF;
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reg [7:0] rsdecErrorNumFF;
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reg [7:0] rsdecErasureNumFF;
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reg rsdecFailFF;
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reg [7:0] rsdecDelayedDataFF;
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385 |
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always @(posedge CLK or negedge RESET) begin
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if (~RESET) begin
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rsdecOutDataFF <= 8'd0;
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rsdecOutEnableFF <= 1'b0;
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|
|
rsdecDelayedDataFF <= 8'd0;
|
390 |
|
|
rsdecErrorNumFF <= 8'd0;
|
391 |
|
|
rsdecErasureNumFF <= 8'd0;
|
392 |
|
|
rsdecFailFF <= 1'b0;
|
393 |
|
|
end
|
394 |
|
|
else begin
|
395 |
|
|
rsdecOutDataFF <= rsdecOutData;
|
396 |
|
|
rsdecOutEnableFF <= rsdecOutEnable;
|
397 |
|
|
rsdecDelayedDataFF <= rsdecDelayedData;
|
398 |
|
|
rsdecErrorNumFF <= rsdecErrorNum;
|
399 |
|
|
rsdecErasureNumFF <= rsdecErasureNum;
|
400 |
|
|
rsdecFailFF <= rsdecFail;
|
401 |
|
|
end
|
402 |
|
|
end
|
403 |
|
|
|
404 |
|
|
|
405 |
|
|
//--------------------------------------------------------------------------
|
406 |
|
|
//+ rsDecDelayedDataFlag, rsDecNGDelayedDataFlag
|
407 |
|
|
//--------------------------------------------------------------------------
|
408 |
|
|
reg rsDecDelayedDataFlag;
|
409 |
|
|
reg rsDecNGDelayedDataFlag;
|
410 |
|
|
always @(posedge CLK or negedge RESET) begin
|
411 |
|
|
if (~RESET) begin
|
412 |
|
|
rsDecDelayedDataFlag <= 1'b0;
|
413 |
|
|
rsDecNGDelayedDataFlag <= 1'b0;
|
414 |
|
|
end
|
415 |
|
|
else if (rsdecOutEnableFF == 1'b1) begin
|
416 |
|
|
if (rsdecDelayedDataFF == rsdecExpDelayedData) begin
|
417 |
|
|
rsDecDelayedDataFlag <= 1'b0;
|
418 |
|
|
end
|
419 |
|
|
else begin
|
420 |
|
|
rsDecDelayedDataFlag <= 1'b1;
|
421 |
|
|
rsDecNGDelayedDataFlag <= 1'b1;
|
422 |
|
|
$fdisplay(handleA,"Reed Solomon Decoder: Delayed Data Pin NG!!!!");
|
423 |
|
|
end
|
424 |
|
|
end
|
425 |
|
|
else begin
|
426 |
|
|
rsDecDelayedDataFlag <= 1'b0;
|
427 |
|
|
end
|
428 |
|
|
end
|
429 |
|
|
|
430 |
|
|
|
431 |
|
|
|
432 |
|
|
|
433 |
|
|
|
434 |
|
|
|
435 |
|
|
//--------------------------------------------------------------------------
|
436 |
|
|
//+ rsDecDataFlag, rsDecNGDataFlag
|
437 |
|
|
//--------------------------------------------------------------------------
|
438 |
|
|
reg rsDecDataFlag;
|
439 |
|
|
reg rsDecNGDataFlag;
|
440 |
|
|
always @(posedge CLK or negedge RESET) begin
|
441 |
|
|
if (~RESET) begin
|
442 |
|
|
rsDecDataFlag <= 1'b0;
|
443 |
|
|
rsDecNGDataFlag <= 1'b0;
|
444 |
|
|
end
|
445 |
|
|
else if (rsdecOutEnableFF == 1'b1) begin
|
446 |
|
|
if (rsdecOutDataFF == rsdecExpData) begin
|
447 |
|
|
rsDecDataFlag <= 1'b0;
|
448 |
|
|
end
|
449 |
|
|
else begin
|
450 |
|
|
rsDecDataFlag <= 1'b1;
|
451 |
|
|
rsDecNGDataFlag <= 1'b1;
|
452 |
|
|
$fdisplay(handleA,"Reed Solomon Decoder Data Out: NG!!!!");
|
453 |
|
|
end
|
454 |
|
|
end
|
455 |
|
|
else begin
|
456 |
|
|
rsDecDataFlag <= 1'b0;
|
457 |
|
|
end
|
458 |
|
|
end
|
459 |
|
|
|
460 |
|
|
|
461 |
|
|
|
462 |
|
|
//--------------------------------------------------------------------------
|
463 |
|
|
//+ rsDecErasureFlag, rsDecNGErasureFlag
|
464 |
|
|
//--------------------------------------------------------------------------
|
465 |
|
|
reg rsDecErasureFlag;
|
466 |
|
|
reg rsDecNGErasureFlag;
|
467 |
|
|
always @(posedge CLK or negedge RESET) begin
|
468 |
|
|
if (~RESET) begin
|
469 |
|
|
rsDecErasureFlag <= 1'b0;
|
470 |
|
|
rsDecNGErasureFlag <= 1'b0;
|
471 |
|
|
end
|
472 |
|
|
else if (rsdecOutEnableFF == 1'b1) begin
|
473 |
|
|
if (rsdecErasureNumFF == rsdecExpNumErasure) begin
|
474 |
|
|
rsDecErasureFlag <= 1'b0;
|
475 |
|
|
end
|
476 |
|
|
else begin
|
477 |
|
|
rsDecErasureFlag <= 1'b1;
|
478 |
|
|
rsDecNGErasureFlag <= 1'b1;
|
479 |
|
|
$fdisplay(handleA,"Reed Solomon Decoder Erasure Pin: NG!!!!");
|
480 |
|
|
end
|
481 |
|
|
end
|
482 |
|
|
else begin
|
483 |
|
|
rsDecErasureFlag <= 1'b0;
|
484 |
|
|
end
|
485 |
|
|
end
|
486 |
|
|
|
487 |
|
|
|
488 |
|
|
|
489 |
|
|
//--------------------------------------------------------------------------
|
490 |
|
|
//+ rsDecErrorFlag, rsDecNGErrorFlag
|
491 |
|
|
//--------------------------------------------------------------------------
|
492 |
|
|
reg rsDecErrorFlag;
|
493 |
|
|
reg rsDecNGErrorFlag;
|
494 |
|
|
always @(posedge CLK or negedge RESET) begin
|
495 |
|
|
if (~RESET) begin
|
496 |
|
|
rsDecErrorFlag <= 1'b0;
|
497 |
|
|
rsDecNGErrorFlag <= 1'b0;
|
498 |
|
|
end
|
499 |
|
|
else if (rsdecOutEnableFF == 1'b1) begin
|
500 |
|
|
if (rsdecErrorNumFF == rsdecExpNumError) begin
|
501 |
|
|
rsDecErrorFlag <= 1'b0;
|
502 |
|
|
end
|
503 |
|
|
else begin
|
504 |
|
|
rsDecErrorFlag <= 1'b1;
|
505 |
|
|
rsDecNGErrorFlag <= 1'b1;
|
506 |
|
|
$fdisplay(handleA,"Reed Solomon Decoder Error Pin : NG!!!!");
|
507 |
|
|
end
|
508 |
|
|
end
|
509 |
|
|
else begin
|
510 |
|
|
rsDecErrorFlag <= 1'b0;
|
511 |
|
|
end
|
512 |
|
|
end
|
513 |
|
|
|
514 |
|
|
|
515 |
|
|
|
516 |
|
|
//--------------------------------------------------------------------------
|
517 |
|
|
//+ rsDecFailPinFlag, rsDecNGFailPinFlag
|
518 |
|
|
//--------------------------------------------------------------------------
|
519 |
|
|
reg rsDecFailPinFlag;
|
520 |
|
|
reg rsDecNGFailPinFlag;
|
521 |
|
|
always @(posedge CLK or negedge RESET) begin
|
522 |
|
|
if (~RESET) begin
|
523 |
|
|
rsDecFailPinFlag <= 1'b0;
|
524 |
|
|
rsDecNGFailPinFlag <= 1'b0;
|
525 |
|
|
end
|
526 |
|
|
else if (rsdecOutEnableFF == 1'b1) begin
|
527 |
|
|
if (rsdecFailFF == rsdecExpFailFlag) begin
|
528 |
|
|
rsDecFailPinFlag <= 1'b0;
|
529 |
|
|
end
|
530 |
|
|
else begin
|
531 |
|
|
rsDecFailPinFlag <= 1'b1;
|
532 |
|
|
rsDecNGFailPinFlag <= 1'b1;
|
533 |
|
|
$fdisplay(handleA,"Reed Solomon Decoder Pass Fail Pin : NG!!!!");
|
534 |
|
|
end
|
535 |
|
|
end
|
536 |
|
|
else begin
|
537 |
|
|
rsDecFailPinFlag <= 1'b0;
|
538 |
|
|
end
|
539 |
|
|
end
|
540 |
|
|
|
541 |
|
|
|
542 |
|
|
|
543 |
|
|
//--------------------------------------------------------------------------
|
544 |
|
|
//+ rsDecCorrectionAmount
|
545 |
|
|
//--------------------------------------------------------------------------
|
546 |
|
|
wire [12:0] rsDecCorrectionAmount;
|
547 |
|
|
assign rsDecCorrectionAmount = rsdecTheoricalNumErasure + rsdecTheoricalNumError*2;
|
548 |
|
|
|
549 |
|
|
|
550 |
|
|
//--------------------------------------------------------------------------
|
551 |
|
|
//+ passFailPinThFlag
|
552 |
|
|
//--------------------------------------------------------------------------
|
553 |
|
|
reg passFailPinThFlag;
|
554 |
|
|
always @(posedge CLK or negedge RESET) begin
|
555 |
|
|
if (~RESET) begin
|
556 |
|
|
passFailPinThFlag <= 1'b0;
|
557 |
|
|
end
|
558 |
|
|
else if (rsdecOutEnableFF == 1'b1) begin
|
559 |
|
|
if (rsDecCorrectionAmount <= rsdecTheoricalSyndromeLength) begin
|
560 |
|
|
if (rsdecFailFF==1'b1) begin
|
561 |
|
|
passFailPinThFlag <= 1'b1;
|
562 |
|
|
$fdisplay(handleA,"Reed Solomon Decoder Pass Fail Pin : Th NG!!!!");
|
563 |
|
|
end
|
564 |
|
|
end
|
565 |
|
|
end
|
566 |
|
|
end
|
567 |
|
|
//--------------------------------------------------------------------------
|
568 |
|
|
//+ ErasurePinThFlag
|
569 |
|
|
//--------------------------------------------------------------------------
|
570 |
|
|
reg ErasurePinThFlag;
|
571 |
|
|
always @(posedge CLK or negedge RESET) begin
|
572 |
|
|
if (~RESET) begin
|
573 |
|
|
ErasurePinThFlag <= 1'b0;
|
574 |
|
|
end
|
575 |
|
|
else if (rsdecOutEnableFF == 1'b1) begin
|
576 |
|
|
if (rsDecCorrectionAmount <= rsdecTheoricalSyndromeLength) begin
|
577 |
|
|
if (rsdecErasureNumFF != rsdecTheoricalNumErasure) begin
|
578 |
|
|
ErasurePinThFlag <= 1'b1;
|
579 |
|
|
$fdisplay(handleA,"Reed Solomon Decoder Erasure Pin : Th NG!!!!");
|
580 |
|
|
end
|
581 |
|
|
end
|
582 |
|
|
end
|
583 |
|
|
end
|
584 |
|
|
//--------------------------------------------------------------------------
|
585 |
|
|
//+ ErrorPinThFlag
|
586 |
|
|
//--------------------------------------------------------------------------
|
587 |
|
|
reg ErrorPinThFlag;
|
588 |
|
|
always @(posedge CLK or negedge RESET) begin
|
589 |
|
|
if (~RESET) begin
|
590 |
|
|
ErrorPinThFlag <= 1'b0;
|
591 |
|
|
end
|
592 |
|
|
else if (rsdecOutEnableFF == 1'b1) begin
|
593 |
|
|
if (rsDecCorrectionAmount <= rsdecTheoricalSyndromeLength) begin
|
594 |
|
|
if (rsdecErrorNumFF != rsdecTheoricalNumError) begin
|
595 |
|
|
ErrorPinThFlag <= 1'b1;
|
596 |
|
|
$fdisplay(handleA,"Reed Solomon Decoder Error Pin : Th NG!!!!");
|
597 |
|
|
end
|
598 |
|
|
end
|
599 |
|
|
end
|
600 |
|
|
end
|
601 |
|
|
//--------------------------------------------------------------------------
|
602 |
|
|
//- RS Encoder Test Bench
|
603 |
|
|
//--------------------------------------------------------------------------
|
604 |
|
|
//--------------------------------------------------------------------------
|
605 |
|
|
//- rsencInput
|
606 |
|
|
//--------------------------------------------------------------------------
|
607 |
|
|
wire [15:0] rsencInput;
|
608 |
|
|
assign rsencInput = (IBankIndex < 32'd765) ? rsencInputBank [IBankIndex] : 16'd0;
|
609 |
|
|
|
610 |
|
|
|
611 |
|
|
//------------------------------------------------------------------------
|
612 |
|
|
//+ rsencStartPls
|
613 |
|
|
//------------------------------------------------------------------------
|
614 |
|
|
always @(posedge CLK or negedge RESET) begin
|
615 |
|
|
if (~RESET) begin
|
616 |
|
|
rsencStartPls <= 1'b0;
|
617 |
|
|
end
|
618 |
|
|
else if (simStart == 1'b1) begin
|
619 |
|
|
rsencStartPls <= rsencInput[12];
|
620 |
|
|
end
|
621 |
|
|
end
|
622 |
|
|
|
623 |
|
|
|
624 |
|
|
//------------------------------------------------------------------------
|
625 |
|
|
//+ rsencEnable
|
626 |
|
|
//------------------------------------------------------------------------
|
627 |
|
|
always @(posedge CLK or negedge RESET) begin
|
628 |
|
|
if (~RESET) begin
|
629 |
|
|
rsencEnable <= 1'b0;
|
630 |
|
|
end
|
631 |
|
|
else begin
|
632 |
|
|
rsencEnable <= rsencInput[8];
|
633 |
|
|
end
|
634 |
|
|
end
|
635 |
|
|
|
636 |
|
|
|
637 |
|
|
//------------------------------------------------------------------------
|
638 |
|
|
//+ rsencDataIn
|
639 |
|
|
//------------------------------------------------------------------------
|
640 |
|
|
always @(posedge CLK or negedge RESET) begin
|
641 |
|
|
if (~RESET) begin
|
642 |
|
|
rsencDataIn <= 8'd0;
|
643 |
|
|
end
|
644 |
|
|
else begin
|
645 |
|
|
rsencDataIn <= rsencInput[7:0];
|
646 |
|
|
end
|
647 |
|
|
end
|
648 |
|
|
|
649 |
|
|
|
650 |
|
|
//------------------------------------------------------------------------
|
651 |
|
|
//+ rsencOBankIndex
|
652 |
|
|
//------------------------------------------------------------------------
|
653 |
|
|
reg [31:0] rsencOBankIndex;
|
654 |
|
|
always @(posedge CLK or negedge RESET) begin
|
655 |
|
|
if (~RESET) begin
|
656 |
|
|
rsencOBankIndex <= 32'd0;
|
657 |
|
|
end
|
658 |
|
|
else if (simStartFF2 == 1'b1) begin
|
659 |
|
|
rsencOBankIndex <= rsencOBankIndex + 32'd1;
|
660 |
|
|
end
|
661 |
|
|
end
|
662 |
|
|
|
663 |
|
|
|
664 |
|
|
//--------------------------------------------------------------------------
|
665 |
|
|
//- rsencOutput
|
666 |
|
|
//--------------------------------------------------------------------------
|
667 |
|
|
wire [7:0] rsencOutput;
|
668 |
|
|
assign rsencOutput = (rsencOBankIndex < 32'd765) ? rsencOutputBank [rsencOBankIndex] : 8'd0;
|
669 |
|
|
|
670 |
|
|
|
671 |
|
|
//--------------------------------------------------------------------------
|
672 |
|
|
//+ rsencExpData
|
673 |
|
|
//--------------------------------------------------------------------------
|
674 |
|
|
reg [7:0] rsencExpData;
|
675 |
|
|
always @(posedge CLK or negedge RESET) begin
|
676 |
|
|
if (~RESET) begin
|
677 |
|
|
rsencExpData <= 8'd0;
|
678 |
|
|
end
|
679 |
|
|
else if (simStartFF2 == 1'b1) begin
|
680 |
|
|
rsencExpData <= rsencOutput[7:0];
|
681 |
|
|
end
|
682 |
|
|
else begin
|
683 |
|
|
rsencExpData <= 8'd0;
|
684 |
|
|
end
|
685 |
|
|
end
|
686 |
|
|
|
687 |
|
|
|
688 |
|
|
//--------------------------------------------------------------------------
|
689 |
|
|
//+ rsEncPassFailFlag, rsEncFailFlag
|
690 |
|
|
//--------------------------------------------------------------------------
|
691 |
|
|
reg rsEncPassFailFlag;
|
692 |
|
|
reg rsEncFailFlag;
|
693 |
|
|
always @(posedge CLK or negedge RESET) begin
|
694 |
|
|
if (~RESET) begin
|
695 |
|
|
rsEncPassFailFlag <= 1'b0;
|
696 |
|
|
rsEncFailFlag <= 1'b0;
|
697 |
|
|
end
|
698 |
|
|
else if ((simStartFF3 == 1'b1) && (rsencOBankIndex < 32'd766)) begin
|
699 |
|
|
if (rsencDataOut == rsencExpData) begin
|
700 |
|
|
rsEncPassFailFlag <= 1'b0;
|
701 |
|
|
end
|
702 |
|
|
else begin
|
703 |
|
|
rsEncPassFailFlag <= 1'b1;
|
704 |
|
|
rsEncFailFlag <= 1'b1;
|
705 |
|
|
$fdisplay(handleA,"Reed Solomon Encoder: NG!!!!");
|
706 |
|
|
end
|
707 |
|
|
end
|
708 |
|
|
else begin
|
709 |
|
|
rsEncPassFailFlag <= 1'b0;
|
710 |
|
|
end
|
711 |
|
|
end
|
712 |
|
|
//------------------------------------------------------------------------
|
713 |
|
|
// + simOver
|
714 |
|
|
//------------------------------------------------------------------------
|
715 |
|
|
reg simOver;
|
716 |
|
|
always @(posedge CLK or negedge RESET) begin
|
717 |
|
|
if (~RESET) begin
|
718 |
|
|
simOver <= 1'b0;
|
719 |
|
|
end
|
720 |
|
|
else if ((rsencOBankIndex > 32'd766) && (rsdecOBankIndex > 32'd2549)) begin
|
721 |
|
|
simOver <= 1'b1;
|
722 |
|
|
$fclose(handleA);
|
723 |
|
|
$finish;
|
724 |
|
|
end
|
725 |
|
|
end
|
726 |
|
|
//------------------------------------------------------------------------
|
727 |
|
|
//- TIMING
|
728 |
|
|
//------------------------------------------------------------------------
|
729 |
|
|
initial begin
|
730 |
|
|
simStart = 1'b0;
|
731 |
|
|
CLK = 0;
|
732 |
|
|
RESET = 1;
|
733 |
|
|
#(period*2) RESET = 0;
|
734 |
|
|
#(period*2) RESET = 1;
|
735 |
|
|
#(period*20) simStart = 1'b1;
|
736 |
|
|
#(period*99999999);
|
737 |
|
|
#(period*99999999);
|
738 |
|
|
#(period*99999999);
|
739 |
|
|
#(period*99999999);
|
740 |
|
|
#(period*99999999);
|
741 |
|
|
#(period*99999999);
|
742 |
|
|
#(period*99999999);
|
743 |
|
|
#(period*99999999);
|
744 |
|
|
#(period*99999999);
|
745 |
|
|
#(period*99999999);
|
746 |
|
|
#(period*99999999);
|
747 |
|
|
#(period*99999999);
|
748 |
|
|
#(period*99999999);
|
749 |
|
|
#(period*99999999);
|
750 |
|
|
#(period*99999999);
|
751 |
|
|
#(period*99999999);
|
752 |
|
|
#(period*99999999);
|
753 |
|
|
#(period*99999999);
|
754 |
|
|
#(period*99999999);
|
755 |
|
|
#(period*99999999);
|
756 |
|
|
#(period*99999999);
|
757 |
|
|
#(period*99999999);
|
758 |
|
|
#(period*99999999);
|
759 |
|
|
#(period*99999999);
|
760 |
|
|
#(period*99999999);
|
761 |
|
|
#(period*99999999);
|
762 |
|
|
#(period*99999999);
|
763 |
|
|
#(period*99999999);
|
764 |
|
|
#(period*99999999);
|
765 |
|
|
#(period*99999999);
|
766 |
|
|
#(period*99999999);
|
767 |
|
|
#(period*99999999);
|
768 |
|
|
#(period*99999999);
|
769 |
|
|
#(period*99999999);
|
770 |
|
|
#(period*99999999);
|
771 |
|
|
#(period*99999999);
|
772 |
|
|
#(period*99999999);
|
773 |
|
|
#(period*99999999);
|
774 |
|
|
#(period*99999999);
|
775 |
|
|
#(period*99999999);
|
776 |
|
|
end
|
777 |
|
|
endmodule
|