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Subversion Repositories reed_solomon_codec_generator

[/] [reed_solomon_codec_generator/] [trunk/] [source/] [RsSimBench.cpp] - Blame information for rev 2

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//===================================================================
2 
// Module Name : RsSimBench
3 
// File Name   : RsSimBench.cpp
4 
// Function    : RTL Decoder Bench Module generation
5 
//
6 
// Revision History:
7 
// Date          By           Version    Change Description
8 
//===================================================================
9 
// 2009/02/03  Gael Sapience     1.0       Original
10 
//
11 
//===================================================================
12 
// (C) COPYRIGHT 2009 SYSTEM LSI CO., Ltd.
13 
//
14 
#include <stdio.h>
15 
#include <stdlib.h>
16 
#include <iostream>
17 
#include<windows.h>
18 
#include<fstream>
19 
#include <string.h>
20 
using namespace std;
21 
FILE  *OutFileSimBench;
22 
 
23 
 
24 
void RsSimBench(int DataSize, int TotalSize, int PrimPoly, int bitSymbol, int errorStats, int passFailFlag, int delayDataIn, int encDecMode, int ErasureOption, int BlockAmount, int encBlockAmount, int ErrorRate, int PowerErrorRate, int ErasureRate, int PowerErasureRate, int pathFlag, int lengthPath, char *rootFolderPath) {
25 
 
26 
 
27 
   //---------------------------------------------------------------
28 
   // c++ variables
29 
   //---------------------------------------------------------------
30 
   int syndromeLength;
31 
   int ii;
32 
   int Words, benchInSize, benchOutSize;
33 
   int encBenchInSize;
34 
   int delay;
35 
   int *euclideTab;
36 
   char *strsimReedSolomon;
37 
 
38 
   syndromeLength = TotalSize - DataSize;
39 
 
40 
   euclideTab    =new int[(syndromeLength+1)];
41 
 
42 
   //------------------------------------------------------------------------
43 
   //- Data files
44 
   //------------------------------------------------------------------------
45 
   Words = BlockAmount;
46 
 
47 
   benchOutSize = (Words * TotalSize) - 1;
48 
 
49 
   encBenchInSize = encBlockAmount * ((DataSize + (TotalSize-DataSize)*1)) - 1;
50 
 
51 
 
52 
   //------------------------------------------------------------------------
53 
   //- Euclide Length calculation
54 
   //------------------------------------------------------------------------
55 
   euclideTab [syndromeLength] = 3;
56 
   euclideTab [syndromeLength-1] = 3;
57 
 
58 
   for(ii=(syndromeLength-2); ii>0; ii=ii-2){
59 
      euclideTab [ii] = euclideTab   [ii+2] + 6;
60 
      euclideTab [ii-1] = euclideTab [ii+1] + 6;
61 
   }
62 
 
63 
   euclideTab [0] = euclideTab [2] + 6;
64 
 
65 
 
66 
   if (euclideTab [0] > TotalSize) {
67 
      benchInSize = (Words * euclideTab [0]) - 1;;
68 
   }
69 
   else {
70 
      benchInSize = (Words * TotalSize) - 1;;
71 
   }
72 
 
73 
  //---------------------------------------------------------------
74 
  // delay variable calculation
75 
  //---------------------------------------------------------------
76 
   if (ErasureOption == 1) {
77 
      delay = TotalSize + syndromeLength + 1 + euclideTab [0] + 5;
78 
   }else{
79 
      delay = TotalSize + euclideTab [0] + 5;
80 
   }
81 
   benchInSize = benchInSize + delay + 1;
82 
 
83 
 
84 
  //---------------------------------------------------------------
85 
  // open file
86 
  //---------------------------------------------------------------
87 
  strsimReedSolomon = (char *)calloc(lengthPath + 22,  sizeof(char));
88 
  if (pathFlag == 0) {
89 
        strsimReedSolomon[0] = '.';
90 
  }else{
91 
     for(ii=0; ii<lengthPath; ii++){
92 
        strsimReedSolomon[ii] = rootFolderPath[ii];
93 
     }
94 
  }
95 
  strcat(strsimReedSolomon, "/sim/simReedSolomon.v");
96 
 
97 
  OutFileSimBench = fopen(strsimReedSolomon,"w");
98 
 
99 
 
100 
 
101 
  //---------------------------------------------------------------
102 
  // Ports Declaration
103 
  //---------------------------------------------------------------
104 
   fprintf(OutFileSimBench, "//===================================================================\n");
105 
   fprintf(OutFileSimBench, "// Module Name : simReedSolomon\n");
106 
   fprintf(OutFileSimBench, "// File Name   : simReedSolomon.v\n");
107 
   fprintf(OutFileSimBench, "// Function    : Rs bench Module\n");
108 
   fprintf(OutFileSimBench, "// \n");
109 
   fprintf(OutFileSimBench, "// Revision History:\n");
110 
   fprintf(OutFileSimBench, "// Date          By           Version    Change Description\n");
111 
   fprintf(OutFileSimBench, "//===================================================================\n");
112 
   fprintf(OutFileSimBench, "// 2009/02/03  Gael Sapience     1.0       Original\n");
113 
   fprintf(OutFileSimBench, "//\n");
114 
   fprintf(OutFileSimBench, "//===================================================================\n");
115 
   fprintf(OutFileSimBench, "// (C) COPYRIGHT 2009 SYSTEM LSI CO., Ltd.\n");
116 
   fprintf(OutFileSimBench, "//\n\n\n");
117 
 
118 
   fprintf(OutFileSimBench, "module simReedSolomon;\n");
119 
   fprintf(OutFileSimBench, "\n\n");
120 
 
121 
 
122 
  //---------------------------------------------------------------
123 
  // global Reg & wires declaration
124 
  //---------------------------------------------------------------
125 
 
126 
   fprintf(OutFileSimBench, "   //------------------------------------------------------------------------\n");
127 
   fprintf(OutFileSimBench, "   // global registers\n");
128 
   fprintf(OutFileSimBench, "   //------------------------------------------------------------------------\n");
129 
   fprintf(OutFileSimBench, "   reg          CLK;       // RSenc && RSdec system clock signal\n");
130 
   fprintf(OutFileSimBench, "   reg          RESET;     // RSenc && RSdec system reset\n");
131 
   fprintf(OutFileSimBench, "\n\n");
132 
 
133 
 
134 
   //------------------------------------------------------------------------
135 
   // RS decoder Reg & wires declaration
136 
   //------------------------------------------------------------------------
137 
   if ((encDecMode == 2) || (encDecMode == 3)){
138 
      fprintf(OutFileSimBench, "   //------------------------------------------------------------------------\n");
139 
      fprintf(OutFileSimBench, "   // RS decoder registers & wires\n");
140 
      fprintf(OutFileSimBench, "   //------------------------------------------------------------------------\n");
141 
      fprintf(OutFileSimBench, "   reg          rsdecEnable;        // RSdec system enable\n");
142 
      fprintf(OutFileSimBench, "   reg          rsdecSync;          // RSdec sync signal\n");
143 
      fprintf(OutFileSimBench, "   reg          rsdecErasureIn;     // RSdec erasure Input signal  \n");
144 
      fprintf(OutFileSimBench, "   reg  [%d:0]   rsdecDataIn;        // Rsdec Data Input signal\n", bitSymbol-1);
145 
      fprintf(OutFileSimBench, "\n\n");
146 
 
147 
      fprintf(OutFileSimBench, "   wire         rsdecOutStartPls;   // RSdec first decoded symbol trigger\n");
148 
      fprintf(OutFileSimBench, "   wire         rsdecOutDone;       // RSdec last decoder symbol trigger\n");
149 
      fprintf(OutFileSimBench, "   wire [%d:0]   rsdecOutData;       // RSdec output data signal\n", bitSymbol-1);
150 
 
151 
 
152 
      if (errorStats == 1) {
153 
         fprintf(OutFileSimBench, "   wire [%d:0]   rsdecErrorNum;      // RSdec Error amount statistics\n", bitSymbol-1);
154 
         fprintf(OutFileSimBench, "   wire [%d:0]   rsdecErasureNum;    // RSdec Erasure amount statistics\n", bitSymbol-1);
155 
      }
156 
 
157 
      if (passFailFlag == 1){
158 
         fprintf(OutFileSimBench, "   wire         rsdecFail;          // RSdec Pass/Fail output flag\n");
159 
      }
160 
      fprintf(OutFileSimBench, "   wire         rsdecOutEnable;     // RSdec output enable\n");
161 
 
162 
      if (delayDataIn == 1){
163 
         fprintf(OutFileSimBench, "   wire [%d:0]   rsdecDelayedData;   // RSdec delayed data\n", bitSymbol-1);
164 
      }
165 
      fprintf(OutFileSimBench, "\n\n");
166 
   }
167 
 
168 
   //------------------------------------------------------------------------
169 
   // RS encoder Reg & wires declaration
170 
   //------------------------------------------------------------------------
171 
   if ((encDecMode == 1) || (encDecMode == 3)){
172 
      fprintf(OutFileSimBench, "   //------------------------------------------------------------------------\n");
173 
      fprintf(OutFileSimBench, "   // RS encoder registers & wires\n");
174 
      fprintf(OutFileSimBench, "   //------------------------------------------------------------------------\n");
175 
      fprintf(OutFileSimBench, "   reg          rsencEnable;     // RSenc data enable input\n");
176 
      fprintf(OutFileSimBench, "   reg          rsencStartPls;   // RSenc Start Pulse input\n");
177 
      fprintf(OutFileSimBench, "   reg  [%d:0]   rsencDataIn;     // RSenc data in\n", (bitSymbol-1));
178 
      fprintf(OutFileSimBench, "   wire [%d:0]   rsencDataOut;    // RSenc data out\n", (bitSymbol-1));
179 
      fprintf(OutFileSimBench, "\n\n");
180 
   }
181 
 
182 
 
183 
   //------------------------------------------------------------------------
184 
   // RS  Decoder Top module Instantiation
185 
   //------------------------------------------------------------------------
186 
   if ((encDecMode == 2) || (encDecMode == 3)){
187 
      fprintf(OutFileSimBench, "   //------------------------------------------------------------------------\n");
188 
      fprintf(OutFileSimBench, "   //RS  Decoder Top module Instantiation\n");
189 
      fprintf(OutFileSimBench, "   //------------------------------------------------------------------------\n");
190 
      fprintf(OutFileSimBench, "   RsDecodeTop RsDecodeTop(\n");
191 
      fprintf(OutFileSimBench, "      // Inputs\n");
192 
      fprintf(OutFileSimBench, "      .CLK          (CLK),               // system clock\n");
193 
      fprintf(OutFileSimBench, "      .RESET        (RESET),             // system reset\n");
194 
      fprintf(OutFileSimBench, "      .enable       (rsdecEnable),       // RSdec enable in\n");
195 
      fprintf(OutFileSimBench, "      .startPls     (rsdecSync),         // RSdec sync signal\n");
196 
      if (ErasureOption == 1) {
197 
         fprintf(OutFileSimBench, "      .erasureIn    (rsdecErasureIn),    // RSdec erasure in\n");
198 
      }
199 
      fprintf(OutFileSimBench, "      .dataIn       (rsdecDataIn),       // RSdec data in\n");
200 
      fprintf(OutFileSimBench, "      // Outputs\n");
201 
      fprintf(OutFileSimBench, "      .outEnable    (rsdecOutEnable),    // RSdec enable out\n");
202 
      fprintf(OutFileSimBench, "      .outStartPls  (rsdecOutStartPls),  // RSdec start pulse out\n");
203 
      fprintf(OutFileSimBench, "      .outDone      (rsdecOutDone),      // RSdec done out\n");
204 
 
205 
      if (errorStats == 1) {
206 
         fprintf(OutFileSimBench, "      .errorNum     (rsdecErrorNum),     // RSdec error number\n");
207 
         if (ErasureOption == 1) {
208 
            fprintf(OutFileSimBench, "      .erasureNum   (rsdecErasureNum),   // RSdec Erasure number\n");
209 
         }
210 
      }
211 
 
212 
      if (passFailFlag == 1){
213 
         fprintf(OutFileSimBench, "      .fail         (rsdecFail),         // RSdec Pass/Fail flag\n");
214 
      }
215 
      if (delayDataIn == 1){
216 
         fprintf(OutFileSimBench, "      .delayedData  (rsdecDelayedData),  // RSdec delayed data\n");
217 
      }
218 
      fprintf(OutFileSimBench, "      .outData      (rsdecOutData)       // Rsdec data out\n");
219 
      fprintf(OutFileSimBench, "   );\n");
220 
      fprintf(OutFileSimBench, "\n\n");
221 
   }
222 
 
223 
 
224 
   //------------------------------------------------------------------------
225 
   // Encoder Top module
226 
   //------------------------------------------------------------------------
227 
   if ((encDecMode == 1) || (encDecMode == 3)){
228 
      fprintf(OutFileSimBench, "   //------------------------------------------------------------------------\n");
229 
      fprintf(OutFileSimBench, "   // RS Encoder Top module Instantiation\n");
230 
      fprintf(OutFileSimBench, "   //------------------------------------------------------------------------\n");
231 
      fprintf(OutFileSimBench, "   RsEncodeTop RsEncodeTop(\n");
232 
      fprintf(OutFileSimBench, "      // Inputs\n");
233 
      fprintf(OutFileSimBench, "      .CLK      (CLK),           // system clock\n");
234 
      fprintf(OutFileSimBench, "      .RESET    (RESET),         // system reset\n");
235 
      fprintf(OutFileSimBench, "      .enable   (rsencEnable),   // RSenc enable signal\n");
236 
      fprintf(OutFileSimBench, "      .startPls (rsencStartPls), // RSenc sync signal\n");
237 
      fprintf(OutFileSimBench, "      // Outputs\n");
238 
      fprintf(OutFileSimBench, "      .dataIn   (rsencDataIn),   // RSenc data in\n");
239 
      fprintf(OutFileSimBench, "      .dataOut  (rsencDataOut)   // RSenc data out\n");
240 
      fprintf(OutFileSimBench, "   );\n");
241 
      fprintf(OutFileSimBench, "\n\n");
242 
   }
243 
 
244 
   //------------------------------------------------------------------------
245 
   // clock CLK generation
246 
   //------------------------------------------------------------------------
247 
   fprintf(OutFileSimBench, "   //------------------------------------------------------------------------\n");
248 
   fprintf(OutFileSimBench, "   // clock CLK generation\n");
249 
   fprintf(OutFileSimBench, "   //------------------------------------------------------------------------\n");
250 
   fprintf(OutFileSimBench, "   parameter period = 10;\n");
251 
   fprintf(OutFileSimBench, "   always # (period) CLK =~CLK;\n");
252 
   fprintf(OutFileSimBench, "\n\n");
253 
 
254 
 
255 
   //------------------------------------------------------------------------
256 
   // log file
257 
   //------------------------------------------------------------------------
258 
   fprintf(OutFileSimBench, "   //------------------------------------------------------------------------\n");
259 
   fprintf(OutFileSimBench, "   // log file\n");
260 
   fprintf(OutFileSimBench, "   //------------------------------------------------------------------------\n");
261 
   fprintf(OutFileSimBench, "   reg           simStart;\n");
262 
   fprintf(OutFileSimBench, "   integer  handleA;\n");
263 
   fprintf(OutFileSimBench, "   initial begin\n");
264 
   fprintf(OutFileSimBench, "      handleA = $fopen(\"result.out\", \"w\");\n");
265 
   fprintf(OutFileSimBench, "   end\n");
266 
   fprintf(OutFileSimBench, "\n\n");
267 
 
268 
 
269 
 
270 
   //------------------------------------------------------------------------
271 
   // RSdec Input && Output Data files
272 
   //------------------------------------------------------------------------
273 
   if ((encDecMode == 2) || (encDecMode == 3)){
274 
      fprintf(OutFileSimBench, "   //------------------------------------------------------------------------\n");
275 
      fprintf(OutFileSimBench, "   //- RSdec Input && Output Data files\n");
276 
      fprintf(OutFileSimBench, "   //------------------------------------------------------------------------\n");
277 
      fprintf(OutFileSimBench, "   reg  [23:0]   rsdecInputBank  [%d:0];\n", benchInSize);
278 
      fprintf(OutFileSimBench, "   reg  [87:0]   rsdecOutputBank [%d:0];\n", benchOutSize);
279 
      fprintf(OutFileSimBench, "\n");
280 
//      fprintf(OutFileSimBench, "   initial $readmemh(\"./RsDecIn_%d_%d_%d_%d_%d_%d_%d_%d_%d_%d_%d_%d_%d_%d_%d.hex\", rsdecInputBank);\n", DataSize, TotalSize, PrimPoly, ErasureOption,BlockAmount, ErrorRate, PowerErrorRate, ErasureRate, PowerErasureRate, bitSymbol,errorStats, passFailFlag, delayDataIn, encDecMode, encBlockAmount);
281 
//      fprintf(OutFileSimBench, "   initial $readmemh(\"./RsDecOut_%d_%d_%d_%d_%d_%d_%d_%d_%d_%d_%d_%d_%d_%d_%d.hex\", rsdecOutputBank);\n", DataSize, TotalSize, PrimPoly, ErasureOption,BlockAmount, ErrorRate, PowerErrorRate, ErasureRate, PowerErasureRate, bitSymbol,errorStats, passFailFlag, delayDataIn, encDecMode, encBlockAmount);
282 
      fprintf(OutFileSimBench, "   initial $readmemh(\"./RsDecIn.hex\", rsdecInputBank);\n");
283 
      fprintf(OutFileSimBench, "   initial $readmemh(\"./RsDecOut.hex\", rsdecOutputBank);\n");
284 
      fprintf(OutFileSimBench, "\n\n");
285 
   }
286 
 
287 
 
288 
   //------------------------------------------------------------------------
289 
   // RSenc Input && Output Data files
290 
   //------------------------------------------------------------------------
291 
   if ((encDecMode == 1) || (encDecMode == 3)){
292 
      fprintf(OutFileSimBench, "   //------------------------------------------------------------------------\n");
293 
      fprintf(OutFileSimBench, "   //- RSenc Input && Output Data files\n");
294 
      fprintf(OutFileSimBench, "   //------------------------------------------------------------------------\n");
295 
 
296 
      if (bitSymbol < 9){
297 
         fprintf(OutFileSimBench, "   reg  [15:0]   rsencInputBank  [%d:0];\n", encBenchInSize);
298 
         fprintf(OutFileSimBench, "   reg  [7:0]   rsencOutputBank  [%d:0];\n", encBenchInSize);
299 
      }else{
300 
         fprintf(OutFileSimBench, "   reg  [19:0]   rsencInputBank  [%d:0];\n", encBenchInSize);
301 
         fprintf(OutFileSimBench, "   reg  [11:0]   rsencOutputBank  [%d:0];\n", encBenchInSize);
302 
      }
303 
//      fprintf(OutFileSimBench, "   initial $readmemh(\"./RsEncIn_%d_%d_%d_%d_%d_%d_%d_%d_%d_%d_%d_%d_%d_%d_%d.hex\", rsencInputBank);\n", DataSize, TotalSize, PrimPoly, ErasureOption,BlockAmount, ErrorRate, PowerErrorRate, ErasureRate, PowerErasureRate, bitSymbol,errorStats, passFailFlag, delayDataIn, encDecMode, encBlockAmount);
304 
//      fprintf(OutFileSimBench, "   initial $readmemh(\"./RsEncOut_%d_%d_%d_%d_%d_%d_%d_%d_%d_%d_%d_%d_%d_%d_%d.hex\", rsencOutputBank);\n", DataSize, TotalSize, PrimPoly, ErasureOption,BlockAmount, ErrorRate, PowerErrorRate, ErasureRate, PowerErasureRate, bitSymbol,errorStats, passFailFlag, delayDataIn, encDecMode, encBlockAmount);
305 
      fprintf(OutFileSimBench, "   initial $readmemh(\"./RsEncIn.hex\", rsencInputBank);\n");
306 
      fprintf(OutFileSimBench, "   initial $readmemh(\"./RsEncOut.hex\", rsencOutputBank);\n");
307 
      fprintf(OutFileSimBench, "\n\n");
308 
  }
309 
 
310 
 
311 
   //--------------------------------------------------------------------------
312 
   //- simStartFF
313 
   //--------------------------------------------------------------------------
314 
   fprintf(OutFileSimBench, "   //--------------------------------------------------------------------------\n");
315 
   fprintf(OutFileSimBench, "   //- simStartFF1, simStartFF2, simStartFF3\n");
316 
   fprintf(OutFileSimBench, "   //--------------------------------------------------------------------------\n");
317 
   fprintf(OutFileSimBench, "   reg simStartFF1;\n");
318 
   fprintf(OutFileSimBench, "   reg simStartFF2;\n");
319 
   fprintf(OutFileSimBench, "   reg simStartFF3;\n");
320 
   fprintf(OutFileSimBench, "   always @(posedge CLK or negedge RESET) begin\n");
321 
   fprintf(OutFileSimBench, "      if (~RESET) begin\n");
322 
   fprintf(OutFileSimBench, "         simStartFF1 <= 1'b0;\n");
323 
   fprintf(OutFileSimBench, "         simStartFF2 <= 1'b0;\n");
324 
   fprintf(OutFileSimBench, "         simStartFF3 <= 1'b0;\n");
325 
   fprintf(OutFileSimBench, "      end\n");
326 
   fprintf(OutFileSimBench, "      else begin\n");
327 
   fprintf(OutFileSimBench, "         simStartFF1 <= simStart;\n");
328 
   fprintf(OutFileSimBench, "         simStartFF2 <= simStartFF1;\n");
329 
   fprintf(OutFileSimBench, "         simStartFF3 <= simStartFF2;\n");
330 
   fprintf(OutFileSimBench, "      end\n");
331 
   fprintf(OutFileSimBench, "   end\n");
332 
   fprintf(OutFileSimBench, "\n\n");
333 
 
334 
 
335 
   //------------------------------------------------------------------------
336 
   //+ IBankIndex
337 
   //------------------------------------------------------------------------
338 
   fprintf(OutFileSimBench, "   //------------------------------------------------------------------------\n");
339 
   fprintf(OutFileSimBench, "   //+ IBankIndex\n");
340 
   fprintf(OutFileSimBench, "   //------------------------------------------------------------------------\n");
341 
   fprintf(OutFileSimBench, "   reg [31:0]  IBankIndex;\n");
342 
   fprintf(OutFileSimBench, "   always @(posedge CLK or negedge RESET) begin\n");
343 
   fprintf(OutFileSimBench, "      if (~RESET) begin\n");
344 
   fprintf(OutFileSimBench, "         IBankIndex <= 32'd0;\n");
345 
   fprintf(OutFileSimBench, "      end\n");
346 
   fprintf(OutFileSimBench, "      else if (simStart == 1'b1) begin\n");
347 
   fprintf(OutFileSimBench, "         IBankIndex <= IBankIndex + 32'd1;\n");
348 
   fprintf(OutFileSimBench, "      end\n");
349 
   fprintf(OutFileSimBench, "   end\n");
350 
   fprintf(OutFileSimBench, "\n\n");
351 
 
352 
 
353 
   //--------------------------------------------------------------------------
354 
   //--------------------------------------------------------------------------
355 
   //--------------------------------------------------------------------------
356 
   //-  RS DECODER test Bench
357 
   //--------------------------------------------------------------------------
358 
   //--------------------------------------------------------------------------
359 
   //--------------------------------------------------------------------------
360 
   if ((encDecMode == 2) || (encDecMode == 3)){
361 
      fprintf(OutFileSimBench, "//--------------------------------------------------------------------------\n");
362 
      fprintf(OutFileSimBench, "//- RS Decoder Test Bench\n");
363 
      fprintf(OutFileSimBench, "//--------------------------------------------------------------------------\n");
364 
 
365 
 
366 
      //--------------------------------------------------------------------------
367 
      //- rsdecInput
368 
      //--------------------------------------------------------------------------
369 
      fprintf(OutFileSimBench, "   //--------------------------------------------------------------------------\n");
370 
      fprintf(OutFileSimBench, "   //- rsdecInput\n");
371 
      fprintf(OutFileSimBench, "   //--------------------------------------------------------------------------\n");
372 
      fprintf(OutFileSimBench, "   wire  [23:0] rsdecInput;\n");
373 
      fprintf(OutFileSimBench, "   assign rsdecInput = (IBankIndex < 32'd%d) ? rsdecInputBank [IBankIndex] : 24'd0;\n", benchInSize+1);
374 
      fprintf(OutFileSimBench, "\n\n");
375 
 
376 
 
377 
      //------------------------------------------------------------------------
378 
      //+ rsdecSync
379 
      //------------------------------------------------------------------------
380 
      fprintf(OutFileSimBench, "   //------------------------------------------------------------------------\n");
381 
      fprintf(OutFileSimBench, "   //+ rsdecSync\n");
382 
      fprintf(OutFileSimBench, "   //------------------------------------------------------------------------\n");
383 
      fprintf(OutFileSimBench, "   always @(posedge CLK or negedge RESET) begin\n");
384 
      fprintf(OutFileSimBench, "      if (~RESET) begin\n");
385 
      fprintf(OutFileSimBench, "         rsdecSync <= 1'b0;\n");
386 
      fprintf(OutFileSimBench, "      end\n");
387 
      fprintf(OutFileSimBench, "      else if (simStart == 1'b1) begin\n");
388 
      fprintf(OutFileSimBench, "         rsdecSync <= rsdecInput[20];\n");
389 
      fprintf(OutFileSimBench, "      end\n");
390 
      fprintf(OutFileSimBench, "   end\n");
391 
      fprintf(OutFileSimBench, "\n\n");
392 
 
393 
 
394 
      //------------------------------------------------------------------------
395 
      //+ rsdecEnable
396 
      //------------------------------------------------------------------------
397 
      fprintf(OutFileSimBench, "   //------------------------------------------------------------------------\n");
398 
      fprintf(OutFileSimBench, "   //+ rsdecEnable\n");
399 
      fprintf(OutFileSimBench, "   //------------------------------------------------------------------------\n");
400 
      fprintf(OutFileSimBench, "   always @(posedge CLK or negedge RESET) begin\n");
401 
      fprintf(OutFileSimBench, "      if (~RESET) begin\n");
402 
      fprintf(OutFileSimBench, "         rsdecEnable <= 1'b0;\n");
403 
      fprintf(OutFileSimBench, "      end\n");
404 
      fprintf(OutFileSimBench, "      else if (simStart == 1'b1) begin\n");
405 
      fprintf(OutFileSimBench, "         rsdecEnable <= rsdecInput[16];\n");
406 
      fprintf(OutFileSimBench, "      end\n");
407 
      fprintf(OutFileSimBench, "   end\n");
408 
      fprintf(OutFileSimBench, "\n\n");
409 
 
410 
 
411 
      //------------------------------------------------------------------------
412 
      //+ rsdecErasureIn
413 
      //------------------------------------------------------------------------
414 
      fprintf(OutFileSimBench, "   //------------------------------------------------------------------------\n");
415 
      fprintf(OutFileSimBench, "   //+ rsdecErasureIn\n");
416 
      fprintf(OutFileSimBench, "   //------------------------------------------------------------------------\n");
417 
      fprintf(OutFileSimBench, "   always @(posedge CLK or negedge RESET) begin\n");
418 
      fprintf(OutFileSimBench, "      if (~RESET) begin\n");
419 
      fprintf(OutFileSimBench, "         rsdecErasureIn <= 1'b0;\n");
420 
      fprintf(OutFileSimBench, "      end\n");
421 
      fprintf(OutFileSimBench, "      else begin\n");
422 
      fprintf(OutFileSimBench, "         rsdecErasureIn <= rsdecInput[12];\n");
423 
      fprintf(OutFileSimBench, "      end\n");
424 
      fprintf(OutFileSimBench, "   end\n");
425 
      fprintf(OutFileSimBench, "\n\n");
426 
 
427 
 
428 
      //------------------------------------------------------------------------
429 
      //+ rsdecDataIn
430 
      //------------------------------------------------------------------------
431 
      fprintf(OutFileSimBench, "   //------------------------------------------------------------------------\n");
432 
      fprintf(OutFileSimBench, "   //+ rsdecDataIn\n");
433 
      fprintf(OutFileSimBench, "   //------------------------------------------------------------------------\n");
434 
      fprintf(OutFileSimBench, "   always @(posedge CLK or negedge RESET) begin\n");
435 
      fprintf(OutFileSimBench, "      if (~RESET) begin\n");
436 
      fprintf(OutFileSimBench, "         rsdecDataIn <= %d'd0;\n", bitSymbol);
437 
      fprintf(OutFileSimBench, "      end\n");
438 
      fprintf(OutFileSimBench, "      else begin\n");
439 
      fprintf(OutFileSimBench, "         rsdecDataIn <= rsdecInput[%d:0];\n", bitSymbol-1);
440 
      fprintf(OutFileSimBench, "      end\n");
441 
      fprintf(OutFileSimBench, "   end\n");
442 
      fprintf(OutFileSimBench, "\n\n");
443 
 
444 
 
445 
      //------------------------------------------------------------------------
446 
      //+ rsdecOBankIndex
447 
      //------------------------------------------------------------------------
448 
      fprintf(OutFileSimBench, "   //------------------------------------------------------------------------\n");
449 
      fprintf(OutFileSimBench, "   //+ rsdecOBankIndex\n");
450 
      fprintf(OutFileSimBench, "   //------------------------------------------------------------------------\n");
451 
      fprintf(OutFileSimBench, "   reg [31:0]  rsdecOBankIndex;\n");
452 
      fprintf(OutFileSimBench, "   always @(posedge CLK or negedge RESET) begin\n");
453 
      fprintf(OutFileSimBench, "      if (~RESET) begin\n");
454 
      fprintf(OutFileSimBench, "         rsdecOBankIndex <= 32'd0;\n");
455 
      fprintf(OutFileSimBench, "      end\n");
456 
      fprintf(OutFileSimBench, "      else if (rsdecOutEnable == 1'b1) begin\n");
457 
      fprintf(OutFileSimBench, "         rsdecOBankIndex <= rsdecOBankIndex + 32'd1;\n");
458 
      fprintf(OutFileSimBench, "      end\n");
459 
      fprintf(OutFileSimBench, "   end\n");
460 
      fprintf(OutFileSimBench, "\n\n");
461 
 
462 
 
463 
      //--------------------------------------------------------------------------
464 
      //- rsdecOutput
465 
      //--------------------------------------------------------------------------
466 
      fprintf(OutFileSimBench, "   //--------------------------------------------------------------------------\n");
467 
      fprintf(OutFileSimBench, "   //- rsdecOutput\n");
468 
      fprintf(OutFileSimBench, "   //--------------------------------------------------------------------------\n");
469 
      fprintf(OutFileSimBench, "   wire  [87:0] rsdecOutput;\n");
470 
      fprintf(OutFileSimBench, "   assign rsdecOutput = (rsdecOBankIndex < 32'd%d) ? rsdecOutputBank [rsdecOBankIndex] : 48'd0;\n", benchOutSize+1);
471 
      fprintf(OutFileSimBench, "\n\n");
472 
 
473 
 
474 
      //--------------------------------------------------------------------------
475 
      //+ rsdecExpNumError
476 
      //--------------------------------------------------------------------------
477 
      fprintf(OutFileSimBench, "   //--------------------------------------------------------------------------\n");
478 
      fprintf(OutFileSimBench, "   //+ rsdecExpNumError\n");
479 
      fprintf(OutFileSimBench, "   //--------------------------------------------------------------------------\n");
480 
      fprintf(OutFileSimBench, "   reg [%d:0]   rsdecExpNumError;\n", bitSymbol-1);
481 
      fprintf(OutFileSimBench, "   always @(posedge CLK or negedge RESET) begin\n");
482 
      fprintf(OutFileSimBench, "      if (~RESET) begin\n");
483 
      fprintf(OutFileSimBench, "         rsdecExpNumError <= %d'd0;\n", bitSymbol);
484 
      fprintf(OutFileSimBench, "      end\n");
485 
      fprintf(OutFileSimBench, "      else if (rsdecOutEnable == 1'b1) begin\n");
486 
      fprintf(OutFileSimBench, "         rsdecExpNumError <= rsdecOutput[47:36];\n");
487 
      fprintf(OutFileSimBench, "      end\n");
488 
      fprintf(OutFileSimBench, "      else begin\n");
489 
      fprintf(OutFileSimBench, "         rsdecExpNumError <= %d'd0;\n", bitSymbol);
490 
      fprintf(OutFileSimBench, "      end\n");
491 
      fprintf(OutFileSimBench, "   end\n");
492 
      fprintf(OutFileSimBench, "\n\n");
493 
 
494 
 
495 
      //--------------------------------------------------------------------------
496 
      //+ rsdecTheoricalNumError
497 
      //--------------------------------------------------------------------------
498 
      fprintf(OutFileSimBench, "   //--------------------------------------------------------------------------\n");
499 
      fprintf(OutFileSimBench, "   //+ rsdecTheoricalNumError\n");
500 
      fprintf(OutFileSimBench, "   //--------------------------------------------------------------------------\n");
501 
      fprintf(OutFileSimBench, "   reg [%d:0]   rsdecTheoricalNumError;\n", bitSymbol-1);
502 
      fprintf(OutFileSimBench, "   always @(posedge CLK or negedge RESET) begin\n");
503 
      fprintf(OutFileSimBench, "      if (~RESET) begin\n");
504 
      fprintf(OutFileSimBench, "         rsdecTheoricalNumError <= %d'd0;\n", bitSymbol);
505 
      fprintf(OutFileSimBench, "      end\n");
506 
      fprintf(OutFileSimBench, "      else if (rsdecOutEnable == 1'b1) begin\n");
507 
      fprintf(OutFileSimBench, "         rsdecTheoricalNumError <= rsdecOutput[75:64];\n");
508 
      fprintf(OutFileSimBench, "      end\n");
509 
      fprintf(OutFileSimBench, "      else begin\n");
510 
      fprintf(OutFileSimBench, "         rsdecTheoricalNumError <= %d'd0;\n", bitSymbol);
511 
      fprintf(OutFileSimBench, "      end\n");
512 
      fprintf(OutFileSimBench, "   end\n");
513 
      fprintf(OutFileSimBench, "\n\n");
514 
 
515 
 
516 
      //--------------------------------------------------------------------------
517 
      //+ rsdecExpNumErasure
518 
      //--------------------------------------------------------------------------
519 
      fprintf(OutFileSimBench, "   //--------------------------------------------------------------------------\n");
520 
      fprintf(OutFileSimBench, "   //+ rsdecExpNumErasure\n");
521 
      fprintf(OutFileSimBench, "   //--------------------------------------------------------------------------\n");
522 
      fprintf(OutFileSimBench, "   reg [%d:0]   rsdecExpNumErasure;\n", bitSymbol-1);
523 
      fprintf(OutFileSimBench, "   always @(posedge CLK or negedge RESET) begin\n");
524 
      fprintf(OutFileSimBench, "      if (~RESET) begin\n");
525 
      fprintf(OutFileSimBench, "         rsdecExpNumErasure <= %d'd0;\n", bitSymbol);
526 
      fprintf(OutFileSimBench, "      end\n");
527 
      fprintf(OutFileSimBench, "      else if (rsdecOutEnable == 1'b1) begin\n");
528 
 
529 
      switch(bitSymbol)
530 
      {
531 
         case (3):
532 
            fprintf(OutFileSimBench, "         rsdecExpNumErasure <= rsdecOutput[26:24];\n");
533 
         break;
534 
         case (4):
535 
            fprintf(OutFileSimBench, "         rsdecExpNumErasure <= rsdecOutput[27:24];\n");
536 
         break;
537 
         case (5):
538 
            fprintf(OutFileSimBench, "         rsdecExpNumErasure <= rsdecOutput[28:24];\n");
539 
         break;
540 
         case (6):
541 
            fprintf(OutFileSimBench, "         rsdecExpNumErasure <= rsdecOutput[29:24];\n");
542 
         break;
543 
         case (7):
544 
            fprintf(OutFileSimBench, "         rsdecExpNumErasure <= rsdecOutput[30:24];\n");
545 
         break;
546 
         case (8):
547 
            fprintf(OutFileSimBench, "         rsdecExpNumErasure <= rsdecOutput[31:24];\n");
548 
         break;
549 
         case (9):
550 
            fprintf(OutFileSimBench, "         rsdecExpNumErasure <= rsdecOutput[32:24];\n");
551 
         break;
552 
         case (10):
553 
            fprintf(OutFileSimBench, "         rsdecExpNumErasure <= rsdecOutput[33:24];\n");
554 
         break;
555 
         case (11):
556 
            fprintf(OutFileSimBench, "         rsdecExpNumErasure <= rsdecOutput[34:24];\n");
557 
         break;
558 
         case (12):
559 
             fprintf(OutFileSimBench, "         rsdecExpNumErasure <= rsdecOutput[35:24];\n");
560 
         break;
561 
         default :
562 
             fprintf(OutFileSimBench, "         rsdecExpNumErasure <= 0;\n");
563 
         break;
564 
      }
565 
 
566 
      fprintf(OutFileSimBench, "      end\n");
567 
      fprintf(OutFileSimBench, "      else begin\n");
568 
      fprintf(OutFileSimBench, "         rsdecExpNumErasure <= %d'd0;\n", bitSymbol);
569 
      fprintf(OutFileSimBench, "      end\n");
570 
      fprintf(OutFileSimBench, "   end\n");
571 
      fprintf(OutFileSimBench, "\n\n");
572 
 
573 
 
574 
 
575 
      //--------------------------------------------------------------------------
576 
      //+ rsdecTheoricalNumErasure
577 
      //--------------------------------------------------------------------------
578 
      fprintf(OutFileSimBench, "   //--------------------------------------------------------------------------\n");
579 
      fprintf(OutFileSimBench, "   //+ rsdecTheoricalNumErasure\n");
580 
      fprintf(OutFileSimBench, "   //--------------------------------------------------------------------------\n");
581 
      fprintf(OutFileSimBench, "   reg [%d:0]   rsdecTheoricalNumErasure;\n", bitSymbol-1);
582 
      fprintf(OutFileSimBench, "   always @(posedge CLK or negedge RESET) begin\n");
583 
      fprintf(OutFileSimBench, "      if (~RESET) begin\n");
584 
      fprintf(OutFileSimBench, "         rsdecTheoricalNumErasure <= %d'd0;\n", bitSymbol);
585 
      fprintf(OutFileSimBench, "      end\n");
586 
      fprintf(OutFileSimBench, "      else if (rsdecOutEnable == 1'b1) begin\n");
587 
 
588 
         switch(bitSymbol)
589 
         {
590 
         case (3):
591 
            fprintf(OutFileSimBench, "         rsdecTheoricalNumErasure <= rsdecOutput[54:52];\n");
592 
         break;
593 
         case (4):
594 
            fprintf(OutFileSimBench, "         rsdecTheoricalNumErasure <= rsdecOutput[55:52];\n");
595 
         break;
596 
         case (5):
597 
            fprintf(OutFileSimBench, "         rsdecTheoricalNumErasure <= rsdecOutput[56:52];\n");
598 
         break;
599 
         case (6):
600 
            fprintf(OutFileSimBench, "         rsdecTheoricalNumErasure <= rsdecOutput[57:52];\n");
601 
         break;
602 
         case (7):
603 
            fprintf(OutFileSimBench, "         rsdecTheoricalNumErasure <= rsdecOutput[58:52];\n");
604 
         break;
605 
         case (8):
606 
            fprintf(OutFileSimBench, "         rsdecTheoricalNumErasure <= rsdecOutput[59:52];\n");
607 
         break;
608 
         case (9):
609 
            fprintf(OutFileSimBench, "         rsdecTheoricalNumErasure <= rsdecOutput[60:52];\n");
610 
         break;
611 
         case (10):
612 
            fprintf(OutFileSimBench, "         rsdecTheoricalNumErasure <= rsdecOutput[61:52];\n");
613 
         break;
614 
         case (11):
615 
            fprintf(OutFileSimBench, "         rsdecTheoricalNumErasure <= rsdecOutput[62:52];\n");
616 
         break;
617 
         case (12):
618 
             fprintf(OutFileSimBench, "         rsdecTheoricalNumErasure <= rsdecOutput[63:52];\n");
619 
         break;
620 
         default :
621 
             fprintf(OutFileSimBench, "         rsdecTheoricalNumErasure <= 0;\n");
622 
         break;
623 
         }
624 
 
625 
 
626 
      fprintf(OutFileSimBench, "      end\n");
627 
      fprintf(OutFileSimBench, "      else begin\n");
628 
      fprintf(OutFileSimBench, "         rsdecTheoricalNumErasure <= %d'd0;\n", bitSymbol);
629 
      fprintf(OutFileSimBench, "      end\n");
630 
      fprintf(OutFileSimBench, "   end\n");
631 
      fprintf(OutFileSimBench, "\n\n");
632 
 
633 
 
634 
      //--------------------------------------------------------------------------
635 
      //+ rsdecTheoricalSyndromeLength
636 
      //--------------------------------------------------------------------------
637 
      fprintf(OutFileSimBench, "   //--------------------------------------------------------------------------\n");
638 
      fprintf(OutFileSimBench, "   //+ rsdecTheoricalSyndromeLength\n");
639 
      fprintf(OutFileSimBench, "   //--------------------------------------------------------------------------\n");
640 
      fprintf(OutFileSimBench, "   reg [%d:0]   rsdecTheoricalSyndromeLength;\n", 12);
641 
      fprintf(OutFileSimBench, "   always @(posedge CLK or negedge RESET) begin\n");
642 
      fprintf(OutFileSimBench, "      if (~RESET) begin\n");
643 
      fprintf(OutFileSimBench, "         rsdecTheoricalSyndromeLength <= %d'd0;\n", 13);
644 
      fprintf(OutFileSimBench, "      end\n");
645 
      fprintf(OutFileSimBench, "      else if (rsdecOutEnable == 1'b1) begin\n");
646 
      fprintf(OutFileSimBench, "         rsdecTheoricalSyndromeLength <= {1'b0, rsdecOutput[87:76]};\n");
647 
      fprintf(OutFileSimBench, "      end\n");
648 
      fprintf(OutFileSimBench, "      else begin\n");
649 
      fprintf(OutFileSimBench, "         rsdecTheoricalSyndromeLength <= %d'd0;\n", 13);
650 
      fprintf(OutFileSimBench, "      end\n");
651 
      fprintf(OutFileSimBench, "   end\n");
652 
      fprintf(OutFileSimBench, "\n\n");
653 
 
654 
 
655 
      //--------------------------------------------------------------------------
656 
      //+ rsdecExpFailFlag
657 
      //--------------------------------------------------------------------------
658 
      fprintf(OutFileSimBench, "   //--------------------------------------------------------------------------\n");
659 
      fprintf(OutFileSimBench, "   //+ rsdecExpFailFlag\n");
660 
      fprintf(OutFileSimBench, "   //--------------------------------------------------------------------------\n");
661 
      fprintf(OutFileSimBench, "   reg       rsdecExpFailFlag;\n");
662 
      fprintf(OutFileSimBench, "   always @(posedge CLK or negedge RESET) begin\n");
663 
      fprintf(OutFileSimBench, "      if (~RESET) begin\n");
664 
      fprintf(OutFileSimBench, "         rsdecExpFailFlag <= 1'b0;\n");
665 
      fprintf(OutFileSimBench, "      end\n");
666 
      fprintf(OutFileSimBench, "      else if (rsdecOutEnable == 1'b1) begin\n");
667 
      fprintf(OutFileSimBench, "         rsdecExpFailFlag <= rsdecOutput[48];\n");
668 
      fprintf(OutFileSimBench, "      end\n");
669 
      fprintf(OutFileSimBench, "   end\n");
670 
 
671 
 
672 
      //--------------------------------------------------------------------------
673 
      //+ rsdecExpData
674 
      //--------------------------------------------------------------------------
675 
      fprintf(OutFileSimBench, "   //--------------------------------------------------------------------------\n");
676 
      fprintf(OutFileSimBench, "   //+ rsdecExpData\n");
677 
      fprintf(OutFileSimBench, "   //--------------------------------------------------------------------------\n");
678 
      fprintf(OutFileSimBench, "   reg [%d:0]   rsdecExpData;\n", bitSymbol-1);
679 
      fprintf(OutFileSimBench, "   always @(posedge CLK or negedge RESET) begin\n");
680 
      fprintf(OutFileSimBench, "      if (~RESET) begin\n");
681 
      fprintf(OutFileSimBench, "         rsdecExpData <= %d'd0;\n", bitSymbol);
682 
      fprintf(OutFileSimBench, "      end\n");
683 
      fprintf(OutFileSimBench, "      else if (rsdecOutEnable == 1'b1) begin\n");
684 
      fprintf(OutFileSimBench, "         rsdecExpData <= rsdecOutput[%d:0];\n", bitSymbol-1);
685 
      fprintf(OutFileSimBench, "      end\n");
686 
      fprintf(OutFileSimBench, "      else begin\n");
687 
      fprintf(OutFileSimBench, "         rsdecExpData <= %d'd0;\n", bitSymbol);
688 
      fprintf(OutFileSimBench, "      end\n");
689 
      fprintf(OutFileSimBench, "   end\n");
690 
      fprintf(OutFileSimBench, "\n\n");
691 
 
692 
 
693 
      //--------------------------------------------------------------------------
694 
      //+ rsdecExpDelayedData
695 
      //--------------------------------------------------------------------------
696 
      if (delayDataIn == 1){
697 
         fprintf(OutFileSimBench, "   //--------------------------------------------------------------------------\n");
698 
         fprintf(OutFileSimBench, "   //+ rsdecExpDelayedData\n");
699 
         fprintf(OutFileSimBench, "   //--------------------------------------------------------------------------\n");
700 
         fprintf(OutFileSimBench, "   reg [%d:0]   rsdecExpDelayedData;\n", bitSymbol-1);
701 
         fprintf(OutFileSimBench, "   always @(posedge CLK or negedge RESET) begin\n");
702 
         fprintf(OutFileSimBench, "      if (~RESET) begin\n");
703 
         fprintf(OutFileSimBench, "         rsdecExpDelayedData <= %d'd0;\n", bitSymbol);
704 
         fprintf(OutFileSimBench, "      end\n");
705 
         fprintf(OutFileSimBench, "      else if (rsdecOutEnable == 1'b1) begin\n");
706 
         fprintf(OutFileSimBench, "         rsdecExpDelayedData <= rsdecOutput[%d:12];\n", bitSymbol+11);
707 
         fprintf(OutFileSimBench, "      end\n");
708 
         fprintf(OutFileSimBench, "      else begin\n");
709 
         fprintf(OutFileSimBench, "         rsdecExpDelayedData <= %d'd0;\n", bitSymbol);
710 
         fprintf(OutFileSimBench, "      end\n");
711 
         fprintf(OutFileSimBench, "   end\n");
712 
         fprintf(OutFileSimBench, "\n\n");
713 
      }
714 
 
715 
 
716 
      //--------------------------------------------------------------------------
717 
      //+ rsdecOutDataFF, rsdecOutEnableFF
718 
      //--------------------------------------------------------------------------
719 
      fprintf(OutFileSimBench, "   //--------------------------------------------------------------------------\n");
720 
      fprintf(OutFileSimBench, "   //+ rsdecOutDataFF, rsdecOutEnableFF\n");
721 
      fprintf(OutFileSimBench, "   //--------------------------------------------------------------------------\n");
722 
      fprintf(OutFileSimBench, "   reg [%d:0] rsdecOutDataFF;\n", bitSymbol -1);
723 
      fprintf(OutFileSimBench, "   reg       rsdecOutEnableFF;\n");
724 
 
725 
      if (errorStats == 1) {
726 
         fprintf(OutFileSimBench, "   reg [%d:0]   rsdecErrorNumFF;\n", bitSymbol-1);
727 
         fprintf(OutFileSimBench, "   reg [%d:0]   rsdecErasureNumFF;\n", bitSymbol-1);
728 
      }
729 
 
730 
      if (passFailFlag == 1){
731 
         fprintf(OutFileSimBench, "   reg         rsdecFailFF;\n");
732 
      }
733 
 
734 
 
735 
 
736 
      if (delayDataIn == 1){
737 
         fprintf(OutFileSimBench, "   reg [%d:0] rsdecDelayedDataFF;\n", bitSymbol -1);
738 
      }
739 
 
740 
 
741 
      fprintf(OutFileSimBench, "   always @(posedge CLK or negedge RESET) begin\n");
742 
      fprintf(OutFileSimBench, "      if (~RESET) begin\n");
743 
      fprintf(OutFileSimBench, "         rsdecOutDataFF <= %d'd0;\n",bitSymbol );
744 
      fprintf(OutFileSimBench, "         rsdecOutEnableFF <= 1'b0;\n");
745 
      if (delayDataIn == 1){
746 
         fprintf(OutFileSimBench, "         rsdecDelayedDataFF <= %d'd0;\n",bitSymbol );
747 
      }
748 
      if (errorStats == 1) {
749 
         fprintf(OutFileSimBench, "         rsdecErrorNumFF <= %d'd0;\n",bitSymbol );
750 
         fprintf(OutFileSimBench, "         rsdecErasureNumFF <= %d'd0;\n",bitSymbol );
751 
      }
752 
      if (passFailFlag == 1){
753 
         fprintf(OutFileSimBench, "         rsdecFailFF <= 1'b0;\n");
754 
      }
755 
 
756 
 
757 
      fprintf(OutFileSimBench, "      end\n");
758 
      fprintf(OutFileSimBench, "      else begin\n");
759 
      fprintf(OutFileSimBench, "         rsdecOutDataFF <= rsdecOutData;\n");
760 
      fprintf(OutFileSimBench, "         rsdecOutEnableFF <= rsdecOutEnable;\n");
761 
      if (delayDataIn == 1){
762 
         fprintf(OutFileSimBench, "         rsdecDelayedDataFF <= rsdecDelayedData;\n");
763 
      }
764 
      if (errorStats == 1) {
765 
         fprintf(OutFileSimBench, "         rsdecErrorNumFF <= rsdecErrorNum;\n");
766 
         fprintf(OutFileSimBench, "         rsdecErasureNumFF <= rsdecErasureNum;\n");
767 
      }
768 
      if (passFailFlag == 1){
769 
         fprintf(OutFileSimBench, "         rsdecFailFF <= rsdecFail;\n");
770 
      }
771 
      fprintf(OutFileSimBench, "      end\n");
772 
      fprintf(OutFileSimBench, "   end\n");
773 
      fprintf(OutFileSimBench, "\n\n");
774 
 
775 
 
776 
      //--------------------------------------------------------------------------
777 
      //+ rsDecDelayedDataFlag, rsDecNGDelayedDataFlag
778 
      //--------------------------------------------------------------------------
779 
      if (delayDataIn == 1){
780 
         fprintf(OutFileSimBench, "   //--------------------------------------------------------------------------\n");
781 
         fprintf(OutFileSimBench, "   //+ rsDecDelayedDataFlag, rsDecNGDelayedDataFlag\n");
782 
         fprintf(OutFileSimBench, "   //--------------------------------------------------------------------------\n");
783 
         fprintf(OutFileSimBench, "   reg   rsDecDelayedDataFlag;\n");
784 
         fprintf(OutFileSimBench, "   reg   rsDecNGDelayedDataFlag;\n");
785 
         fprintf(OutFileSimBench, "   always @(posedge CLK or negedge RESET) begin\n");
786 
         fprintf(OutFileSimBench, "      if (~RESET) begin\n");
787 
         fprintf(OutFileSimBench, "         rsDecDelayedDataFlag <= 1'b0;\n");
788 
         fprintf(OutFileSimBench, "         rsDecNGDelayedDataFlag   <= 1'b0;\n");
789 
         fprintf(OutFileSimBench, "      end\n");
790 
         fprintf(OutFileSimBench, "      else if (rsdecOutEnableFF == 1'b1) begin\n");
791 
         fprintf(OutFileSimBench, "         if (rsdecDelayedDataFF == rsdecExpDelayedData) begin\n");
792 
         fprintf(OutFileSimBench, "            rsDecDelayedDataFlag <= 1'b0;\n");
793 
         fprintf(OutFileSimBench, "         end\n");
794 
         fprintf(OutFileSimBench, "         else begin\n");
795 
         fprintf(OutFileSimBench, "            rsDecDelayedDataFlag <= 1'b1;\n");
796 
         fprintf(OutFileSimBench, "            rsDecNGDelayedDataFlag   <= 1'b1;\n");
797 
         fprintf(OutFileSimBench, "            $fdisplay(handleA,\"Reed Solomon Decoder: Delayed Data Pin NG!!!!\");\n");
798 
         fprintf(OutFileSimBench, "         end\n");
799 
         fprintf(OutFileSimBench, "      end\n");
800 
         fprintf(OutFileSimBench, "      else begin\n");
801 
         fprintf(OutFileSimBench, "         rsDecDelayedDataFlag <= 1'b0;\n");
802 
         fprintf(OutFileSimBench, "      end\n");
803 
         fprintf(OutFileSimBench, "   end\n");
804 
         fprintf(OutFileSimBench, "\n\n\n\n\n\n");
805 
      }
806 
 
807 
 
808 
      //--------------------------------------------------------------------------
809 
      //+ rsDecDataFlag, rsDecNGDataFlag
810 
      //--------------------------------------------------------------------------
811 
      fprintf(OutFileSimBench, "   //--------------------------------------------------------------------------\n");
812 
      fprintf(OutFileSimBench, "   //+ rsDecDataFlag, rsDecNGDataFlag\n");
813 
      fprintf(OutFileSimBench, "   //--------------------------------------------------------------------------\n");
814 
      fprintf(OutFileSimBench, "   reg   rsDecDataFlag;\n");
815 
      fprintf(OutFileSimBench, "   reg   rsDecNGDataFlag;\n");
816 
      fprintf(OutFileSimBench, "   always @(posedge CLK or negedge RESET) begin\n");
817 
      fprintf(OutFileSimBench, "      if (~RESET) begin\n");
818 
      fprintf(OutFileSimBench, "         rsDecDataFlag <= 1'b0;\n");
819 
      fprintf(OutFileSimBench, "         rsDecNGDataFlag   <= 1'b0;\n");
820 
      fprintf(OutFileSimBench, "      end\n");
821 
      fprintf(OutFileSimBench, "      else if (rsdecOutEnableFF == 1'b1) begin\n");
822 
      fprintf(OutFileSimBench, "         if (rsdecOutDataFF == rsdecExpData) begin\n");
823 
      fprintf(OutFileSimBench, "            rsDecDataFlag <= 1'b0;\n");
824 
      fprintf(OutFileSimBench, "         end\n");
825 
      fprintf(OutFileSimBench, "         else begin\n");
826 
      fprintf(OutFileSimBench, "            rsDecDataFlag <= 1'b1;\n");
827 
      fprintf(OutFileSimBench, "            rsDecNGDataFlag   <= 1'b1;\n");
828 
      fprintf(OutFileSimBench, "            $fdisplay(handleA,\"Reed Solomon Decoder Data Out: NG!!!!\");\n");
829 
      fprintf(OutFileSimBench, "         end\n");
830 
      fprintf(OutFileSimBench, "      end\n");
831 
      fprintf(OutFileSimBench, "      else begin\n");
832 
      fprintf(OutFileSimBench, "         rsDecDataFlag <= 1'b0;\n");
833 
      fprintf(OutFileSimBench, "      end\n");
834 
      fprintf(OutFileSimBench, "   end\n");
835 
      fprintf(OutFileSimBench, "\n\n\n");
836 
 
837 
 
838 
      //--------------------------------------------------------------------------
839 
      //+ rsDecErasureFlag, rsDecNGErasureFlag
840 
      //--------------------------------------------------------------------------
841 
if (errorStats == 1) {
842 
   if (ErasureOption == 1) {
843 
      fprintf(OutFileSimBench, "   //--------------------------------------------------------------------------\n");
844 
      fprintf(OutFileSimBench, "   //+ rsDecErasureFlag, rsDecNGErasureFlag\n");
845 
      fprintf(OutFileSimBench, "   //--------------------------------------------------------------------------\n");
846 
      fprintf(OutFileSimBench, "   reg   rsDecErasureFlag;\n");
847 
      fprintf(OutFileSimBench, "   reg   rsDecNGErasureFlag;\n");
848 
      fprintf(OutFileSimBench, "   always @(posedge CLK or negedge RESET) begin\n");
849 
      fprintf(OutFileSimBench, "      if (~RESET) begin\n");
850 
      fprintf(OutFileSimBench, "         rsDecErasureFlag <= 1'b0;\n");
851 
      fprintf(OutFileSimBench, "         rsDecNGErasureFlag   <= 1'b0;\n");
852 
      fprintf(OutFileSimBench, "      end\n");
853 
      fprintf(OutFileSimBench, "      else if (rsdecOutEnableFF == 1'b1) begin\n");
854 
      fprintf(OutFileSimBench, "         if (rsdecErasureNumFF == rsdecExpNumErasure) begin\n");
855 
      fprintf(OutFileSimBench, "            rsDecErasureFlag <= 1'b0;\n");
856 
      fprintf(OutFileSimBench, "         end\n");
857 
      fprintf(OutFileSimBench, "         else begin\n");
858 
      fprintf(OutFileSimBench, "            rsDecErasureFlag <= 1'b1;\n");
859 
      fprintf(OutFileSimBench, "            rsDecNGErasureFlag   <= 1'b1;\n");
860 
      fprintf(OutFileSimBench, "            $fdisplay(handleA,\"Reed Solomon Decoder Erasure Pin: NG!!!!\");\n");
861 
      fprintf(OutFileSimBench, "         end\n");
862 
      fprintf(OutFileSimBench, "      end\n");
863 
      fprintf(OutFileSimBench, "      else begin\n");
864 
      fprintf(OutFileSimBench, "         rsDecErasureFlag <= 1'b0;\n");
865 
      fprintf(OutFileSimBench, "      end\n");
866 
      fprintf(OutFileSimBench, "   end\n");
867 
      fprintf(OutFileSimBench, "\n\n\n");
868 
   }
869 
 
870 
 
871 
      //--------------------------------------------------------------------------
872 
      //+ rsDecErrorFlag, rsDecNGErrorFlag
873 
      //--------------------------------------------------------------------------
874 
      fprintf(OutFileSimBench, "   //--------------------------------------------------------------------------\n");
875 
      fprintf(OutFileSimBench, "   //+ rsDecErrorFlag, rsDecNGErrorFlag\n");
876 
      fprintf(OutFileSimBench, "   //--------------------------------------------------------------------------\n");
877 
      fprintf(OutFileSimBench, "   reg   rsDecErrorFlag;\n");
878 
      fprintf(OutFileSimBench, "   reg   rsDecNGErrorFlag;\n");
879 
      fprintf(OutFileSimBench, "   always @(posedge CLK or negedge RESET) begin\n");
880 
      fprintf(OutFileSimBench, "      if (~RESET) begin\n");
881 
      fprintf(OutFileSimBench, "         rsDecErrorFlag <= 1'b0;\n");
882 
      fprintf(OutFileSimBench, "         rsDecNGErrorFlag   <= 1'b0;\n");
883 
      fprintf(OutFileSimBench, "      end\n");
884 
      fprintf(OutFileSimBench, "      else if (rsdecOutEnableFF == 1'b1) begin\n");
885 
      fprintf(OutFileSimBench, "         if (rsdecErrorNumFF == rsdecExpNumError) begin\n");
886 
      fprintf(OutFileSimBench, "            rsDecErrorFlag <= 1'b0;\n");
887 
      fprintf(OutFileSimBench, "         end\n");
888 
      fprintf(OutFileSimBench, "         else begin\n");
889 
      fprintf(OutFileSimBench, "            rsDecErrorFlag <= 1'b1;\n");
890 
      fprintf(OutFileSimBench, "            rsDecNGErrorFlag   <= 1'b1;\n");
891 
      fprintf(OutFileSimBench, "            $fdisplay(handleA,\"Reed Solomon Decoder Error Pin : NG!!!!\");\n");
892 
      fprintf(OutFileSimBench, "         end\n");
893 
      fprintf(OutFileSimBench, "      end\n");
894 
      fprintf(OutFileSimBench, "      else begin\n");
895 
      fprintf(OutFileSimBench, "         rsDecErrorFlag <= 1'b0;\n");
896 
      fprintf(OutFileSimBench, "      end\n");
897 
      fprintf(OutFileSimBench, "   end\n");
898 
      fprintf(OutFileSimBench, "\n\n\n");
899 
}
900 
 
901 
 
902 
 
903 
   if (passFailFlag == 1){
904 
      //--------------------------------------------------------------------------
905 
      //+ rsDecFailPinFlag, rsDecNGFailPinFlag
906 
      //--------------------------------------------------------------------------
907 
      fprintf(OutFileSimBench, "   //--------------------------------------------------------------------------\n");
908 
      fprintf(OutFileSimBench, "   //+ rsDecFailPinFlag, rsDecNGFailPinFlag\n");
909 
      fprintf(OutFileSimBench, "   //--------------------------------------------------------------------------\n");
910 
      fprintf(OutFileSimBench, "   reg   rsDecFailPinFlag;\n");
911 
      fprintf(OutFileSimBench, "   reg   rsDecNGFailPinFlag;\n");
912 
      fprintf(OutFileSimBench, "   always @(posedge CLK or negedge RESET) begin\n");
913 
      fprintf(OutFileSimBench, "      if (~RESET) begin\n");
914 
      fprintf(OutFileSimBench, "         rsDecFailPinFlag <= 1'b0;\n");
915 
      fprintf(OutFileSimBench, "         rsDecNGFailPinFlag   <= 1'b0;\n");
916 
      fprintf(OutFileSimBench, "      end\n");
917 
      fprintf(OutFileSimBench, "      else if (rsdecOutEnableFF == 1'b1) begin\n");
918 
      fprintf(OutFileSimBench, "         if (rsdecFailFF == rsdecExpFailFlag) begin\n");
919 
      fprintf(OutFileSimBench, "            rsDecFailPinFlag <= 1'b0;\n");
920 
      fprintf(OutFileSimBench, "         end\n");
921 
      fprintf(OutFileSimBench, "         else begin\n");
922 
      fprintf(OutFileSimBench, "            rsDecFailPinFlag <= 1'b1;\n");
923 
      fprintf(OutFileSimBench, "            rsDecNGFailPinFlag   <= 1'b1;\n");
924 
      fprintf(OutFileSimBench, "            $fdisplay(handleA,\"Reed Solomon Decoder Pass Fail Pin : NG!!!!\");\n");
925 
      fprintf(OutFileSimBench, "         end\n");
926 
      fprintf(OutFileSimBench, "      end\n");
927 
      fprintf(OutFileSimBench, "      else begin\n");
928 
      fprintf(OutFileSimBench, "         rsDecFailPinFlag <= 1'b0;\n");
929 
      fprintf(OutFileSimBench, "      end\n");
930 
      fprintf(OutFileSimBench, "   end\n");
931 
      fprintf(OutFileSimBench, "\n\n\n");
932 
   }
933 
 
934 
 
935 
      fprintf(OutFileSimBench, "   //--------------------------------------------------------------------------\n");
936 
      fprintf(OutFileSimBench, "   //+ rsDecCorrectionAmount\n");
937 
      fprintf(OutFileSimBench, "   //--------------------------------------------------------------------------\n");
938 
      fprintf(OutFileSimBench, "   wire [12:0]  rsDecCorrectionAmount;\n");
939 
      fprintf(OutFileSimBench, "   assign rsDecCorrectionAmount = rsdecTheoricalNumErasure + rsdecTheoricalNumError*2;\n\n\n");
940 
 
941 
 
942 
 
943 
   if (passFailFlag == 1){
944 
      fprintf(OutFileSimBench, "   //--------------------------------------------------------------------------\n");
945 
      fprintf(OutFileSimBench, "   //+ passFailPinThFlag\n");
946 
      fprintf(OutFileSimBench, "   //--------------------------------------------------------------------------\n");
947 
      fprintf(OutFileSimBench, "   reg   passFailPinThFlag;\n");
948 
      fprintf(OutFileSimBench, "   always @(posedge CLK or negedge RESET) begin\n");
949 
      fprintf(OutFileSimBench, "      if (~RESET) begin\n");
950 
      fprintf(OutFileSimBench, "         passFailPinThFlag <= 1'b0;\n");
951 
      fprintf(OutFileSimBench, "      end\n");
952 
      fprintf(OutFileSimBench, "      else if (rsdecOutEnableFF == 1'b1) begin\n");
953 
      fprintf(OutFileSimBench, "         if (rsDecCorrectionAmount <=  rsdecTheoricalSyndromeLength) begin\n");
954 
      fprintf(OutFileSimBench, "            if (rsdecFailFF==1'b1) begin\n");
955 
      fprintf(OutFileSimBench, "               passFailPinThFlag <= 1'b1;\n");
956 
      fprintf(OutFileSimBench, "               $fdisplay(handleA,\"Reed Solomon Decoder Pass Fail Pin : Th NG!!!!\");\n");
957 
      fprintf(OutFileSimBench, "            end\n");
958 
      fprintf(OutFileSimBench, "         end\n");
959 
      fprintf(OutFileSimBench, "      end\n");
960 
      fprintf(OutFileSimBench, "   end\n");
961 
   }
962 
 
963 
 
964 
   if (errorStats == 1) {
965 
      if (ErasureOption == 1) {
966 
         fprintf(OutFileSimBench, "   //--------------------------------------------------------------------------\n");
967 
         fprintf(OutFileSimBench, "   //+ ErasurePinThFlag\n");
968 
         fprintf(OutFileSimBench, "   //--------------------------------------------------------------------------\n");
969 
         fprintf(OutFileSimBench, "   reg   ErasurePinThFlag;\n");
970 
         fprintf(OutFileSimBench, "   always @(posedge CLK or negedge RESET) begin\n");
971 
         fprintf(OutFileSimBench, "      if (~RESET) begin\n");
972 
         fprintf(OutFileSimBench, "         ErasurePinThFlag <= 1'b0;\n");
973 
         fprintf(OutFileSimBench, "      end\n");
974 
         fprintf(OutFileSimBench, "      else if (rsdecOutEnableFF == 1'b1) begin\n");
975 
         fprintf(OutFileSimBench, "         if (rsDecCorrectionAmount <=  rsdecTheoricalSyndromeLength) begin\n");
976 
         fprintf(OutFileSimBench, "            if (rsdecErasureNumFF != rsdecTheoricalNumErasure) begin\n");
977 
         fprintf(OutFileSimBench, "               ErasurePinThFlag <= 1'b1;\n");
978 
         fprintf(OutFileSimBench, "               $fdisplay(handleA,\"Reed Solomon Decoder Erasure Pin : Th NG!!!!\");\n");
979 
         fprintf(OutFileSimBench, "            end\n");
980 
         fprintf(OutFileSimBench, "         end\n");
981 
         fprintf(OutFileSimBench, "      end\n");
982 
         fprintf(OutFileSimBench, "   end\n");
983 
      }
984 
 
985 
         fprintf(OutFileSimBench, "   //--------------------------------------------------------------------------\n");
986 
         fprintf(OutFileSimBench, "   //+ ErrorPinThFlag\n");
987 
         fprintf(OutFileSimBench, "   //--------------------------------------------------------------------------\n");
988 
         fprintf(OutFileSimBench, "   reg   ErrorPinThFlag;\n");
989 
         fprintf(OutFileSimBench, "   always @(posedge CLK or negedge RESET) begin\n");
990 
         fprintf(OutFileSimBench, "      if (~RESET) begin\n");
991 
         fprintf(OutFileSimBench, "         ErrorPinThFlag <= 1'b0;\n");
992 
         fprintf(OutFileSimBench, "      end\n");
993 
         fprintf(OutFileSimBench, "      else if (rsdecOutEnableFF == 1'b1) begin\n");
994 
         fprintf(OutFileSimBench, "         if (rsDecCorrectionAmount <=  rsdecTheoricalSyndromeLength) begin\n");
995 
         fprintf(OutFileSimBench, "            if (rsdecErrorNumFF != rsdecTheoricalNumError) begin\n");
996 
         fprintf(OutFileSimBench, "               ErrorPinThFlag <= 1'b1;\n");
997 
         fprintf(OutFileSimBench, "               $fdisplay(handleA,\"Reed Solomon Decoder Error Pin : Th NG!!!!\");\n");
998 
         fprintf(OutFileSimBench, "            end\n");
999 
         fprintf(OutFileSimBench, "         end\n");
1000 
         fprintf(OutFileSimBench, "      end\n");
1001 
         fprintf(OutFileSimBench, "   end\n");
1002 
   }
1003 
 
1004 
 
1005 
   }
1006 
 
1007 
   //--------------------------------------------------------------------------
1008 
   //--------------------------------------------------------------------------
1009 
   //--------------------------------------------------------------------------
1010 
   //-  RS ENCODER test Bench
1011 
   //--------------------------------------------------------------------------
1012 
   //--------------------------------------------------------------------------
1013 
   //--------------------------------------------------------------------------
1014 
   if ((encDecMode == 1) || (encDecMode == 3)){
1015 
 
1016 
      fprintf(OutFileSimBench, "//--------------------------------------------------------------------------\n");
1017 
      fprintf(OutFileSimBench, "//- RS Encoder Test Bench\n");
1018 
      fprintf(OutFileSimBench, "//--------------------------------------------------------------------------\n");
1019 
 
1020 
      //--------------------------------------------------------------------------
1021 
      //- rsencInput
1022 
      //--------------------------------------------------------------------------
1023 
      fprintf(OutFileSimBench, "   //--------------------------------------------------------------------------\n");
1024 
      fprintf(OutFileSimBench, "   //- rsencInput\n");
1025 
      fprintf(OutFileSimBench, "   //--------------------------------------------------------------------------\n");
1026 
      if (bitSymbol < 9){
1027 
         fprintf(OutFileSimBench, "   wire  [15:0] rsencInput;\n");
1028 
         fprintf(OutFileSimBench, "   assign rsencInput = (IBankIndex < 32'd%d) ? rsencInputBank [IBankIndex] : 16'd0;\n", encBenchInSize+1);
1029 
      }else{
1030 
         fprintf(OutFileSimBench, "   wire  [19:0] rsencInput;\n");
1031 
         fprintf(OutFileSimBench, "   assign rsencInput = (IBankIndex < 32'd%d) ? rsencInputBank [IBankIndex] : 20'd0;\n", encBenchInSize+1);
1032 
      }
1033 
      fprintf(OutFileSimBench, "\n\n");
1034 
 
1035 
 
1036 
      //------------------------------------------------------------------------
1037 
      //+ rsencStartPls
1038 
      //------------------------------------------------------------------------
1039 
      fprintf(OutFileSimBench, "   //------------------------------------------------------------------------\n");
1040 
      fprintf(OutFileSimBench, "   //+ rsencStartPls\n");
1041 
      fprintf(OutFileSimBench, "   //------------------------------------------------------------------------\n");
1042 
      fprintf(OutFileSimBench, "   always @(posedge CLK or negedge RESET) begin\n");
1043 
      fprintf(OutFileSimBench, "      if (~RESET) begin\n");
1044 
      fprintf(OutFileSimBench, "         rsencStartPls <= 1'b0;\n");
1045 
      fprintf(OutFileSimBench, "      end\n");
1046 
      fprintf(OutFileSimBench, "      else if (simStart == 1'b1) begin\n");
1047 
      if (bitSymbol < 9){
1048 
         fprintf(OutFileSimBench, "         rsencStartPls <= rsencInput[12];\n");
1049 
      }else{
1050 
         fprintf(OutFileSimBench, "         rsencStartPls <= rsencInput[16];\n");
1051 
      }
1052 
      fprintf(OutFileSimBench, "      end\n");
1053 
      fprintf(OutFileSimBench, "   end\n");
1054 
      fprintf(OutFileSimBench, "\n\n");
1055 
 
1056 
 
1057 
      //------------------------------------------------------------------------
1058 
      //+ rsencEnable
1059 
      //------------------------------------------------------------------------
1060 
      fprintf(OutFileSimBench, "   //------------------------------------------------------------------------\n");
1061 
      fprintf(OutFileSimBench, "   //+ rsencEnable\n");
1062 
      fprintf(OutFileSimBench, "   //------------------------------------------------------------------------\n");
1063 
      fprintf(OutFileSimBench, "   always @(posedge CLK or negedge RESET) begin\n");
1064 
      fprintf(OutFileSimBench, "      if (~RESET) begin\n");
1065 
      fprintf(OutFileSimBench, "         rsencEnable <= 1'b0;\n");
1066 
      fprintf(OutFileSimBench, "      end\n");
1067 
      fprintf(OutFileSimBench, "      else begin\n");
1068 
      if (bitSymbol < 9){
1069 
         fprintf(OutFileSimBench, "         rsencEnable <= rsencInput[8];\n");
1070 
      }else{
1071 
         fprintf(OutFileSimBench, "         rsencEnable <= rsencInput[12];\n");
1072 
      }
1073 
      fprintf(OutFileSimBench, "      end\n");
1074 
      fprintf(OutFileSimBench, "   end\n");
1075 
      fprintf(OutFileSimBench, "\n\n");
1076 
 
1077 
 
1078 
      //------------------------------------------------------------------------
1079 
      //+ rsencDataIn
1080 
      //------------------------------------------------------------------------
1081 
      fprintf(OutFileSimBench, "   //------------------------------------------------------------------------\n");
1082 
      fprintf(OutFileSimBench, "   //+ rsencDataIn\n");
1083 
      fprintf(OutFileSimBench, "   //------------------------------------------------------------------------\n");
1084 
      fprintf(OutFileSimBench, "   always @(posedge CLK or negedge RESET) begin\n");
1085 
      fprintf(OutFileSimBench, "      if (~RESET) begin\n");
1086 
      fprintf(OutFileSimBench, "         rsencDataIn <= %d'd0;\n", bitSymbol);
1087 
      fprintf(OutFileSimBench, "      end\n");
1088 
      fprintf(OutFileSimBench, "      else begin\n");
1089 
      fprintf(OutFileSimBench, "         rsencDataIn <= rsencInput[%d:0];\n", bitSymbol-1);
1090 
      fprintf(OutFileSimBench, "      end\n");
1091 
      fprintf(OutFileSimBench, "   end\n");
1092 
      fprintf(OutFileSimBench, "\n\n");
1093 
 
1094 
 
1095 
      //------------------------------------------------------------------------
1096 
      //+ rsencOBankIndex
1097 
      //------------------------------------------------------------------------
1098 
      fprintf(OutFileSimBench, "   //------------------------------------------------------------------------\n");
1099 
      fprintf(OutFileSimBench, "   //+ rsencOBankIndex\n");
1100 
      fprintf(OutFileSimBench, "   //------------------------------------------------------------------------\n");
1101 
      fprintf(OutFileSimBench, "   reg [31:0]  rsencOBankIndex;\n");
1102 
      fprintf(OutFileSimBench, "   always @(posedge CLK or negedge RESET) begin\n");
1103 
      fprintf(OutFileSimBench, "      if (~RESET) begin\n");
1104 
      fprintf(OutFileSimBench, "         rsencOBankIndex <= 32'd0;\n");
1105 
      fprintf(OutFileSimBench, "      end\n");
1106 
      fprintf(OutFileSimBench, "      else if (simStartFF2 == 1'b1) begin\n");
1107 
      fprintf(OutFileSimBench, "         rsencOBankIndex <= rsencOBankIndex + 32'd1;\n");
1108 
      fprintf(OutFileSimBench, "      end\n");
1109 
      fprintf(OutFileSimBench, "   end\n");
1110 
      fprintf(OutFileSimBench, "\n\n");
1111 
 
1112 
 
1113 
      //--------------------------------------------------------------------------
1114 
      //- rsencOutput
1115 
      //--------------------------------------------------------------------------
1116 
      fprintf(OutFileSimBench, "   //--------------------------------------------------------------------------\n");
1117 
      fprintf(OutFileSimBench, "   //- rsencOutput\n");
1118 
      fprintf(OutFileSimBench, "   //--------------------------------------------------------------------------\n");
1119 
      if (bitSymbol < 9){
1120 
         fprintf(OutFileSimBench, "   wire  [7:0] rsencOutput;\n");
1121 
         fprintf(OutFileSimBench, "   assign rsencOutput = (rsencOBankIndex < 32'd%d) ? rsencOutputBank [rsencOBankIndex] : 8'd0;\n", encBenchInSize+1);
1122 
      }else{
1123 
         fprintf(OutFileSimBench, "   wire  [11:0] rsencOutput;\n");
1124 
         fprintf(OutFileSimBench, "   assign rsencOutput = (rsencOBankIndex < 32'd%d) ? rsencOutputBank [rsencOBankIndex] : 12'd0;\n", encBenchInSize+1);
1125 
      }
1126 
      fprintf(OutFileSimBench, "\n\n");
1127 
 
1128 
 
1129 
      //--------------------------------------------------------------------------
1130 
      //+ rsencExpData
1131 
      //--------------------------------------------------------------------------
1132 
      fprintf(OutFileSimBench, "   //--------------------------------------------------------------------------\n");
1133 
      fprintf(OutFileSimBench, "   //+ rsencExpData\n");
1134 
      fprintf(OutFileSimBench, "   //--------------------------------------------------------------------------\n");
1135 
      fprintf(OutFileSimBench, "   reg [%d:0]   rsencExpData;\n", bitSymbol-1);
1136 
      fprintf(OutFileSimBench, "   always @(posedge CLK or negedge RESET) begin\n");
1137 
      fprintf(OutFileSimBench, "      if (~RESET) begin\n");
1138 
      fprintf(OutFileSimBench, "         rsencExpData <= %d'd0;\n", bitSymbol);
1139 
      fprintf(OutFileSimBench, "      end\n");
1140 
      fprintf(OutFileSimBench, "      else if (simStartFF2 == 1'b1) begin\n");
1141 
      fprintf(OutFileSimBench, "         rsencExpData <= rsencOutput[%d:0];\n", bitSymbol-1);
1142 
      fprintf(OutFileSimBench, "      end\n");
1143 
      fprintf(OutFileSimBench, "      else begin\n");
1144 
      fprintf(OutFileSimBench, "         rsencExpData <= %d'd0;\n", bitSymbol);
1145 
      fprintf(OutFileSimBench, "      end\n");
1146 
      fprintf(OutFileSimBench, "   end\n");
1147 
      fprintf(OutFileSimBench, "\n\n");
1148 
 
1149 
 
1150 
      //--------------------------------------------------------------------------
1151 
      //+ rsEncPassFailFlag, rsEncFailFlag
1152 
      //--------------------------------------------------------------------------
1153 
      fprintf(OutFileSimBench, "   //--------------------------------------------------------------------------\n");
1154 
      fprintf(OutFileSimBench, "   //+ rsEncPassFailFlag, rsEncFailFlag\n");
1155 
      fprintf(OutFileSimBench, "   //--------------------------------------------------------------------------\n");
1156 
      fprintf(OutFileSimBench, "   reg   rsEncPassFailFlag;\n");
1157 
      fprintf(OutFileSimBench, "   reg   rsEncFailFlag;\n");
1158 
 
1159 
      fprintf(OutFileSimBench, "   always @(posedge CLK or negedge RESET) begin\n");
1160 
      fprintf(OutFileSimBench, "      if (~RESET) begin\n");
1161 
      fprintf(OutFileSimBench, "         rsEncPassFailFlag <= 1'b0;\n");
1162 
      fprintf(OutFileSimBench, "         rsEncFailFlag   <= 1'b0;\n");
1163 
      fprintf(OutFileSimBench, "      end\n");
1164 
      fprintf(OutFileSimBench, "      else if ((simStartFF3 == 1'b1) && (rsencOBankIndex < 32'd%d)) begin\n", encBenchInSize+2);
1165 
      fprintf(OutFileSimBench, "         if (rsencDataOut == rsencExpData) begin\n");
1166 
      fprintf(OutFileSimBench, "            rsEncPassFailFlag <= 1'b0;\n");
1167 
      fprintf(OutFileSimBench, "         end\n");
1168 
      fprintf(OutFileSimBench, "         else begin\n");
1169 
      fprintf(OutFileSimBench, "            rsEncPassFailFlag <= 1'b1;\n");
1170 
      fprintf(OutFileSimBench, "            rsEncFailFlag   <= 1'b1;\n");
1171 
      fprintf(OutFileSimBench, "            $fdisplay(handleA,\"Reed Solomon Encoder: NG!!!!\");\n");
1172 
      fprintf(OutFileSimBench, "         end\n");
1173 
      fprintf(OutFileSimBench, "      end\n");
1174 
      fprintf(OutFileSimBench, "      else begin\n");
1175 
      fprintf(OutFileSimBench, "         rsEncPassFailFlag <= 1'b0;\n");
1176 
      fprintf(OutFileSimBench, "      end\n");
1177 
      fprintf(OutFileSimBench, "   end\n");
1178 
   }
1179 
 
1180 
 
1181 
   //------------------------------------------------------------------------
1182 
   // + simOver
1183 
   //------------------------------------------------------------------------
1184 
   fprintf(OutFileSimBench, "   //------------------------------------------------------------------------\n");
1185 
   fprintf(OutFileSimBench, "   // + simOver\n");
1186 
   fprintf(OutFileSimBench, "   //------------------------------------------------------------------------\n");
1187 
   fprintf(OutFileSimBench, "   reg simOver;\n");
1188 
 
1189 
   fprintf(OutFileSimBench, "   always @(posedge CLK or negedge RESET) begin\n");
1190 
   fprintf(OutFileSimBench, "      if (~RESET) begin\n");
1191 
   fprintf(OutFileSimBench, "         simOver <= 1'b0;\n");
1192 
   fprintf(OutFileSimBench, "      end\n");
1193 
   switch (encDecMode){
1194 
      case(1):
1195 
         fprintf(OutFileSimBench, "      else if (rsencOBankIndex > 32'd%d) begin\n", encBenchInSize+2);
1196 
      break;
1197 
      case(2):
1198 
         fprintf(OutFileSimBench, "      else if (rsdecOBankIndex > 32'd%d) begin\n", benchOutSize);
1199 
      break;
1200 
      case(3):
1201 
         fprintf(OutFileSimBench, "      else if ((rsencOBankIndex > 32'd%d) && (rsdecOBankIndex > 32'd%d)) begin\n", encBenchInSize+2, benchOutSize);
1202 
      break;
1203 
   }
1204 
 
1205 
 
1206 
   fprintf(OutFileSimBench, "         simOver <= 1'b1;\n");
1207 
   fprintf(OutFileSimBench, "         $fclose(handleA);\n");
1208 
   fprintf(OutFileSimBench, "         $finish;\n");
1209 
   fprintf(OutFileSimBench, "      end\n");
1210 
   fprintf(OutFileSimBench, "   end\n");
1211 
 
1212 
 
1213 
 
1214 
   //------------------------------------------------------------------------
1215 
   //-  TIMING
1216 
   //------------------------------------------------------------------------
1217 
   fprintf(OutFileSimBench, "   //------------------------------------------------------------------------\n");
1218 
   fprintf(OutFileSimBench, "   //-  TIMING\n");
1219 
   fprintf(OutFileSimBench, "   //------------------------------------------------------------------------\n");
1220 
   fprintf(OutFileSimBench, "   initial begin\n");
1221 
   fprintf(OutFileSimBench, "      simStart = 1'b0;\n");
1222 
   fprintf(OutFileSimBench, "      CLK = 0;\n");
1223 
   fprintf(OutFileSimBench, "      RESET = 1;\n");
1224 
   fprintf(OutFileSimBench, "      #(period*2)  RESET = 0;\n");
1225 
   fprintf(OutFileSimBench, "      #(period*2)  RESET = 1;\n");
1226 
   fprintf(OutFileSimBench, "      #(period*20) simStart = 1'b1;\n");
1227 
   fprintf(OutFileSimBench, "      #(period*99999999);\n");
1228 
   fprintf(OutFileSimBench, "      #(period*99999999);\n");
1229 
   fprintf(OutFileSimBench, "      #(period*99999999);\n");
1230 
   fprintf(OutFileSimBench, "      #(period*99999999);\n");
1231 
   fprintf(OutFileSimBench, "      #(period*99999999);\n");
1232 
   fprintf(OutFileSimBench, "      #(period*99999999);\n");
1233 
   fprintf(OutFileSimBench, "      #(period*99999999);\n");
1234 
   fprintf(OutFileSimBench, "      #(period*99999999);\n");
1235 
   fprintf(OutFileSimBench, "      #(period*99999999);\n");
1236 
   fprintf(OutFileSimBench, "      #(period*99999999);\n");
1237 
   fprintf(OutFileSimBench, "      #(period*99999999);\n");
1238 
   fprintf(OutFileSimBench, "      #(period*99999999);\n");
1239 
   fprintf(OutFileSimBench, "      #(period*99999999);\n");
1240 
   fprintf(OutFileSimBench, "      #(period*99999999);\n");
1241 
   fprintf(OutFileSimBench, "      #(period*99999999);\n");
1242 
   fprintf(OutFileSimBench, "      #(period*99999999);\n");
1243 
   fprintf(OutFileSimBench, "      #(period*99999999);\n");
1244 
   fprintf(OutFileSimBench, "      #(period*99999999);\n");
1245 
   fprintf(OutFileSimBench, "      #(period*99999999);\n");
1246 
   fprintf(OutFileSimBench, "      #(period*99999999);\n");
1247 
   fprintf(OutFileSimBench, "      #(period*99999999);\n");
1248 
   fprintf(OutFileSimBench, "      #(period*99999999);\n");
1249 
   fprintf(OutFileSimBench, "      #(period*99999999);\n");
1250 
   fprintf(OutFileSimBench, "      #(period*99999999);\n");
1251 
   fprintf(OutFileSimBench, "      #(period*99999999);\n");
1252 
   fprintf(OutFileSimBench, "      #(period*99999999);\n");
1253 
   fprintf(OutFileSimBench, "      #(period*99999999);\n");
1254 
   fprintf(OutFileSimBench, "      #(period*99999999);\n");
1255 
   fprintf(OutFileSimBench, "      #(period*99999999);\n");
1256 
   fprintf(OutFileSimBench, "      #(period*99999999);\n");
1257 
   fprintf(OutFileSimBench, "      #(period*99999999);\n");
1258 
   fprintf(OutFileSimBench, "      #(period*99999999);\n");
1259 
   fprintf(OutFileSimBench, "      #(period*99999999);\n");
1260 
   fprintf(OutFileSimBench, "      #(period*99999999);\n");
1261 
   fprintf(OutFileSimBench, "      #(period*99999999);\n");
1262 
   fprintf(OutFileSimBench, "      #(period*99999999);\n");
1263 
   fprintf(OutFileSimBench, "      #(period*99999999);\n");
1264 
   fprintf(OutFileSimBench, "      #(period*99999999);\n");
1265 
   fprintf(OutFileSimBench, "      #(period*99999999);\n");
1266 
   fprintf(OutFileSimBench, "      #(period*99999999);\n");
1267 
 
1268 
 
1269 
   fprintf(OutFileSimBench, "   end\n");
1270 
   fprintf(OutFileSimBench, "endmodule\n");
1271 
 
1272 
 
1273 
  //---------------------------------------------------------------
1274 
  // close file
1275 
  //---------------------------------------------------------------
1276 
   fclose(OutFileSimBench);
1277 
 
1278 
  //---------------------------------------------------------------
1279 
  // Free memory
1280 
  //---------------------------------------------------------------
1281 
   delete[] euclideTab;
1282 
 
1283 
 
1284 
   //---------------------------------------------------------------
1285 
   // automatically convert Dos mode To Unix mode
1286 
   //---------------------------------------------------------------
1287 
        char ch;
1288 
        char temp[MAX_PATH]="\0";
1289 
 
1290 
        //Open the file for reading in binarymode.
1291 
//      ifstream fp_read("simReedSolomon.v", ios_base::in | ios_base::binary);
1292 
   ifstream fp_read(strsimReedSolomon, ios_base::in | ios_base::binary);
1293 
        sprintf(temp, "%s.temp", strsimReedSolomon);
1294 
 
1295 
 
1296 
        //Create a temporary file for writing in the binary mode. This
1297 
        //file will be created in the same directory as the input file.
1298 
        ofstream fp_write(temp, ios_base::out | ios_base::trunc | ios_base::binary);
1299 
 
1300 
        while(fp_read.eof() != true)
1301 
        {
1302 
                fp_read.get(ch);
1303 
                //Check for CR (carriage return)
1304 
                if((int)ch == 0x0D)
1305 
                        continue;
1306 
                if (!fp_read.eof())fp_write.put(ch);
1307 
        }
1308 
 
1309 
        fp_read.close();
1310 
        fp_write.close();
1311 
   //Delete the existing input file.
1312 
   remove(strsimReedSolomon);
1313 
   //Rename the temporary file to the input file.
1314 
   rename(temp, strsimReedSolomon);
1315 
 
1316 
 
1317 
        //Delete the temporary file.
1318 
        remove(temp);
1319 
 
1320 
 
1321 
   //---------------------------------------------------------------
1322 
   // clean string
1323 
   //---------------------------------------------------------------
1324 
   free(strsimReedSolomon);
1325 
 
1326 
 
1327 
}

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