Subversion Repositories reed_solomon_coder

`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////

// Company: University of Hamburg, University of Kiel, Germany

// Engineer: Cagil Gümüs, Andreas Bahr

// 

// Create Date:    17:06:12 01/18/2016 

// Design Name: 

// Module Name:    Middle 

// Project Name: 

// Target Devices: 

// Tool versions: 

// Description: 

//

// Dependencies: 

//

// Revision: 

// Revision 0.01 - File Created

// Additional Comments: 

//

//////////////////////////////////////////////////////////////////////////////////

module Middle(

        input wire                              clk,

        input wire                              reset,

        input wire [35:0]        data_in,

        input wire                              job_done,

        input wire                              go_BM,

        input wire                              go_chien,

        input wire                              go_forney,

        input wire                              go_syndrome,

        output wire                     ready_BM,

        output wire                     ready_chien,

        output wire                     ready_forney,

        output wire                     ready_syndrome,

        output wire [3:0]                errorlocation1,

        output wire [3:0]                errorlocation2,

        output wire [3:0]                errormagnitude1,

        output wire [3:0]                errormagnitude2,

        output wire                     no_errors,

        output wire     [15:0]   errorlocator

    );

assign errorlocator = errorlocator_wire;

wire [3:0] syndrome1_wire;

wire [3:0] syndrome2_wire;

wire [3:0] syndrome3_wire;

wire [3:0] syndrome4_wire;

wire [15:0] errorlocator_wire;

wire [3:0] errorlocation1_wire;

wire [3:0] errorlocation2_wire;

wire [3:0] errormagnitude1_wire;

wire [3:0] errormagnitude2_wire;

assign errorlocation1 = errorlocation1_wire;

assign errorlocation2 = errorlocation2_wire;

assign errormagnitude1 = errormagnitude1_wire;

assign errormagnitude2 = errormagnitude2_wire;

        syndromecalculator syndrome(

        .clk(clk),

        .reset(reset),

        .go(go_syndrome),

        .data_in(data_in),

        .job_done(job_done),

        .syndrome_1(syndrome1_wire),

        .syndrome_2(syndrome2_wire),

        .syndrome_3(syndrome3_wire),

        .syndrome_4(syndrome4_wire),

        .no_errors(no_errors),

        .ready(ready_syndrome)

        );

        berlekampmassey BM(

        .clk(clk),

        .go(go_BM),

        .reset(reset),

        .syndrome_0(syndrome1_wire) ,

        .syndrome_1(syndrome2_wire) ,

        .syndrome_2(syndrome3_wire),

        .syndrome_3(syndrome4_wire) ,

        .errorlocatorn(errorlocator_wire),

        .ready(ready_BM),

        .job_done(job_done)

        );

        chiensearch chien(

        .errorpolynomial(errorlocator_wire),

        .clk(clk),

        .go(go_chien),

        .reset(reset),

        .errorlocation_1(errorlocation1_wire),

        .errorlocation_2(errorlocation2_wire),

        .ready(ready_chien),

        .job_done(job_done)

        );

        forney forney1(

        .clk(clk),

        .reset(reset),

        .errorlocation_1(errorlocation1_wire),

        .errorlocation_2(errorlocation2_wire),

        .errorlocator(errorlocator_wire),

        .syndrome_1(syndrome1_wire),

        .syndrome_2(syndrome2_wire),

        .syndrome_3(syndrome3_wire),

        .syndrome_4(syndrome4_wire),

        .go(go_forney),

        .ready(ready_forney),

        .error_magnitude_1(errormagnitude1_wire),

        .error_magnitude_2(errormagnitude2_wire),

        .job_done(job_done)

        );

endmodule