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cau_sse |
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company: University of Hamburg, University of Kiel, Germany
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// Engineer: Cagil Gümüs, Andreas Bahr
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//
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// Create Date: 14:34:38 03/24/2016
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// Design Name:
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// Module Name: corrector
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module corrector(
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input wire clk,
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input wire reset,
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input wire go,
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input wire [3:0] location1,
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input wire [3:0] location2,
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input wire [3:0] magnitude1,
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input wire [3:0] magnitude2,
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input wire [35:0] data_in,
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output reg [35:0] data_out,
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output reg ready,
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output reg max_error
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);
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reg [35:0] data_out_reg;
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reg go_syndrome;
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wire ready_syndrome;
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wire no_errors_wire;
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reg job_done_reg;
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syndromecalculator syndrome2(
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.clk(clk),
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.reset(reset),
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.data_in(data_out_reg),
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.go(go_syndrome),
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.job_done(job_done_reg),
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.syndrome_1() ,
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.syndrome_2(),
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.syndrome_3(),
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.syndrome_4(),
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.no_errors(no_errors_wire),
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.ready(ready_syndrome)
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);
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reg [3:0] state ; // State Machine
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parameter [3:0] IDLE = 4'b0000,
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LOCATION = 4'b0001,
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FINISH = 4'b0011,
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SYNDROME = 4'b0010;
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always@(posedge clk or negedge reset)
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begin
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if(!reset)
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begin
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state <= IDLE;
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max_error <= 0;
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ready <= 0;
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data_out <= 0;
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data_out_reg <= 0;
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end
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else
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begin
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case(state)
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IDLE:
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begin
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go_syndrome <= 0;
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ready <= 0;
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max_error <= 0;
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data_out_reg <= data_in;
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if(go)
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state <= LOCATION ;
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else
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state <= IDLE;
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end
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LOCATION:
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begin
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job_done_reg <= 0;
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case(location1)
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//0000: data_out_reg[3:0] <= (data_out_reg[3:0]^magnitude1)
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4'b0001: data_out_reg[3:0] <= (data_out_reg[3:0] ^ magnitude1);
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4'b0010: data_out_reg[7:4] <= (data_out_reg[7:4] ^ magnitude1);
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4'b0011: data_out_reg[19:16] <= (data_out_reg[19:16] ^ magnitude1);
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4'b0100: data_out_reg[11:8] <= (data_out_reg[11:8] ^ magnitude1);
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4'b0101: data_out_reg[35:32] <= (data_out_reg[35:32] ^ magnitude1);
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4'b0110: data_out_reg[23:20] <= (data_out_reg[23:20] ^ magnitude1);
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4'b0111: data_out_reg[7:4] <= (data_out_reg[7:4] ^ magnitude1);
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4'b1000: data_out_reg[15:12] <= (data_out_reg[15:12] ^ magnitude1);
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4'b1001: data_out_reg[23:20] <= (data_out_reg[23:20] ^ magnitude1);
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4'b1010: data_out_reg[3:0] <= (data_out_reg[3:0] ^ magnitude1);
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4'b1011: data_out_reg[31:28] <= (data_out_reg[31:28] ^ magnitude1);
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4'b1100: data_out_reg[27:24] <= (data_out_reg[27:24] ^ magnitude1);
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4'b1101: data_out_reg[19:16] <= (data_out_reg[19:16] ^ magnitude1);
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4'b1110: data_out_reg[11:8] <= (data_out_reg[11:8] ^ magnitude1);
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4'b1111: data_out_reg[15:12] <= (data_out_reg[15:12] ^ magnitude1);
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endcase
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case(location2)
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//0000: data_out_reg[3:0] <= (data_out_reg[3:0]^magnitude1)
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4'b0001: data_out_reg[3:0] <= (data_out_reg[3:0] ^ magnitude2);
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4'b0010: data_out_reg[7:4] <= (data_out_reg[7:4] ^ magnitude2);
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4'b0011: data_out_reg[19:16] <= (data_out_reg[19:16] ^ magnitude2);
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4'b0100: data_out_reg[11:8] <= (data_out_reg[11:8] ^ magnitude2);
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4'b0101: data_out_reg[35:32] <= (data_out_reg[35:32] ^ magnitude2);
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4'b0110: data_out_reg[23:20] <= (data_out_reg[23:20] ^ magnitude2);
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4'b0111: data_out_reg[7:4] <= (data_out_reg[7:4] ^ magnitude2);
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4'b1000: data_out_reg[15:12] <= (data_out_reg[15:12] ^ magnitude2);
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4'b1001: data_out_reg[23:20] <= (data_out_reg[23:20] ^ magnitude2);
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4'b1010: data_out_reg[3:0] <= (data_out_reg[3:0] ^ magnitude2);
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4'b1011: data_out_reg[31:28] <= (data_out_reg[31:28] ^ magnitude2);
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4'b1100: data_out_reg[27:24] <= (data_out_reg[27:24] ^ magnitude2);
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4'b1101: data_out_reg[19:16] <= (data_out_reg[19:16] ^ magnitude2);
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4'b1110: data_out_reg[11:8] <= (data_out_reg[11:8] ^ magnitude2);
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4'b1111: data_out_reg[15:12] <= (data_out_reg[15:12] ^ magnitude2);
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endcase
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state <= SYNDROME;
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end
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SYNDROME:
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begin
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go_syndrome <= 1;
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if(ready_syndrome)
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begin
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state <= FINISH;
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end
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else
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begin
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state <= SYNDROME;
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end
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end
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FINISH:
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begin
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if(no_errors_wire)
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max_error <= 0;
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else
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max_error <= 1;
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data_out <= data_out_reg;
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job_done_reg <= 1;
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state <= IDLE;
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ready <= 1;
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end
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default: state <= IDLE ;
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endcase
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end
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end
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endmodule
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