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[/] [reed_solomon_coder/] [trunk/] [division.v] - Blame information for rev 6

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Line No. Rev Author Line
1 5 cau_sse
`timescale 1ns / 1ps
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module division(A,B,Res);
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    input [31:0] A;
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    input [31:0] B;
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    output [31:0] Res;
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    reg [31:0] Res = 0;
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    reg [31:0] a1,b1;
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    reg [32:0] p1;
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    integer i;
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    always@ (A or B)
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    begin
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        a1 = A;
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        b1 = B;
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        p1= 0;
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        for(i=0;i < 32;i=i+1)    begin
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            p1 = {p1[30:0],a1[31]};
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            a1[31:1] = a1[30:0];
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            p1 = p1-b1;
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            if(p1[31] == 1)    begin
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                a1[0] = 0;
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                p1 = p1 + b1;   end
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            else
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                a1[0] = 1;
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        end
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        Res = a1;
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    end
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endmodule

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