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[/] [reed_solomon_decoder/] [trunk/] [rtl/] [input_syndromes.v] - Blame information for rev 2

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/* This program is free software: you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation, either version 3 of the License, or
   (at your option) any later version.
 
   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.
 
   You should have received a copy of the GNU General Public License
   along with this program.  If not, see <http://www.gnu.org/licenses/>.
 
   Email : semiconductors@varkongroup.com
   Tel   : 1-732-447-8611
 
*/
 
 
 
//// input stage of reed-solomon decoder and syndromes calculation
//// inputs will be buffered on pipelining rams and it will be used 
////to calcultes syndromes for each block
module input_syndromes
(
input clk, // clk planned to be 56 mega
input reset, // asynchorounus active high reset 
// chip enable active high flag should be active for one clock with every input
input CE,
input [7:0] input_byte, // input byte
input [7:0] R_Add, // read address to read from inputs pipeling memories
/// input read enable to the input pipeling memories (1 for mem0, and 0 for mem1 )
input RE,
 
/// syndromes 16 elements
/// active high flag will be active for one clock when Syndromes values are ready
output reg S_Ready,
output reg [7:0] s0,s1,s2,s3,s4,s5,s6,s7,s8,s9,s10,s11,s12,s13,s14,s15,
output [7:0] Read_byte  /// output byte from input pipelinig memories
);
 
 
 
reg WE;
reg [7:0] input_byte0;
reg [7:0] W_Add;
wire [7:0] out_byte_0,out_byte_1;
 
 
 
 
 
assign Read_byte = (RE)? out_byte_0:out_byte_1;
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
/////// input pipelining memories
DP_RAM #(.num_words(205),.address_width(8),.data_width(8))
mem_in_0
 
(
.clk(clk),
.we(WE),
.re(RE),
.address_read(R_Add),
.address_write(W_Add),
.data_in(input_byte0),
.data_out(out_byte_0)
);
 
DP_RAM  #(.num_words(205),.address_width(8),.data_width(8))
mem_in_1
(
.clk(clk),
.we(!WE),
.re(!RE),
.address_read(R_Add),
.address_write(W_Add),
.data_in(input_byte0),
.data_out(out_byte_1)
);
 
 
 
 
 
 
//////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////
////// input handling
 
reg CE0,CE1;
reg [7:0] Address_GF_ascending;
wire [7:0] out_GF_ascending;
 
 
always@(posedge clk or posedge reset)
begin
        if (reset)
                begin
                        WE<=1;  /// use mem0 first
                        W_Add<=204;
                        input_byte0<=0;
                        CE0<=0;
                        CE1<=0;
                        Address_GF_ascending<=0;
                end
        else
                begin
 
 
                        //  two delay lines to input CE
                        CE0<=CE;
                        CE1<=CE0;  // now can read from memory
 
                        if(CE)
                                begin
                // one delay line for input as address of memory changes after one clock from CE
                                        input_byte0<=input_byte;
                                        Address_GF_ascending<=input_byte;
 
                // does not need to add one like matlab as memory index from 0 to 255   not from 1:256
                                        if (W_Add == 0)
                                                begin
                                                        WE <= ~WE;
                                                        W_Add <=203;
                                                end
                                        else
                                                W_Add<=W_Add-1;
                                end
                end
end
 
 
 
 
 
 
 
 
///////////// instant of GF_matrix_ascending_binary Rom/////////////
GF_matrix_ascending_binary rom_instant
(
.clk(clk),
.re(1'b1),
.address_read(Address_GF_ascending),
.data_out(out_GF_ascending)
);
 
 
/////////////////////////////////////////////////////
////////////////////////////////////////////////////
////// x_power generation
 
reg [7:0] x_power_0;
 
reg [8:0] x1;
reg [7:0] x_power_1;
 
reg [8:0] x2;
reg [7:0] x_power_2;
 
reg [8:0] x3;
reg [7:0] x_power_3;
 
reg [8:0] x4;
reg [7:0] x_power_4;
 
reg [8:0] x5;
reg [7:0] x_power_5;
 
reg [8:0] x6;
reg [7:0] x_power_6;
 
reg [8:0] x7;
reg [7:0] x_power_7;
 
reg [8:0] x8;
reg [7:0] x_power_8;
 
 
reg [8:0] x9;
reg [7:0] x_power_9;
 
reg [8:0] x10;
reg [7:0] x_power_10;
 
reg [8:0] x11;
reg [7:0] x_power_11;
 
reg [8:0] x12;
reg [7:0] x_power_12;
 
reg [8:0] x13;
reg [7:0] x_power_13;
 
reg [8:0] x14;
reg [7:0] x_power_14;
 
reg [8:0] x15;
reg [7:0] x_power_15;
always@(posedge clk or posedge reset)
begin
        if (reset)
                begin
                        x_power_0<=0;
 
                        x1<=0;
                        x_power_1<=0;
                        x2<=0;
                        x_power_2<=0;
                        x3<=0;
                        x_power_3<=0;
                        x4<=0;
                        x_power_4<=0;
                        x5<=0;
                        x_power_5<=0;
                        x6<=0;
                        x_power_6<=0;
                        x7<=0;
                        x_power_7<=0;
                        x8<=0;
                        x_power_8<=0;
                        x9<=0;
                        x_power_9<=0;
                        x10<=0;
                        x_power_10<=0;
                        x11<=0;
                        x_power_11<=0;
                        x12<=0;
                        x_power_12<=0;
                        x13<=0;
                        x_power_13<=0;
                        x14<=0;
                        x_power_14<=0;
                        x15<=0;
                        x_power_15<=0;
                end
        else
                begin
                        if (CE)
                                begin
                                        if (x_power_0 == 0)
                                                begin
                                                        x_power_0<=203;
                                                        x1<=151;
                                                        x2<=99;
                                                        x3<=47;
                                                        x4<=250;
                                                        x5<=198;
                                                        x6<=146;
                                                        x7<=94;
                                                        x8<=42;
                                                        x9<=245;
                                                        x10<=193;
                                                        x11<=141;
                                                        x12<=89;
                                                        x13<=37;
                                                        x14<=240;
                                                        x15<=188;
                                                end
                                        else
                                                begin
                                                        x_power_0<= x_power_0 - 1;
                                                        x1<=x_power_1 - 2;
                                                        x2<=x_power_2 - 3;
                                                        x3<=x_power_3 - 4;
                                                        x4<=x_power_4 - 5;
                                                        x5<=x_power_5 - 6;
                                                        x6<=x_power_6 - 7;
                                                        x7<=x_power_7 - 8;
                                                        x8<=x_power_8 - 9;
                                                        x9<=x_power_9 - 10;
                                                        x10<=x_power_10 - 11;
                                                        x11<=x_power_11 - 12;
                                                        x12<=x_power_12 - 13;
                                                        x13<=x_power_13 - 14;
                                                        x14<=x_power_14 - 15;
                                                        x15<=x_power_15 - 16;
                                                end
 
                                end
 
                                x_power_1<= x1[7:0] - x1[8];
                                x_power_2<= x2[7:0] - x2[8];
                                x_power_3<= x3[7:0] - x3[8];
                                x_power_4<= x4[7:0] - x4[8];
                                x_power_5<= x5[7:0] - x5[8];
                                x_power_6<= x6[7:0] - x6[8];
                                x_power_7<= x7[7:0] - x7[8];
                                x_power_8<= x8[7:0] - x8[8];
                                x_power_9<= x9[7:0] - x9[8];
                                x_power_10<= x10[7:0] - x10[8];
                                x_power_11<= x11[7:0] - x11[8];
                                x_power_12<= x12[7:0] - x12[8];
                                x_power_13<= x13[7:0] - x13[8];
                                x_power_14<= x14[7:0] - x14[8];
                                x_power_15<= x15[7:0] - x15[8];
                end
end
//// these wires to replace every FF with 00
wire [7:0] x_power0,x_power1,x_power2,x_power3,x_power4,x_power5,x_power6,x_power7;
wire [7:0] x_power8,x_power9,x_power10,x_power11,x_power12,x_power13,x_power14,x_power15;
 
assign x_power0 = x_power_0;
assign x_power1 = x_power_1;
assign x_power2 = (&x_power_2)? 8'h00:x_power_2;
assign x_power3 = x_power_3;
assign x_power4 = (&x_power_4)? 8'h00:x_power_4;
assign x_power5 = (&x_power_5)? 8'h00:x_power_5;
assign x_power6 = x_power_6;
assign x_power7 = x_power_7;
assign x_power8 = (&x_power_8)? 8'h00:x_power_8;
assign x_power9 = (&x_power_9)? 8'h00:x_power_9;
assign x_power10 = x_power_10;
assign x_power11 = (&x_power_11)? 8'h00:x_power_11;
assign x_power12 = x_power_12;
assign x_power13 = x_power_13;
assign x_power14 = (&x_power_14)? 8'h00:x_power_14;
assign x_power15 = x_power_15;
//////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////
 
 
//////////////// two instants of syndromes calculation unit ///////////////
 
reg CE_GF_mult_add;
reg [7:0] ip1_0,ip2_0;
reg [7:0] ip1_1,ip2_1;
reg [2:0] count_in;
wire S_Ready_0;
wire [7:0] s_unit0,s_unit1;
 
GF_mult_add_syndromes    unit0
(
.clk(clk),
.reset(reset),
.CE(CE_GF_mult_add),
.ip1(ip1_0),
.ip2(ip2_0),
.count_in(count_in),
/// active high flag will be active for one clock when S of the RS_block is ready 
.S_Ready(S_Ready_0),
 /// decimal format output syndromes value
.S(s_unit0)
);
 
 
 
GF_mult_add_syndromes    unit1
(
.clk(clk),
.reset(reset),
.CE(CE_GF_mult_add),
.ip1(ip1_1),
.ip2(ip2_1),
.count_in(count_in),
.S_Ready(),
 /// decimal format output syndromes value
.S(s_unit1)
);
 
 
/////////////////// control inputs to two syndromes units//////////
 
always@(posedge clk or posedge reset)
begin
        if (reset)
                begin
                        CE_GF_mult_add<=0;
                        count_in<=7;
                        ip1_0<=0;ip2_0<=0;
                        ip1_1<=0;ip2_1<=0;
                end
        else
                begin
                        if(CE1)
                                begin
                                        CE_GF_mult_add<=1;
                                        count_in<=0;
                                        ip1_0<=out_GF_ascending;
                                        ip1_1<=out_GF_ascending;
                                end
                        if (&count_in  &&  !CE1)
                                begin
                                        count_in <= 3'd7;
                                        CE_GF_mult_add<=0;
                                end
                        else
                                count_in <= count_in+1;
 
                        case(count_in)
                        0:
                                begin
                                        ip2_0<=x_power2;
                                        ip2_1<=x_power3;
                                end
 
                        1:
                                begin
                                        ip2_0<=x_power4;
                                        ip2_1<=x_power5;
                                end
 
                        2:
                                begin
                                        ip2_0<=x_power6;
                                        ip2_1<=x_power7;
                                end
 
                        3:
                                begin
                                        ip2_0<=x_power8;
                                        ip2_1<=x_power9;
                                end
 
                        4:
                                begin
                                        ip2_0<=x_power10;
                                        ip2_1<=x_power11;
                                end
 
                        5:
                                begin
                                        ip2_0<=x_power12;
                                        ip2_1<=x_power13;
                                end
 
                        6:
                                begin
                                        ip2_0<=x_power14;
                                        ip2_1<=x_power15;
                                end
                        default:
                                begin
                                        ip2_0<=x_power0;
                                        ip2_1<=x_power1;
                                end
                        endcase
                end
end
 
 
/////////////////// control output 16 syndromes values/////////////
 
reg [2:0] cnt8;
 
always@(posedge clk or posedge reset)
begin
        if (reset)
                begin
                        cnt8<=7;
                        S_Ready<=0;
                        s0<=0;s1<=0;s2<=0;s3<=0;s4<=0;s5<=0;s6<=0;s7<=0;
                        s8<=0;s9<=0;s10<=0;s11<=0;s12<=0;s13<=0;s14<=0;s15<=0;
                end
        else
                begin
                        if(S_Ready_0)
                                begin
                                        cnt8<=0;
                                end
 
                        if (&cnt8  &&  !S_Ready_0)
                                begin
                                        cnt8 <= 3'd7;
                                end
                        else
                                cnt8<=cnt8+1;
 
 
                        case (cnt8)
                                0:begin s2<=s_unit0; s3<=s_unit1; end
                                1:begin s4<=s_unit0; s5<=s_unit1; end
                                2:begin s6<=s_unit0; s7<=s_unit1; end
                                3:begin s8<=s_unit0; s9<=s_unit1; end
                                4:begin s10<=s_unit0; s11<=s_unit1; end
                                5:begin s12<=s_unit0; s13<=s_unit1; end
                                6:begin s14<=s_unit0; s15<=s_unit1;   S_Ready<=1; end
                                default:begin  s0<=s_unit0; s1<=s_unit1; end
                        endcase
 
                        if (S_Ready)
                                S_Ready<=0;
                end
end
 
endmodule

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Subversion Repositories reed_solomon_decoder

[/] [reed_solomon_decoder/] [trunk/] [rtl/] [input_syndromes.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	aelmahmoud	`/* This program is free software: you can redistribute it and/or modify`
2			`it under the terms of the GNU General Public License as published by`
3			`the Free Software Foundation, either version 3 of the License, or`
4			`(at your option) any later version.`
5
6			`This program is distributed in the hope that it will be useful,`
7			`but WITHOUT ANY WARRANTY; without even the implied warranty of`
8			`MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
9			`GNU General Public License for more details.`
10
11			`You should have received a copy of the GNU General Public License`
12			`along with this program. If not, see <http://www.gnu.org/licenses/>.`
13
14			`Email : semiconductors@varkongroup.com`
15			`Tel : 1-732-447-8611`
16
17			`*/`
18
19
20
21			`//// input stage of reed-solomon decoder and syndromes calculation`
22			`//// inputs will be buffered on pipelining rams and it will be used`
23			`////to calcultes syndromes for each block`
24			`module input_syndromes`
25			`(`
26			`input clk, // clk planned to be 56 mega`
27			`input reset, // asynchorounus active high reset`
28			`// chip enable active high flag should be active for one clock with every input`
29			`input CE,`
30			`input [7:0] input_byte, // input byte`
31			`input [7:0] R_Add, // read address to read from inputs pipeling memories`
32			`/// input read enable to the input pipeling memories (1 for mem0, and 0 for mem1 )`
33			`input RE,`
34
35			`/// syndromes 16 elements`
36			`/// active high flag will be active for one clock when Syndromes values are ready`
37			`output reg S_Ready,`
38			`output reg [7:0] s0,s1,s2,s3,s4,s5,s6,s7,s8,s9,s10,s11,s12,s13,s14,s15,`
39			`output [7:0] Read_byte /// output byte from input pipelinig memories`
40			`);`
41
42
43
44			`reg WE;`
45			`reg [7:0] input_byte0;`
46			`reg [7:0] W_Add;`
47			`wire [7:0] out_byte_0,out_byte_1;`
48
49
50
51
52
53			`assign Read_byte = (RE)? out_byte_0:out_byte_1;`
54			`//////////////////////////////////////////////////////////////`
55			`//////////////////////////////////////////////////////////////`
56			`/////// input pipelining memories`
57			`DP_RAM #(.num_words(205),.address_width(8),.data_width(8))`
58			`mem_in_0`
59
60			`(`
61			`.clk(clk),`
62			`.we(WE),`
63			`.re(RE),`
64			`.address_read(R_Add),`
65			`.address_write(W_Add),`
66			`.data_in(input_byte0),`
67			`.data_out(out_byte_0)`
68			`);`
69
70			`DP_RAM #(.num_words(205),.address_width(8),.data_width(8))`
71			`mem_in_1`
72			`(`
73			`.clk(clk),`
74			`.we(!WE),`
75			`.re(!RE),`
76			`.address_read(R_Add),`
77			`.address_write(W_Add),`
78			`.data_in(input_byte0),`
79			`.data_out(out_byte_1)`
80			`);`
81
82
83
84
85
86
87			`//////////////////////////////////////////////////////////////`
88			`/////////////////////////////////////////////////////////////`
89			`////// input handling`
90
91			`reg CE0,CE1;`
92			`reg [7:0] Address_GF_ascending;`
93			`wire [7:0] out_GF_ascending;`
94
95
96			`always@(posedge clk or posedge reset)`
97			`begin`
98			`if (reset)`
99			`begin`
100			`WE<=1; /// use mem0 first`
101			`W_Add<=204;`
102			`input_byte0<=0;`
103			`CE0<=0;`
104			`CE1<=0;`
105			`Address_GF_ascending<=0;`
106			`end`
107			`else`
108			`begin`
109
110
111			`// two delay lines to input CE`
112			`CE0<=CE;`
113			`CE1<=CE0; // now can read from memory`
114
115			`if(CE)`
116			`begin`
117			`// one delay line for input as address of memory changes after one clock from CE`
118			`input_byte0<=input_byte;`
119			`Address_GF_ascending<=input_byte;`
120
121			`// does not need to add one like matlab as memory index from 0 to 255 not from 1:256`
122			`if (W_Add == 0)`
123			`begin`
124			`WE <= ~WE;`
125			`W_Add <=203;`
126			`end`
127			`else`
128			`W_Add<=W_Add-1;`
129			`end`
130			`end`
131			`end`
132
133
134
135
136
137
138
139
140			`///////////// instant of GF_matrix_ascending_binary Rom/////////////`
141			`GF_matrix_ascending_binary rom_instant`
142			`(`
143			`.clk(clk),`
144			`.re(1'b1),`
145			`.address_read(Address_GF_ascending),`
146			`.data_out(out_GF_ascending)`
147			`);`
148
149
150			`/////////////////////////////////////////////////////`
151			`////////////////////////////////////////////////////`
152			`////// x_power generation`
153
154			`reg [7:0] x_power_0;`
155
156			`reg [8:0] x1;`
157			`reg [7:0] x_power_1;`
158
159			`reg [8:0] x2;`
160			`reg [7:0] x_power_2;`
161
162			`reg [8:0] x3;`
163			`reg [7:0] x_power_3;`
164
165			`reg [8:0] x4;`
166			`reg [7:0] x_power_4;`
167
168			`reg [8:0] x5;`
169			`reg [7:0] x_power_5;`
170
171			`reg [8:0] x6;`
172			`reg [7:0] x_power_6;`
173
174			`reg [8:0] x7;`
175			`reg [7:0] x_power_7;`
176
177			`reg [8:0] x8;`
178			`reg [7:0] x_power_8;`
179
180
181			`reg [8:0] x9;`
182			`reg [7:0] x_power_9;`
183
184			`reg [8:0] x10;`
185			`reg [7:0] x_power_10;`
186
187			`reg [8:0] x11;`
188			`reg [7:0] x_power_11;`
189
190			`reg [8:0] x12;`
191			`reg [7:0] x_power_12;`
192
193			`reg [8:0] x13;`
194			`reg [7:0] x_power_13;`
195
196			`reg [8:0] x14;`
197			`reg [7:0] x_power_14;`
198
199			`reg [8:0] x15;`
200			`reg [7:0] x_power_15;`
201			`always@(posedge clk or posedge reset)`
202			`begin`
203			`if (reset)`
204			`begin`
205			`x_power_0<=0;`
206
207			`x1<=0;`
208			`x_power_1<=0;`
209			`x2<=0;`
210			`x_power_2<=0;`
211			`x3<=0;`
212			`x_power_3<=0;`
213			`x4<=0;`
214			`x_power_4<=0;`
215			`x5<=0;`
216			`x_power_5<=0;`
217			`x6<=0;`
218			`x_power_6<=0;`
219			`x7<=0;`
220			`x_power_7<=0;`
221			`x8<=0;`
222			`x_power_8<=0;`
223			`x9<=0;`
224			`x_power_9<=0;`
225			`x10<=0;`
226			`x_power_10<=0;`
227			`x11<=0;`
228			`x_power_11<=0;`
229			`x12<=0;`
230			`x_power_12<=0;`
231			`x13<=0;`
232			`x_power_13<=0;`
233			`x14<=0;`
234			`x_power_14<=0;`
235			`x15<=0;`
236			`x_power_15<=0;`
237			`end`
238			`else`
239			`begin`
240			`if (CE)`
241			`begin`
242			`if (x_power_0 == 0)`
243			`begin`
244			`x_power_0<=203;`
245			`x1<=151;`
246			`x2<=99;`
247			`x3<=47;`
248			`x4<=250;`
249			`x5<=198;`
250			`x6<=146;`
251			`x7<=94;`
252			`x8<=42;`
253			`x9<=245;`
254			`x10<=193;`
255			`x11<=141;`
256			`x12<=89;`
257			`x13<=37;`
258			`x14<=240;`
259			`x15<=188;`
260			`end`
261			`else`
262			`begin`
263			`x_power_0<= x_power_0 - 1;`
264			`x1<=x_power_1 - 2;`
265			`x2<=x_power_2 - 3;`
266			`x3<=x_power_3 - 4;`
267			`x4<=x_power_4 - 5;`
268			`x5<=x_power_5 - 6;`
269			`x6<=x_power_6 - 7;`
270			`x7<=x_power_7 - 8;`
271			`x8<=x_power_8 - 9;`
272			`x9<=x_power_9 - 10;`
273			`x10<=x_power_10 - 11;`
274			`x11<=x_power_11 - 12;`
275			`x12<=x_power_12 - 13;`
276			`x13<=x_power_13 - 14;`
277			`x14<=x_power_14 - 15;`
278			`x15<=x_power_15 - 16;`
279			`end`
280
281			`end`
282
283			`x_power_1<= x1[7:0] - x1[8];`
284			`x_power_2<= x2[7:0] - x2[8];`
285			`x_power_3<= x3[7:0] - x3[8];`
286			`x_power_4<= x4[7:0] - x4[8];`
287			`x_power_5<= x5[7:0] - x5[8];`
288			`x_power_6<= x6[7:0] - x6[8];`
289			`x_power_7<= x7[7:0] - x7[8];`
290			`x_power_8<= x8[7:0] - x8[8];`
291			`x_power_9<= x9[7:0] - x9[8];`
292			`x_power_10<= x10[7:0] - x10[8];`
293			`x_power_11<= x11[7:0] - x11[8];`
294			`x_power_12<= x12[7:0] - x12[8];`
295			`x_power_13<= x13[7:0] - x13[8];`
296			`x_power_14<= x14[7:0] - x14[8];`
297			`x_power_15<= x15[7:0] - x15[8];`
298			`end`
299			`end`
300			`//// these wires to replace every FF with 00`
301			`wire [7:0] x_power0,x_power1,x_power2,x_power3,x_power4,x_power5,x_power6,x_power7;`
302			`wire [7:0] x_power8,x_power9,x_power10,x_power11,x_power12,x_power13,x_power14,x_power15;`
303
304			`assign x_power0 = x_power_0;`
305			`assign x_power1 = x_power_1;`
306			`assign x_power2 = (&x_power_2)? 8'h00:x_power_2;`
307			`assign x_power3 = x_power_3;`
308			`assign x_power4 = (&x_power_4)? 8'h00:x_power_4;`
309			`assign x_power5 = (&x_power_5)? 8'h00:x_power_5;`
310			`assign x_power6 = x_power_6;`
311			`assign x_power7 = x_power_7;`
312			`assign x_power8 = (&x_power_8)? 8'h00:x_power_8;`
313			`assign x_power9 = (&x_power_9)? 8'h00:x_power_9;`
314			`assign x_power10 = x_power_10;`
315			`assign x_power11 = (&x_power_11)? 8'h00:x_power_11;`
316			`assign x_power12 = x_power_12;`
317			`assign x_power13 = x_power_13;`
318			`assign x_power14 = (&x_power_14)? 8'h00:x_power_14;`
319			`assign x_power15 = x_power_15;`
320			`//////////////////////////////////////////////////////////////////`
321			`/////////////////////////////////////////////////////////////////`
322
323
324			`//////////////// two instants of syndromes calculation unit ///////////////`
325
326			`reg CE_GF_mult_add;`
327			`reg [7:0] ip1_0,ip2_0;`
328			`reg [7:0] ip1_1,ip2_1;`
329			`reg [2:0] count_in;`
330			`wire S_Ready_0;`
331			`wire [7:0] s_unit0,s_unit1;`
332
333			`GF_mult_add_syndromes unit0`
334			`(`
335			`.clk(clk),`
336			`.reset(reset),`
337			`.CE(CE_GF_mult_add),`
338			`.ip1(ip1_0),`
339			`.ip2(ip2_0),`
340			`.count_in(count_in),`
341			`/// active high flag will be active for one clock when S of the RS_block is ready`
342			`.S_Ready(S_Ready_0),`
343			`/// decimal format output syndromes value`
344			`.S(s_unit0)`
345			`);`
346
347
348
349			`GF_mult_add_syndromes unit1`
350			`(`
351			`.clk(clk),`
352			`.reset(reset),`
353			`.CE(CE_GF_mult_add),`
354			`.ip1(ip1_1),`
355			`.ip2(ip2_1),`
356			`.count_in(count_in),`
357			`.S_Ready(),`
358			`/// decimal format output syndromes value`
359			`.S(s_unit1)`
360			`);`
361
362
363			`/////////////////// control inputs to two syndromes units//////////`
364
365			`always@(posedge clk or posedge reset)`
366			`begin`
367			`if (reset)`
368			`begin`
369			`CE_GF_mult_add<=0;`
370			`count_in<=7;`
371			`ip1_0<=0;ip2_0<=0;`
372			`ip1_1<=0;ip2_1<=0;`
373			`end`
374			`else`
375			`begin`
376			`if(CE1)`
377			`begin`
378			`CE_GF_mult_add<=1;`
379			`count_in<=0;`
380			`ip1_0<=out_GF_ascending;`
381			`ip1_1<=out_GF_ascending;`
382			`end`
383			`if (&count_in && !CE1)`
384			`begin`
385			`count_in <= 3'd7;`
386			`CE_GF_mult_add<=0;`
387			`end`
388			`else`
389			`count_in <= count_in+1;`
390
391			`case(count_in)`
392			`0:`
393			`begin`
394			`ip2_0<=x_power2;`
395			`ip2_1<=x_power3;`
396			`end`
397
398			`1:`
399			`begin`
400			`ip2_0<=x_power4;`
401			`ip2_1<=x_power5;`
402			`end`
403
404			`2:`
405			`begin`
406			`ip2_0<=x_power6;`
407			`ip2_1<=x_power7;`
408			`end`
409
410			`3:`
411			`begin`
412			`ip2_0<=x_power8;`
413			`ip2_1<=x_power9;`
414			`end`
415
416			`4:`
417			`begin`
418			`ip2_0<=x_power10;`
419			`ip2_1<=x_power11;`
420			`end`
421
422			`5:`
423			`begin`
424			`ip2_0<=x_power12;`
425			`ip2_1<=x_power13;`
426			`end`
427
428			`6:`
429			`begin`
430			`ip2_0<=x_power14;`
431			`ip2_1<=x_power15;`
432			`end`
433			`default:`
434			`begin`
435			`ip2_0<=x_power0;`
436			`ip2_1<=x_power1;`
437			`end`
438			`endcase`
439			`end`
440			`end`
441
442
443			`/////////////////// control output 16 syndromes values/////////////`
444
445			`reg [2:0] cnt8;`
446
447			`always@(posedge clk or posedge reset)`
448			`begin`
449			`if (reset)`
450			`begin`
451			`cnt8<=7;`
452			`S_Ready<=0;`
453			`s0<=0;s1<=0;s2<=0;s3<=0;s4<=0;s5<=0;s6<=0;s7<=0;`
454			`s8<=0;s9<=0;s10<=0;s11<=0;s12<=0;s13<=0;s14<=0;s15<=0;`
455			`end`
456			`else`
457			`begin`
458			`if(S_Ready_0)`
459			`begin`
460			`cnt8<=0;`
461			`end`
462
463			`if (&cnt8 && !S_Ready_0)`
464			`begin`
465			`cnt8 <= 3'd7;`
466			`end`
467			`else`
468			`cnt8<=cnt8+1;`
469
470
471			`case (cnt8)`
472			`0:begin s2<=s_unit0; s3<=s_unit1; end`
473			`1:begin s4<=s_unit0; s5<=s_unit1; end`
474			`2:begin s6<=s_unit0; s7<=s_unit1; end`
475			`3:begin s8<=s_unit0; s9<=s_unit1; end`
476			`4:begin s10<=s_unit0; s11<=s_unit1; end`
477			`5:begin s12<=s_unit0; s13<=s_unit1; end`
478			`6:begin s14<=s_unit0; s15<=s_unit1; S_Ready<=1; end`
479			`default:begin s0<=s_unit0; s1<=s_unit1; end`
480			`endcase`
481
482			`if (S_Ready)`
483			`S_Ready<=0;`
484			`end`
485			`end`
486
487			`endmodule`