1 |
2 |
robfinch |
// ============================================================================
|
2 |
|
|
// __
|
3 |
|
|
// \\__/ o\ (C) 2022 Robert Finch, Waterloo
|
4 |
|
|
// \ __ / All rights reserved.
|
5 |
|
|
// \/_// robfinch@finitron.ca
|
6 |
|
|
// ||
|
7 |
|
|
//
|
8 |
|
|
// io_bitmap.sv
|
9 |
|
|
//
|
10 |
|
|
// BSD 3-Clause License
|
11 |
|
|
// Redistribution and use in source and binary forms, with or without
|
12 |
|
|
// modification, are permitted provided that the following conditions are met:
|
13 |
|
|
//
|
14 |
|
|
// 1. Redistributions of source code must retain the above copyright notice, this
|
15 |
|
|
// list of conditions and the following disclaimer.
|
16 |
|
|
//
|
17 |
|
|
// 2. Redistributions in binary form must reproduce the above copyright notice,
|
18 |
|
|
// this list of conditions and the following disclaimer in the documentation
|
19 |
|
|
// and/or other materials provided with the distribution.
|
20 |
|
|
//
|
21 |
|
|
// 3. Neither the name of the copyright holder nor the names of its
|
22 |
|
|
// contributors may be used to endorse or promote products derived from
|
23 |
|
|
// this software without specific prior written permission.
|
24 |
|
|
//
|
25 |
|
|
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
26 |
|
|
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
27 |
|
|
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
28 |
|
|
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
29 |
|
|
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
30 |
|
|
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
31 |
|
|
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
32 |
|
|
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
33 |
|
|
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
34 |
|
|
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
35 |
|
|
//
|
36 |
|
|
// ============================================================================
|
37 |
|
|
|
38 |
|
|
module io_bitmap(rst_i, clk_i, cs_i, cyc_i, stb_i, ack_o, we_i, asid_i, adr_i, dat_i, dat_o,
|
39 |
|
|
iocs_i, gate_o, gate_en);
|
40 |
|
|
input rst_i;
|
41 |
|
|
input clk_i;
|
42 |
|
|
input cs_i;
|
43 |
|
|
input cyc_i;
|
44 |
|
|
input stb_i;
|
45 |
|
|
output ack_o;
|
46 |
|
|
input we_i;
|
47 |
|
|
input [5:0] asid_i;
|
48 |
|
|
input [19:0] adr_i;
|
49 |
|
|
input [31:0] dat_i;
|
50 |
|
|
output reg [31:0] dat_o;
|
51 |
|
|
input iocs_i;
|
52 |
|
|
output reg gate_o;
|
53 |
|
|
output gate_en;
|
54 |
|
|
|
55 |
|
|
wire [31:0] douta, doutb;
|
56 |
|
|
reg ena, enb;
|
57 |
|
|
|
58 |
|
|
ack_gen #(
|
59 |
|
|
.READ_STAGES(2),
|
60 |
|
|
.WRITE_STAGES(1),
|
61 |
|
|
.REGISTER_OUTPUT(1)
|
62 |
|
|
) uag1
|
63 |
|
|
(
|
64 |
|
|
.rst_i(rst_i),
|
65 |
|
|
.clk_i(clk_i),
|
66 |
|
|
.ce_i(1'b1),
|
67 |
|
|
.rid_i('d0),
|
68 |
|
|
.wid_i('d0),
|
69 |
|
|
.i(ena & ~we_i),
|
70 |
|
|
.we_i(ena & we_i),
|
71 |
|
|
.o(ack_o),
|
72 |
|
|
.rid_o(),
|
73 |
|
|
.wid_o()
|
74 |
|
|
);
|
75 |
|
|
|
76 |
|
|
ack_gen #(
|
77 |
|
|
.READ_STAGES(2),
|
78 |
|
|
.WRITE_STAGES(1),
|
79 |
|
|
.REGISTER_OUTPUT(1)
|
80 |
|
|
) uag2
|
81 |
|
|
(
|
82 |
|
|
.rst_i(rst_i),
|
83 |
|
|
.clk_i(clk_i),
|
84 |
|
|
.ce_i(1'b1),
|
85 |
|
|
.rid_i('d0),
|
86 |
|
|
.wid_i('d0),
|
87 |
|
|
.i(enb & ~we_i),
|
88 |
|
|
.we_i(enb & we_i),
|
89 |
|
|
.o(gate_en),
|
90 |
|
|
.rid_o(),
|
91 |
|
|
.wid_o()
|
92 |
|
|
);
|
93 |
|
|
|
94 |
|
|
always_comb
|
95 |
|
|
ena = cs_i & cyc_i & stb_i;
|
96 |
|
|
always_comb
|
97 |
|
|
enb = iocs_i & cyc_i & stb_i;
|
98 |
|
|
|
99 |
|
|
// xpm_memory_tdpram: True Dual Port RAM
|
100 |
|
|
// Xilinx Parameterized Macro, version 2022.2
|
101 |
|
|
|
102 |
|
|
xpm_memory_tdpram #(
|
103 |
|
|
.ADDR_WIDTH_A(13), // DECIMAL
|
104 |
|
|
.ADDR_WIDTH_B(13), // DECIMAL
|
105 |
|
|
.AUTO_SLEEP_TIME(0), // DECIMAL
|
106 |
|
|
.BYTE_WRITE_WIDTH_A(32), // DECIMAL
|
107 |
|
|
.BYTE_WRITE_WIDTH_B(32), // DECIMAL
|
108 |
|
|
.CASCADE_HEIGHT(0), // DECIMAL
|
109 |
|
|
.CLOCKING_MODE("common_clock"), // String
|
110 |
|
|
.ECC_MODE("no_ecc"), // String
|
111 |
|
|
.MEMORY_INIT_FILE("none"), // String
|
112 |
|
|
.MEMORY_INIT_PARAM("0"), // String
|
113 |
|
|
.MEMORY_OPTIMIZATION("true"), // String
|
114 |
|
|
.MEMORY_PRIMITIVE("auto"), // String
|
115 |
|
|
.MEMORY_SIZE(4096*64), // DECIMAL
|
116 |
|
|
.MESSAGE_CONTROL(0), // DECIMAL
|
117 |
|
|
.READ_DATA_WIDTH_A(32), // DECIMAL
|
118 |
|
|
.READ_DATA_WIDTH_B(32), // DECIMAL
|
119 |
|
|
.READ_LATENCY_A(2), // DECIMAL
|
120 |
|
|
.READ_LATENCY_B(1), // DECIMAL
|
121 |
|
|
.READ_RESET_VALUE_A("0"), // String
|
122 |
|
|
.READ_RESET_VALUE_B("0"), // String
|
123 |
|
|
.RST_MODE_A("SYNC"), // String
|
124 |
|
|
.RST_MODE_B("SYNC"), // String
|
125 |
|
|
.SIM_ASSERT_CHK(0), // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
|
126 |
|
|
.USE_EMBEDDED_CONSTRAINT(0), // DECIMAL
|
127 |
|
|
.USE_MEM_INIT(1), // DECIMAL
|
128 |
|
|
.USE_MEM_INIT_MMI(0), // DECIMAL
|
129 |
|
|
.WAKEUP_TIME("disable_sleep"), // String
|
130 |
|
|
.WRITE_DATA_WIDTH_A(32), // DECIMAL
|
131 |
|
|
.WRITE_DATA_WIDTH_B(32), // DECIMAL
|
132 |
|
|
.WRITE_MODE_A("no_change"), // String
|
133 |
|
|
.WRITE_MODE_B("no_change"), // String
|
134 |
|
|
.WRITE_PROTECT(1) // DECIMAL
|
135 |
|
|
)
|
136 |
|
|
xpm_memory_tdpram_inst (
|
137 |
|
|
.dbiterra(), // 1-bit output: Status signal to indicate double bit error occurrence
|
138 |
|
|
// on the data output of port A.
|
139 |
|
|
|
140 |
|
|
.dbiterrb(), // 1-bit output: Status signal to indicate double bit error occurrence
|
141 |
|
|
// on the data output of port A.
|
142 |
|
|
|
143 |
|
|
.douta(douta), // READ_DATA_WIDTH_A-bit output: Data output for port A read operations.
|
144 |
|
|
.doutb(doutb), // READ_DATA_WIDTH_B-bit output: Data output for port B read operations.
|
145 |
|
|
.sbiterra(), // 1-bit output: Status signal to indicate single bit error occurrence
|
146 |
|
|
// on the data output of port A.
|
147 |
|
|
|
148 |
|
|
.sbiterrb(), // 1-bit output: Status signal to indicate single bit error occurrence
|
149 |
|
|
// on the data output of port B.
|
150 |
|
|
|
151 |
|
|
.addra({asid_i[5:0],adr_i[ 8: 2]}), // ADDR_WIDTH_A-bit input: Address for port A write and read operations.
|
152 |
|
|
.addrb({asid_i[5:0],adr_i[19:13]}), // ADDR_WIDTH_B-bit input: Address for port B write and read operations.
|
153 |
|
|
.clka(clk_i), // 1-bit input: Clock signal for port A. Also clocks port B when
|
154 |
|
|
// parameter CLOCKING_MODE is "common_clock".
|
155 |
|
|
|
156 |
|
|
.clkb(clk_i), // 1-bit input: Clock signal for port B when parameter CLOCKING_MODE is
|
157 |
|
|
// "independent_clock". Unused when parameter CLOCKING_MODE is
|
158 |
|
|
// "common_clock".
|
159 |
|
|
|
160 |
|
|
.dina(dat_i), // WRITE_DATA_WIDTH_A-bit input: Data input for port A write operations.
|
161 |
|
|
.dinb(32'h0), // WRITE_DATA_WIDTH_B-bit input: Data input for port B write operations.
|
162 |
|
|
.ena(ena), // 1-bit input: Memory enable signal for port A. Must be high on clock
|
163 |
|
|
// cycles when read or write operations are initiated. Pipelined
|
164 |
|
|
// internally.
|
165 |
|
|
|
166 |
|
|
.enb(enb), // 1-bit input: Memory enable signal for port B. Must be high on clock
|
167 |
|
|
// cycles when read or write operations are initiated. Pipelined
|
168 |
|
|
// internally.
|
169 |
|
|
|
170 |
|
|
.injectdbiterra(1'b0), // 1-bit input: Controls double bit error injection on input data when
|
171 |
|
|
// ECC enabled (Error injection capability is not available in
|
172 |
|
|
// "decode_only" mode).
|
173 |
|
|
|
174 |
|
|
.injectdbiterrb(1'b0), // 1-bit input: Controls double bit error injection on input data when
|
175 |
|
|
// ECC enabled (Error injection capability is not available in
|
176 |
|
|
// "decode_only" mode).
|
177 |
|
|
|
178 |
|
|
.injectsbiterra(1'b0), // 1-bit input: Controls single bit error injection on input data when
|
179 |
|
|
// ECC enabled (Error injection capability is not available in
|
180 |
|
|
// "decode_only" mode).
|
181 |
|
|
|
182 |
|
|
.injectsbiterrb(1'b0), // 1-bit input: Controls single bit error injection on input data when
|
183 |
|
|
// ECC enabled (Error injection capability is not available in
|
184 |
|
|
// "decode_only" mode).
|
185 |
|
|
|
186 |
|
|
.regcea(1'b1), // 1-bit input: Clock Enable for the last register stage on the output
|
187 |
|
|
// data path.
|
188 |
|
|
|
189 |
|
|
.regceb(1'b1), // 1-bit input: Clock Enable for the last register stage on the output
|
190 |
|
|
// data path.
|
191 |
|
|
|
192 |
|
|
.rsta(1'b0), // 1-bit input: Reset signal for the final port A output register stage.
|
193 |
|
|
// Synchronously resets output port douta to the value specified by
|
194 |
|
|
// parameter READ_RESET_VALUE_A.
|
195 |
|
|
|
196 |
|
|
.rstb(1'b0), // 1-bit input: Reset signal for the final port B output register stage.
|
197 |
|
|
// Synchronously resets output port doutb to the value specified by
|
198 |
|
|
// parameter READ_RESET_VALUE_B.
|
199 |
|
|
|
200 |
|
|
.sleep(1'b0), // 1-bit input: sleep signal to enable the dynamic power saving feature.
|
201 |
|
|
.wea(we_i), // WRITE_DATA_WIDTH_A/BYTE_WRITE_WIDTH_A-bit input: Write enable vector
|
202 |
|
|
// for port A input data port dina. 1 bit wide when word-wide writes are
|
203 |
|
|
// used. In byte-wide write configurations, each bit controls the
|
204 |
|
|
// writing one byte of dina to address addra. For example, to
|
205 |
|
|
// synchronously write only bits [15-8] of dina when WRITE_DATA_WIDTH_A
|
206 |
|
|
// is 32, wea would be 4'b0010.
|
207 |
|
|
|
208 |
|
|
.web(1'b0) // WRITE_DATA_WIDTH_B/BYTE_WRITE_WIDTH_B-bit input: Write enable vector
|
209 |
|
|
// for port B input data port dinb. 1 bit wide when word-wide writes are
|
210 |
|
|
// used. In byte-wide write configurations, each bit controls the
|
211 |
|
|
// writing one byte of dinb to address addrb. For example, to
|
212 |
|
|
// synchronously write only bits [15-8] of dinb when WRITE_DATA_WIDTH_B
|
213 |
|
|
// is 32, web would be 4'b0010.
|
214 |
|
|
|
215 |
|
|
);
|
216 |
|
|
|
217 |
|
|
always_ff @(posedge clk_i)
|
218 |
|
|
if (ena)
|
219 |
|
|
dat_o <= douta;
|
220 |
|
|
else
|
221 |
|
|
dat_o <= 32'd0;
|
222 |
|
|
|
223 |
|
|
always_comb
|
224 |
|
|
gate_o <= doutb[adr_i[12:8]];
|
225 |
|
|
|
226 |
|
|
endmodule
|