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// ============================================================================

//        __

//   \\__/ o\    (C) 2022  Robert Finch, Waterloo

//    \  __ /    All rights reserved.

//     \/_//     robfinch@finitron.ca

//       ||

//

//      io_bitmap.sv

//

// BSD 3-Clause License

// Redistribution and use in source and binary forms, with or without

// modification, are permitted provided that the following conditions are met:

//

// 1. Redistributions of source code must retain the above copyright notice, this

//    list of conditions and the following disclaimer.

//

// 2. Redistributions in binary form must reproduce the above copyright notice,

//    this list of conditions and the following disclaimer in the documentation

//    and/or other materials provided with the distribution.

//

// 3. Neither the name of the copyright holder nor the names of its

//    contributors may be used to endorse or promote products derived from

//    this software without specific prior written permission.

//

// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"

// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE

// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE

// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL

// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR

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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

//

// ============================================================================

module io_bitmap(rst_i, clk_i, cs_i, cyc_i, stb_i, ack_o, we_i, asid_i, adr_i, dat_i, dat_o,

        iocs_i, gate_o, gate_en);

input rst_i;

input clk_i;

input cs_i;

input cyc_i;

input stb_i;

output ack_o;

input we_i;

input [5:0] asid_i;

input [19:0] adr_i;

input [31:0] dat_i;

output reg [31:0] dat_o;

input iocs_i;

output reg gate_o;

output gate_en;

wire [31:0] douta, doutb;

reg ena, enb;

ack_gen #(

        .READ_STAGES(2),

        .WRITE_STAGES(1),

        .REGISTER_OUTPUT(1)

) uag1

(

        .rst_i(rst_i),

        .clk_i(clk_i),

        .ce_i(1'b1),

        .rid_i('d0),

        .wid_i('d0),

        .i(ena & ~we_i),

        .we_i(ena & we_i),

        .o(ack_o),

        .rid_o(),

        .wid_o()

);

ack_gen #(

        .READ_STAGES(2),

        .WRITE_STAGES(1),

        .REGISTER_OUTPUT(1)

) uag2

(

        .rst_i(rst_i),

        .clk_i(clk_i),

        .ce_i(1'b1),

        .rid_i('d0),

        .wid_i('d0),

        .i(enb & ~we_i),

        .we_i(enb & we_i),

        .o(gate_en),

        .rid_o(),

        .wid_o()

);

always_comb

        ena = cs_i & cyc_i & stb_i;

always_comb

        enb = iocs_i & cyc_i & stb_i;

   // xpm_memory_tdpram: True Dual Port RAM

   // Xilinx Parameterized Macro, version 2022.2

   xpm_memory_tdpram #(

      .ADDR_WIDTH_A(13),               // DECIMAL

      .ADDR_WIDTH_B(13),               // DECIMAL

      .AUTO_SLEEP_TIME(0),            // DECIMAL

      .BYTE_WRITE_WIDTH_A(32),        // DECIMAL

      .BYTE_WRITE_WIDTH_B(32),        // DECIMAL

      .CASCADE_HEIGHT(0),             // DECIMAL

      .CLOCKING_MODE("common_clock"), // String

      .ECC_MODE("no_ecc"),            // String

      .MEMORY_INIT_FILE("none"),      // String

      .MEMORY_INIT_PARAM("0"),        // String

      .MEMORY_OPTIMIZATION("true"),   // String

      .MEMORY_PRIMITIVE("auto"),      // String

      .MEMORY_SIZE(4096*64),          // DECIMAL

      .MESSAGE_CONTROL(0),            // DECIMAL

      .READ_DATA_WIDTH_A(32),         // DECIMAL

      .READ_DATA_WIDTH_B(32),         // DECIMAL

      .READ_LATENCY_A(2),             // DECIMAL

      .READ_LATENCY_B(1),             // DECIMAL

      .READ_RESET_VALUE_A("0"),       // String

      .READ_RESET_VALUE_B("0"),       // String

      .RST_MODE_A("SYNC"),            // String

      .RST_MODE_B("SYNC"),            // String

      .SIM_ASSERT_CHK(0),             // DECIMAL; 0=disable simulation messages, 1=enable simulation messages

      .USE_EMBEDDED_CONSTRAINT(0),    // DECIMAL

      .USE_MEM_INIT(1),               // DECIMAL

      .USE_MEM_INIT_MMI(0),           // DECIMAL

      .WAKEUP_TIME("disable_sleep"),  // String

      .WRITE_DATA_WIDTH_A(32),        // DECIMAL

      .WRITE_DATA_WIDTH_B(32),        // DECIMAL

      .WRITE_MODE_A("no_change"),     // String

      .WRITE_MODE_B("no_change"),     // String

      .WRITE_PROTECT(1)               // DECIMAL

   )

   xpm_memory_tdpram_inst (

      .dbiterra(),             // 1-bit output: Status signal to indicate double bit error occurrence

                                       // on the data output of port A.

      .dbiterrb(),             // 1-bit output: Status signal to indicate double bit error occurrence

                                       // on the data output of port A.

      .douta(douta),                   // READ_DATA_WIDTH_A-bit output: Data output for port A read operations.

      .doutb(doutb),                   // READ_DATA_WIDTH_B-bit output: Data output for port B read operations.

      .sbiterra(),             // 1-bit output: Status signal to indicate single bit error occurrence

                                       // on the data output of port A.

      .sbiterrb(),             // 1-bit output: Status signal to indicate single bit error occurrence

                                       // on the data output of port B.

      .addra(adr_i[14: 2]),                                     // ADDR_WIDTH_A-bit input: Address for port A write and read operations.

      .addrb({asid_i[5:0],adr_i[19:13]}), // ADDR_WIDTH_B-bit input: Address for port B write and read operations.

      .clka(clk_i),                     // 1-bit input: Clock signal for port A. Also clocks port B when

                                       // parameter CLOCKING_MODE is "common_clock".

      .clkb(clk_i),                     // 1-bit input: Clock signal for port B when parameter CLOCKING_MODE is

                                       // "independent_clock". Unused when parameter CLOCKING_MODE is

                                       // "common_clock".

      .dina(dat_i),                     // WRITE_DATA_WIDTH_A-bit input: Data input for port A write operations.

      .dinb(32'h0),                     // WRITE_DATA_WIDTH_B-bit input: Data input for port B write operations.

      .ena(ena),                       // 1-bit input: Memory enable signal for port A. Must be high on clock

                                       // cycles when read or write operations are initiated. Pipelined

                                       // internally.

      .enb(enb),                       // 1-bit input: Memory enable signal for port B. Must be high on clock

                                       // cycles when read or write operations are initiated. Pipelined

                                       // internally.

      .injectdbiterra(1'b0), // 1-bit input: Controls double bit error injection on input data when

                                       // ECC enabled (Error injection capability is not available in

                                       // "decode_only" mode).

      .injectdbiterrb(1'b0), // 1-bit input: Controls double bit error injection on input data when

                                       // ECC enabled (Error injection capability is not available in

                                       // "decode_only" mode).

      .injectsbiterra(1'b0), // 1-bit input: Controls single bit error injection on input data when

                                       // ECC enabled (Error injection capability is not available in

                                       // "decode_only" mode).

      .injectsbiterrb(1'b0), // 1-bit input: Controls single bit error injection on input data when

                                       // ECC enabled (Error injection capability is not available in

                                       // "decode_only" mode).

      .regcea(1'b1),                 // 1-bit input: Clock Enable for the last register stage on the output

                                       // data path.

      .regceb(1'b1),                 // 1-bit input: Clock Enable for the last register stage on the output

                                       // data path.

      .rsta(1'b0),                     // 1-bit input: Reset signal for the final port A output register stage.

                                       // Synchronously resets output port douta to the value specified by

                                       // parameter READ_RESET_VALUE_A.

      .rstb(1'b0),                     // 1-bit input: Reset signal for the final port B output register stage.

                                       // Synchronously resets output port doutb to the value specified by

                                       // parameter READ_RESET_VALUE_B.

      .sleep(1'b0),                   // 1-bit input: sleep signal to enable the dynamic power saving feature.

      .wea(we_i),                       // WRITE_DATA_WIDTH_A/BYTE_WRITE_WIDTH_A-bit input: Write enable vector

                                       // for port A input data port dina. 1 bit wide when word-wide writes are

                                       // used. In byte-wide write configurations, each bit controls the

                                       // writing one byte of dina to address addra. For example, to

                                       // synchronously write only bits [15-8] of dina when WRITE_DATA_WIDTH_A

                                       // is 32, wea would be 4'b0010.

      .web(1'b0)                        // WRITE_DATA_WIDTH_B/BYTE_WRITE_WIDTH_B-bit input: Write enable vector

                                       // for port B input data port dinb. 1 bit wide when word-wide writes are

                                       // used. In byte-wide write configurations, each bit controls the

                                       // writing one byte of dinb to address addrb. For example, to

                                       // synchronously write only bits [15-8] of dinb when WRITE_DATA_WIDTH_B

                                       // is 32, web would be 4'b0010.

   );

always_ff @(posedge clk_i)

        if (ena)

                dat_o <= douta;

        else

                dat_o <= 32'd0;

always_ff @(posedge clk_i)

        gate_o <= doutb[adr_i[12:8]] & enb;

endmodule