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1 2 robfinch
`timescale 1ns / 1ps
2
// ============================================================================
3
//        __
4
//   \\__/ o\    (C) 2008-2022  Robert Finch, Waterloo
5
//    \  __ /    All rights reserved.
6
//     \/_//     robfinch@finitron.ca
7
//       ||
8
//
9
//      rf68000.sv
10
//
11
//
12
// BSD 3-Clause License
13
// Redistribution and use in source and binary forms, with or without
14
// modification, are permitted provided that the following conditions are met:
15
//
16
// 1. Redistributions of source code must retain the above copyright notice, this
17
//    list of conditions and the following disclaimer.
18
//
19
// 2. Redistributions in binary form must reproduce the above copyright notice,
20
//    this list of conditions and the following disclaimer in the documentation
21
//    and/or other materials provided with the distribution.
22
//
23
// 3. Neither the name of the copyright holder nor the names of its
24
//    contributors may be used to endorse or promote products derived from
25
//    this software without specific prior written permission.
26
//
27
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
28
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
29
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
30
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
31
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
33
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
34
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
35
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37
//
38
// ============================================================================
39
//
40
// Uncomment the following to optimize for performance. Increases the core size.
41
//`define OPT_PERF    1'b1
42
`define BIG_ENDIAN      1'b1
43
 
44
//`define SUPPORT_RETRY 1'b1
45
`define SUPPORT_MUL     1'b1
46
`define SUPPORT_DIV     1'b1
47
`define SUPPORT_BCD     1'b1
48
//`define SUPPORT_010   1'b1
49
`define SUPPORT_BITPAIRS 1'b1
50
 
51 3 robfinch
//`define HAS_MMU 1'b1
52
 
53 2 robfinch
//`define SUPPORT_TASK  1'b1
54
 
55
//`define SUPPORT_B24   1'b1            // To support 23-bit branch displacements
56
 
57
`define TRUE        1'b1
58
`define FALSE       1'b0
59
`define HIGH        1'b1
60
`define LOW         1'b0
61
 
62
`define RESET_VECTOR    32'h00000400
63
`define CSR_CORENO    32'hFFFFFFE0
64
`define CSR_TICK        32'hFFFFFFE4
65
`define CSR_ICNT                                32'hFFFFFFE8
66
`define CSR_TASK        32'hFFFFFFFC
67
 
68
//`define SSP_VEC       9'd000
69
`define RESET_VEC       9'd001
70
`define BUSERR_VEC      9'd002
71
`define ADDRERR_VEC     9'd003
72
`define ILLEGAL_VEC     9'd004
73
`define DBZ_VEC         9'd005
74
`define CHK_VEC         9'd006
75
`define TRAPV_VEC       9'd007
76
`define PRIV_VEC        9'd008
77
`define TRACE_VEC       9'd009
78
`define LINE10_VEC      9'd010
79
`define LINE15_VEC      9'd011
80
`define UNINITINT_VEC   9'd015
81
// Vectors 24-31 for IRQ's
82
`define SPURIOUS_VEC            9'd024
83
`define IRQ_VEC         9'd024
84
// Vectors 32-46 for TRAPQ instruction
85
`define TRAP_VEC        9'd032
86
`define DISP_VEC                                9'd063
87
`define USER64          9'd064
88
//`define NMI_TRAP        9'h1FE
89
`define RESET_TASK      9'h000
90
 
91
`define LDB             16'b0001_xxx0xx_xxxxxx
92
`define LDH             16'b0010_xxx0xx_xxxxxx
93
`define LDW             16'b0011_xxx0xx_xxxxxx
94
`define STB             16'b0001_xxx1xx_xxxxxx
95
`define STH             16'b0010_xxx1xx_xxxxxx
96
`define STW             16'b0011_xxx1xx_xxxxxx
97
 
98 3 robfinch
// DBcc also for Scc
99 2 robfinch
`define DBRA    8'h50
100
`define DBSR    8'h51
101
`define DBHI    8'h52
102
`define DBLS    8'h53
103
`define DBHS    8'h54
104
`define DBLO    8'h55
105
`define DBNE    8'h56
106
`define DBEQ    8'h57
107
`define DBVC    8'h58
108
`define DBVS    8'h59
109
`define DBPL    8'h5A
110
`define DBMI    8'h5B
111
`define DBGE    8'h5C
112
`define DBLT    8'h5D
113
`define DBGT    8'h5E
114
`define DBLE    8'h5F
115
 
116
`define BRA             8'h60
117
`define BSR             8'h61
118
`define BHI             8'h62
119
`define BLS             8'h63
120
`define BHS             8'h64
121
`define BLO             8'h65
122
`define BNE             8'h66
123
`define BEQ             8'h67
124
`define BVC             8'h68
125
`define BVS             8'h69
126
`define BPL             8'h6A
127
`define BMI             8'h6B
128
`define BGE             8'h6C
129
`define BLT             8'h6D
130
`define BGT             8'h6E
131
`define BLE             8'h6F
132
 
133
// 12000 LUTs / 80MHz
134
// slices
135
// 1600 FF's
136
// 2 MULTS
137
// 8 BRAMs
138
 
139
module rf68000(coreno_i, clken_i, rst_i, rst_o, clk_i, nmi_i, ipl_i, vpa_i,
140
        lock_o, cyc_o, stb_o, ack_i, err_i, rty_i, we_o, sel_o, fc_o,
141
        asid_o, mmus_o, ios_o, iops_o, adr_o, dat_i, dat_o);
142
typedef enum logic [7:0] {
143
        IFETCH = 8'd1,
144
        DECODE,
145
        RETSTATE,
146
        FETCH_BYTE,
147
        FETCH_WORD,
148
        FETCH_LWORD,
149
        FETCH_LWORDa,
150
        STORE_BYTE,
151
        USTORE_BYTE,
152
        // 10
153
        STORE_WORD,
154
        STORE_LWORD,
155
        STORE_LWORDa,
156
 
157
        LFETCH_BYTE,
158
        FETCH_BRDISP,
159
        FETCH_BRDISPa,
160
        FETCH_IMM16,
161
        FETCH_IMM16a,
162
        FETCH_IMM32,
163
        FETCH_IMM32a,
164
 
165
        // 20
166
        FETCH_IMM32b,
167
        JSR,
168
        JMP,
169
        DBRA,
170
 
171
        ADDQ,
172
        ADDQ2,
173
        ADDI,
174
        ADDI2,
175
        ADDI3,
176
        ADDI4,
177
 
178
        // 30
179
        ADD,
180
        ADD1,
181
 
182
        DIV1,
183
        DIV2,
184
 
185
        STORE_IN_DEST,
186
        SHIFT,
187
        SHIFT1,
188
        BIT,
189
        BIT1,
190
        BIT2,
191
 
192
        // 40
193
        RTD1,
194
        RTD2,
195
 
196
        RTE1,
197
        RTE2,
198
        RTE3,
199
        RTE4,
200
        RTE5,
201
        RTE6,
202
        RTE7,
203
        RTE8,
204
 
205
        // 50
206
        RTE9,
207
        RTE10,
208
        RTE11,
209
 
210
        RTS1,
211
        RTS2,
212
 
213
        LINK,
214
        LINK1,
215
        LINK2,
216
        UNLNK,
217
        UNLNK2,
218
 
219
        // 60
220
        JMP_VECTOR,
221
        JMP_VECTOR2,
222
        JMP_VECTOR3,
223
 
224
        NEG,
225
        NEGX,
226
        NEGX1,
227
        NOT,
228
        TAS,
229
        LEA,
230
        LEA2,
231
 
232
        //70
233
        EXG1,
234
 
235
        CMP,
236
        CMP1,
237
        CMPA,
238
        CMPM,
239
        CMPM1,  // defunct
240
 
241
        AND,
242
        AND1,
243
        EOR,
244
        ANDI_CCR,
245
 
246
        // 80
247
        ANDI_CCR2,
248
        ANDI_SR,
249
        ANDI_SRX,
250
        EORI_CCR,
251
        EORI_CCR2,
252
        EORI_SR,
253
        EORI_SRX,
254
        ORI_CCR,
255
        ORI_CCR2,
256
        ORI_SR,
257
 
258
        //90
259
        ORI_SRX,
260
        FETCH_NOP_BYTE,
261
        FETCH_NOP_WORD,
262
        FETCH_NOP_LWORD,
263
        FETCH_IMM8,
264
        FETCH_IMM8a,
265
        FETCH_D32,
266
        FETCH_D32a,
267
        FETCH_D32b,
268
        FETCH_D16,
269
 
270
        //100
271
        FETCH_D16a,
272
        FETCH_NDX,
273
        FETCH_NDXa,
274
 
275
        MOVE2CCR,
276
        MOVE2SR,
277
        MOVE2SRX,
278
 
279
        TRAP,
280
        TRAP3,
281
        TRAP3a,
282
        TRAP3b,
283
 
284
        //110
285
        TRAP4,
286
        TRAP5,
287
        TRAP6,
288
        TRAP7,
289
        TRAP7a,
290
        TRAP8,
291
        TRAP9,
292
        TRAP10,
293
        TRAP20,
294
        TRAP21,
295
 
296
        // 120
297
        TRAP22,
298
        TRAP23,
299
        TRAP24,
300
        TRAP25,
301
        TRAP26,
302
        INTA,
303
 
304
        RETRY,
305
        RETRY2,
306
 
307
        TST,
308
        MUL,
309
 
310
        // 130
311
        MUL1,
312
        STOP,
313
        STOP1,
314
        RESET,
315
        RESET2,
316
        RESET3,
317
        RESET4,
318
        RESET5,
319
        PEA1,
320
        PEA2,
321
 
322
        // 140
323
        PEA3,
324
        BCD,
325
        BCD0,
326
        BCD1,
327
        BCD2,
328
        BCD3,
329
        BCD4,
330
        OR,
331
 
332
        INT,
333
        INT2,
334
        INT3,
335
 
336
        // 150
337
        INT4,
338
 
339
        MOVEM_Xn2D,
340
        MOVEM_Xn2D2,
341
        MOVEM_Xn2D3,
342
        MOVEM_Xn2D4,
343
        MOVEM_s2Xn,
344
        MOVEM_s2Xn2,
345
        MOVEM_s2Xn3,
346
 
347
        TASK1,
348
        THREAD2,
349
 
350
        // 160
351
        TASK3,
352
        TASK4,
353
 
354
        LDT1,
355
        LDT2,
356
        LDT3,
357
        SDT1,
358
        SDT2,
359
 
360
        SUB,
361
        SUB1,
362
        MOVEP,
363
        MOVEP1,
364
        MOVEP2,
365
        MOVEP3,
366
        CHK,
367
 
368
        MOVERc2Rn,
369
        MOVERn2Rc,
370
        MOVERn2Rc2,
371
 
372
        MOVES,
373
        MOVES2,
374
        MOVES3,
375
 
376
        ADDX,
377
        ADDX2,
378
        ADDX3,
379
        SUBX,
380
        SUBX2,
381
        SUBX3,
382
 
383
        MULU1,
384
        MULU2,
385
        MULU3,
386
 
387
        MULS1,
388
        MULS2,
389
        MULS3,
390
 
391
        BIN2BCD1,
392
        BIN2BCD2,
393
        BCD2BIN1,
394
        BCD2BIN2,
395
        BCD2BIN3,
396
 
397
        IFETCH2,
398
 
399
        FSDATA2
400
} state_t;
401
 
402
typedef enum logic [4:0] {
403
        FU_NONE = 5'd0,
404
        FU_MUL,
405
        FU_TST, FU_ADDX, FU_SUBX,
406
        FU_CMP, FU_ADD, FU_SUB, FU_LOGIC, FU_ADDQ, FU_SUBQ,
407
        FU_ADDI, FU_ANDI_CCR, FU_ANDI_SR, FU_EORI_CCR,
408
        FU_ANDI_SRX, FU_EORI_SRX, FU_ORI_SRX, FU_MOVE2SRX,
409
        FU_EORI_SR, FU_ORI_CCR, FU_ORI_SR, FU_MOVE2CCR,
410
        FU_MOVE2SR
411
} flag_update_t;
412
 
413
parameter S = 1'b0;
414
parameter D = 1'b1;
415
 
416
input [31:0] coreno_i;
417
input clken_i;
418
input rst_i;
419
output reg rst_o;
420
input clk_i;
421
input nmi_i;
422
input vpa_i;
423
input [2:0] ipl_i;
424
output lock_o;
425
reg lock_o;
426
output cyc_o;
427
reg cyc_o;
428
output stb_o;
429
reg stb_o;
430
input ack_i;
431
input err_i;
432
input rty_i;
433
output we_o;
434
reg we_o;
435
output [3:0] sel_o;
436
reg [3:0] sel_o;
437
output [2:0] fc_o;
438
reg [2:0] fc_o;
439
output [7:0] asid_o;
440
output mmus_o;
441
output ios_o;
442
output iops_o;
443
output [31:0] adr_o;
444
reg [31:0] adr_o;
445
input [31:0] dat_i;
446
output [31:0] dat_o;
447
reg [31:0] dat_o;
448
 
449
reg em;                                                 // emulation mode
450
reg [15:0] ir;
451
reg [15:0] ir2;                 // second word for ir
452
reg ext_ir;
453
reg [31:0] icnt;
454
state_t state;
455
state_t rstate;
456
state_t state_stk1;
457
state_t state_stk2;
458
state_t state_stk3;
459
state_t state_stk4;
460
state_t sz_state;
461
flag_update_t flag_update;
462
reg [31:0] d0 = 'd0;
463
reg [31:0] d1 = 'd0;
464
reg [31:0] d2 = 'd0;
465
reg [31:0] d3 = 'd0;
466
reg [31:0] d4 = 'd0;
467
reg [31:0] d5 = 'd0;
468
reg [31:0] d6 = 'd0;
469
reg [31:0] d7 = 'd0;
470
reg [31:0] a0 = 'd0;
471
reg [31:0] a1 = 'd0;
472
reg [31:0] a2 = 'd0;
473
reg [31:0] a3 = 'd0;
474
reg [31:0] a4 = 'd0;
475
reg [31:0] a5 = 'd0;
476
reg [31:0] a6 = 'd0;
477
reg [31:0] sp = 'd0;
478 3 robfinch
reg [127:0] fp0 = 'd0;
479
reg [127:0] fp1 = 'd0;
480
reg [127:0] fp2 = 'd0;
481
reg [127:0] fp3 = 'd0;
482
reg [127:0] fp4 = 'd0;
483
reg [127:0] fp5 = 'd0;
484
reg [127:0] fp6 = 'd0;
485
reg [127:0] fp7 = 'd0;
486 2 robfinch
reg [31:0] d0i;
487
reg [31:0] d1i;
488
reg [31:0] d2i;
489
reg [31:0] d3i;
490
reg [31:0] d4i;
491
reg [31:0] d5i;
492
reg [31:0] d6i;
493
reg [31:0] d7i;
494
reg [31:0] a0i;
495
reg [31:0] a1i;
496
reg [31:0] a2i;
497
reg [31:0] a3i;
498
reg [31:0] a4i;
499
reg [31:0] a5i;
500
reg [31:0] a6i;
501
reg [31:0] spi;
502
reg [31:0] flagsi;
503
reg [31:0] pci;
504
wire [31:0] d0o;
505
wire [31:0] d1o;
506
wire [31:0] d2o;
507
wire [31:0] d3o;
508
wire [31:0] d4o;
509
wire [31:0] d5o;
510
wire [31:0] d6o;
511
wire [31:0] d7o;
512
wire [31:0] a0o;
513
wire [31:0] a1o;
514
wire [31:0] a2o;
515
wire [31:0] a3o;
516
wire [31:0] a4o;
517
wire [31:0] a5o;
518
wire [31:0] a6o;
519
wire [31:0] spo;
520
wire [31:0] flagso;
521
wire [31:0] pco;
522
reg cf,vf,nf,zf,xf,sf,tf;
523
reg [2:0] im;
524
reg [2:0] ccr57;
525
reg [1:0] sr1112;
526
reg sr14;
527
wire [15:0] sr = {tf,sr14,sf,sr1112,im,ccr57,xf,nf,zf,vf,cf};
528
wire [31:0] srx = {sr};
529
reg [31:0] isr;
530
reg [3:0] ifmt;
531
reg [31:0] pc;
532
reg [31:0] opc;                 // pc for branch references
533
reg [31:0] ssp,usp;
534
reg [31:0] disp;
535
reg [31:0] s,d,dd,imm,immx;
536
reg [31:0] bit2test;
537
reg wl;
538
reg ds;
539
reg [5:0] cnt;                          // shift count
540
reg [31:0] ea;                          // effective address
541
reg [31:0] vector;
542
reg [7:0] vecno;
543
reg [3:0] Rt;
544
wire [1:0] sz = ir[7:6];
545
reg dsix;
546
reg [2:0] mmm,mmmx,mmm_save='d0;
547
reg [2:0] rrr,rrrx;
548
reg [3:0] rrrr;
549
wire [2:0] MMM = ir[8:6];
550
wire [2:0] RRR = ir[11:9];
551
wire [2:0] QQQ = ir[11:9];
552
wire [2:0] DDD = ir[11:9];
553
wire [2:0] AAA = ir[11:9];
554
reg MMMRRR;
555
wire Anabit;
556
wire [31:0] sp_dec = sp - 32'd2;
557
reg [31:0] rfoAn;
558
always_comb
559
case(rrr)
560
3'd0: rfoAn <= a0;
561
3'd1: rfoAn <= a1;
562
3'd2: rfoAn <= a2;
563
3'd3: rfoAn <= a3;
564
3'd4: rfoAn <= a4;
565
3'd5: rfoAn <= a5;
566
3'd6: rfoAn <= a6;
567
3'd7: rfoAn <= sp;
568
endcase
569
reg [31:0] rfoAna;
570
always_comb
571
case(AAA)
572
3'd0: rfoAna <= a0;
573
3'd1: rfoAna <= a1;
574
3'd2: rfoAna <= a2;
575
3'd3: rfoAna <= a3;
576
3'd4: rfoAna <= a4;
577
3'd5: rfoAna <= a5;
578
3'd6: rfoAna <= a6;
579
3'd7: rfoAna <= sp;
580
endcase
581
//wire [31:0] rfoAn =   rrr==3'b111 ? sp : regfile[{1'b1,rrr}];
582
reg [31:0] rfoDn;
583
always_comb
584
case(DDD)
585
3'd0:   rfoDn <= d0;
586
3'd1:   rfoDn <= d1;
587
3'd2:   rfoDn <= d2;
588
3'd3:   rfoDn <= d3;
589
3'd4:   rfoDn <= d4;
590
3'd5:   rfoDn <= d5;
591
3'd6:   rfoDn <= d6;
592
3'd7:   rfoDn <= d7;
593
endcase
594
reg [31:0] rfoDnn;
595
always_comb
596
case(rrr)
597
3'd0:   rfoDnn <= d0;
598
3'd1:   rfoDnn <= d1;
599
3'd2:   rfoDnn <= d2;
600
3'd3:   rfoDnn <= d3;
601
3'd4:   rfoDnn <= d4;
602
3'd5:   rfoDnn <= d5;
603
3'd6:   rfoDnn <= d6;
604
3'd7:   rfoDnn <= d7;
605
endcase
606
reg [31:0] rfob;
607
always_comb
608
case({mmm[0],rrr})
609
4'd0:   rfob <= d0;
610
4'd1:   rfob <= d1;
611
4'd2:   rfob <= d2;
612
4'd3:   rfob <= d3;
613
4'd4:   rfob <= d4;
614
4'd5:   rfob <= d5;
615
4'd6:   rfob <= d6;
616
4'd7:   rfob <= d7;
617
4'd8:   rfob <= a0;
618
4'd9:   rfob <= a1;
619
4'd10:  rfob <= a2;
620
4'd11:  rfob <= a3;
621
4'd12:  rfob <= a4;
622
4'd13:  rfob <= a5;
623
4'd14:  rfob <= a6;
624
4'd15:  rfob <= sp;
625
endcase
626
reg [31:0] rfoRnn;
627
always_comb
628
case(rrrr)
629
4'd0:   rfoRnn <= d0;
630
4'd1:   rfoRnn <= d1;
631
4'd2:   rfoRnn <= d2;
632
4'd3:   rfoRnn <= d3;
633
4'd4:   rfoRnn <= d4;
634
4'd5:   rfoRnn <= d5;
635
4'd6:   rfoRnn <= d6;
636
4'd7:   rfoRnn <= d7;
637
4'd8:   rfoRnn <= a0;
638
4'd9:   rfoRnn <= a1;
639
4'd10:  rfoRnn <= a2;
640
4'd11:  rfoRnn <= a3;
641
4'd12:  rfoRnn <= a4;
642
4'd13:  rfoRnn <= a5;
643
4'd14:  rfoRnn <= a6;
644
4'd15:  rfoRnn <= sp;
645
endcase
646
//wire [31:0] rfoDn = regfile[{1'b0,DDD}];
647
//wire [31:0] rfoAna = AAA==3'b111 ? sp : regfile[{1'b1,AAA}];
648
//wire [31:0] rfob = {mmm[0],rrr}==4'b1111 ? sp : regfile[{mmm[0],rrr}];
649
//wire [31:0] rfoDnn = regfile[{1'b0,rrr}];
650
//wire [31:0] rfoRnn = rrrr==4'b1111 ? sp : regfile[rrrr];
651
wire clk_g;
652
reg rfwrL,rfwrB,rfwrW;
653 3 robfinch
reg rfwrFp;
654 2 robfinch
reg takb;
655
reg [8:0] resB;
656
reg [16:0] resW;
657
reg [32:0] resL;
658
(* USE_DSP = "no" *)
659
reg [32:0] resL1,resL2;
660
reg [32:0] resMS1,resMS2,resMU1,resMU2;
661
reg [31:0] st_data;
662
wire [11:0] bcdaddo,bcdsubo,bcdnego;
663
wire bcdaddoc,bcdsuboc,bcdnegoc;
664
reg [31:0] bad_addr;
665
reg [15:0] mac_cycle_type;
666
reg prev_nmi;
667
reg pe_nmi;
668
reg is_nmi;
669
reg is_irq, is_trace, is_priv, is_illegal;
670
reg is_adr_err;
671
reg is_rst;
672
reg is_bus_err;
673
reg use_dfc, use_sfc;
674
reg [4:0] rst_cnt;
675
reg [2:0] shift_op;
676
reg rtr;
677
reg bsr;
678
reg lea;
679
reg bcdsub, bcdneg;
680
reg [31:0] dati_buf;    // input data from bus error
681
reg [31:0] dato_buf;
682
 
683
// CSR's
684
reg [31:0] tick;        // FF0
685
reg [7:0] asid;         // 003
686
assign asid_o = asid;
687
reg [31:0] vbr;         // 801
688
reg [31:0] sfc;         // 000
689
reg [31:0] dfc;         // 001
690
reg [31:0] apc;
691
reg [7:0] cpl;
692
reg [31:0] tr;
693
reg [31:0] tcba;
694
reg [31:0] mmus, ios, iops;
695 3 robfinch
assign mmus_o = adr_o[31:20] == mmus[31:20];
696
assign iops_o = adr_o[31:16] == iops[31:16];
697
assign ios_o  = adr_o[31:20] == ios [31:20];
698 2 robfinch
 
699
wire [16:0] lfsr_o;
700
lfsr17 ulfsr1
701
(
702
        .rst(rst_i),
703
        .clk(clk_g),
704
        .ce(1'b1),
705
        .cyc(1'b0),
706
        .o(lfsr_o)
707
);
708
 
709
/*
710
reg [31:0] cache_tag [0:7];
711
reg [15:0] cache_dat [0:7];
712
 
713
task tPushCache;
714
input [31:0] adr;
715
input [15:0] dat;
716
integer n;
717
begin
718
        for (n = 1; n < 8; n = n + 1) begin
719
                cache_tag[n] <= cache_tag[n-1];
720
                cache_dat[n] <= cache_dat[n-1];
721
        end
722
        cache_tag[0] <= adr;
723
        cache_dat[0] <= dat;
724
end
725
endtask
726
 
727
function fnInCache;
728
input [31:0] adr;
729
integer n;
730
begin
731
        fnInCache = 1'b0;
732
        for (n = 0; n < 8; n = n + 1) begin
733
                if (cache_tag[n]==adr) begin
734
                        fnInCache = 1'b1;
735
        end
736
end
737
endfunction
738
 
739
task tFindInCache;
740
input [31:0] adr;
741
output [15:0] dat;
742
integer n;
743
begin
744
        dat = 16'h4E71; // NOP
745
        for (n = 0; n < 8; n = n + 1) begin
746
                if (cache_tag[n]==adr) begin
747
                        dat = cache_dat[n];
748
                end
749
        end
750
end
751
endtask
752
*/
753
 
754
function [31:0] rbo;
755
input [31:0] w;
756
rbo = {w[7:0],w[15:8],w[23:16],w[31:24]};
757
endfunction
758
 
759
wire [7:0] dbin, sbin;
760
reg [9:0] bcdres;
761
wire dd_done;
762
wire [11:0] bcdreso;
763
BCDToBin ub2b1 (clk_g, d, dbin);
764
BCDToBin ub2b2 (clk_g, s, sbin);
765
 
766
DDBinToBCD #(.WID(10)) udd1
767
(
768
        .rst(rst_i),
769
        .clk(clk_g),
770
        .ld(state==BCD3),
771
        .bin(bcdres),
772
        .bcd(bcdreso),
773
        .done(dd_done)
774
);
775
 
776
reg [31:0] dd32in;
777
wire [39:0] dd32out;
778
wire dd32done;
779
DDBinToBCD #(.WID(32)) udd2
780
(
781
        .rst(rst_i),
782
        .clk(clk_g),
783
        .ld(state==BIN2BCD1),
784
        .bin(dd32in),
785
        .bcd(dd32out),
786
        .done(dd32done)
787
);
788
 
789
/*
790
BCDAdd u1
791
(
792
        .ci(xf),
793
        .a(s[7:0]),
794
        .b(d[7:0]),
795
        .o(bcdaddo),
796
        .c(bcdaddoc)
797
);
798
 
799
 
800
BCDSub u2
801
(
802
        .ci(xf),
803
        .a(d[7:0]),
804
        .b(s[7:0]),
805
        .o(bcdsubo),
806
        .c(bcdsuboc)
807
);
808
 
809
BCDSub u3
810
(
811
        .ci(xf),
812
        .a(8'h00),
813
        .b(d[7:0]),
814
        .o(bcdnego),
815
        .c(bcdnegoc)
816
);
817
*/
818
// These functions take the MSBs of the operands and results and return an
819
// overflow status.
820
 
821
// If the signs of the operands are the same, and the sign of the result does
822
// not match the operands sign.
823
function fnAddOverflow;
824
input r;
825
input a;
826
input b;
827
        fnAddOverflow = (r ^ b) & (1'b1 ^ a ^ b);
828
endfunction
829
 
830
// If the signs of the operands are different and sign of the result does not
831
// match the first operand.
832
function fnSubOverflow;
833
input r;
834
input a;
835
input b;
836
        fnSubOverflow = (r ^ a) & (a ^ b);
837
endfunction
838
 
839
reg divs;
840
wire dvdone;
841
wire dvByZr;
842
wire dvovf;
843
wire [31:0] divq;
844
wire [31:0] divr;
845
 
846
rf68000_divider udiv1
847
(
848
        .rst(rst_i),
849
        .clk(clk_g),
850
        .ld(state==DIV1),
851
        .abort(1'b0),
852
        .sgn(divs),
853
        .sgnus(1'b0),
854
        .a(d),
855
        .b(divs? {{16{s[15]}},s[15:0]}:{16'd0,s[15:0]}),
856
        .qo(divq),
857
        .ro(divr),
858
        .dvByZr(dvByZr),
859
        .ovf(dvovf),
860
        .done(dvdone),
861
        .idle()
862
);
863
 
864
always_comb
865
case(ir[15:8])
866
`BRA:   takb = 1'b1;
867
`BSR:   takb = 1'b0;
868
`BHI:   takb = !cf & !zf;
869
`BLS:   takb = cf | zf;
870
`BHS:   takb = !cf;
871
`BLO:   takb =  cf;
872
`BNE:   takb = !zf;
873
`BEQ:   takb =  zf;
874
`BVC:   takb = !vf;
875
`BVS:   takb =  vf;
876
`BPL:   takb = !nf;
877
`BMI:   takb =  nf;
878
`BGE:   takb = (nf & vf)|(!nf & !vf);
879
`BLT:   takb = (nf & !vf)|(!nf & vf);
880
`BGT:   takb = (nf & vf & !zf)|(!nf & !vf & zf);
881
`BLE:   takb = zf | (nf & !vf) | (!nf & vf);
882
`DBRA:  takb = 1'b1;
883
`DBSR:  takb = 1'b0;
884
`DBHI:  takb = !cf & !zf;
885
`DBLS:  takb = cf | zf;
886
`DBHS:  takb = !cf;
887
`DBLO:  takb =  cf;
888
`DBNE:  takb = !zf;
889
`DBEQ:  takb =  zf;
890
`DBVC:  takb = !vf;
891
`DBVS:  takb =  vf;
892
`DBPL:  takb = !nf;
893
`DBMI:  takb =  nf;
894
`DBGE:  takb = ((nf & vf)|(!nf & !vf));
895
`DBLT:  takb = ((nf & !vf)|(!nf & vf));
896
`DBGT:  takb = ((nf & vf & !zf)|(!nf & !vf & zf));
897
`DBLE:  takb = (zf | (nf & !vf) | (!nf & vf));
898
default:        takb = 1'b1;
899
endcase
900
 
901
`ifdef BIG_ENDIAN
902
wire [15:0] iri = pc[1] ? {dat_i[23:16],dat_i[31:24]} : {dat_i[7:0],dat_i[15:8]};
903
`else
904
wire [15:0] iri = pc[1] ? dat_i[31:16] : dat_i[15:0];
905
`endif
906
 
907
assign clk_g = clk_i;
908
 
909
always_ff @(posedge clk_g)
910
if (rst_i) begin
911
        em <= 1'b0;
912
        lock_o <= 1'b0;
913
        cyc_o <= 1'b0;
914
        stb_o <= 1'b0;
915
        we_o <= 1'b0;
916
        sel_o <= 4'b0000;
917
        fc_o <= 3'b000;
918
        adr_o <= 32'd0;
919
        dat_o <= 32'd0;
920
        rfwrB <= 1'b0;
921
        rfwrW <= 1'b0;
922
        rfwrL <= 1'b0;
923
        zf <= 1'b0;
924
        nf <= 1'b0;
925
        cf <= 1'b0;
926
        vf <= 1'b0;
927
        xf <= 1'b0;
928
        im <= 3'b111;
929
        sf <= 1'b1;
930
        tf <= 1'b0;
931
        goto (RESET);
932
        rstate <= RESET;
933
        prev_nmi <= 1'b0;
934
        pe_nmi <= 1'b0;
935
  tick <= 32'd0;
936
  rst_cnt <= 5'd10;
937
  rst_o <= 1'b1;
938
  is_rst <= 1'b1;
939
        MMMRRR <= 1'b0;
940
        rtr <= 1'b0;
941
        bsr <= 1'b0;
942
        lea <= 1'b0;
943
        divs <= 1'b0;
944
        bcdsub <= 1'b0;
945
        bcdneg <= 1'b0;
946
        icnt <= 'd0;
947
        is_bus_err <= 1'b0;
948
        is_adr_err <= 1'b0;
949
        is_trace <= 1'b0;
950
        is_priv <= 1'b0;
951
        is_illegal <= 1'b0;
952
        vbr <= 'd0;
953
        sfc <= 'd0;
954
        dfc <= 'd0;
955
        dati_buf <= 'd0;
956
        dato_buf <= 'd0;
957
        use_sfc <= 'd0;
958
        use_dfc <= 'd0;
959
        ext_ir <= 1'b0;
960
        ios  <= 32'hFD000000;
961
        iops <= 32'hFD100000;
962
        mmus <= 32'hFDC00000;
963
end
964
else begin
965
 
966
if (rst_cnt != 5'd0)
967
    rst_cnt <= rst_cnt - 5'd1;
968
else
969
    rst_o <= 1'b0;
970
 
971
tick <= tick + 32'd1;
972
prev_nmi <= nmi_i;
973
if (nmi_i & !prev_nmi)
974
        pe_nmi <= 1'b1;
975
 
976
// Register file update
977
rfwrB <= 1'b0;
978
rfwrW <= 1'b0;
979
rfwrL <= 1'b0;
980
if (rfwrL) begin
981
  case(Rt)
982
  4'd0:   d0 <= resL[31:0];
983
  4'd1:   d1 <= resL[31:0];
984
  4'd2:   d2 <= resL[31:0];
985
  4'd3:   d3 <= resL[31:0];
986
  4'd4:   d4 <= resL[31:0];
987
  4'd5:   d5 <= resL[31:0];
988
  4'd6:   d6 <= resL[31:0];
989
  4'd7:   d7 <= resL[31:0];
990
  4'd8:   a0 <= resL[31:0];
991
  4'd9:   a1 <= resL[31:0];
992
  4'd10:  a2 <= resL[31:0];
993
  4'd11:  a3 <= resL[31:0];
994
  4'd12:  a4 <= resL[31:0];
995
  4'd13:  a5 <= resL[31:0];
996
  4'd14:  a6 <= resL[31:0];
997
  4'd15:  sp <= resL[31:0];
998
  endcase
999
end
1000
else if (rfwrW) begin
1001
  case(Rt)
1002
  4'd0:   d0[15:0] <= resW[15:0];
1003
  4'd1:   d1[15:0] <= resW[15:0];
1004
  4'd2:   d2[15:0] <= resW[15:0];
1005
  4'd3:   d3[15:0] <= resW[15:0];
1006
  4'd4:   d4[15:0] <= resW[15:0];
1007
  4'd5:   d5[15:0] <= resW[15:0];
1008
  4'd6:   d6[15:0] <= resW[15:0];
1009
  4'd7:   d7[15:0] <= resW[15:0];
1010
  4'd8:   a0 <= {{16{resW[15]}},resW[15:0]};
1011
  4'd9:   a1 <= {{16{resW[15]}},resW[15:0]};
1012
  4'd10:  a2 <= {{16{resW[15]}},resW[15:0]};
1013
  4'd11:  a3 <= {{16{resW[15]}},resW[15:0]};
1014
  4'd12:  a4 <= {{16{resW[15]}},resW[15:0]};
1015
  4'd13:  a5 <= {{16{resW[15]}},resW[15:0]};
1016
  4'd14:  a6 <= {{16{resW[15]}},resW[15:0]};
1017
  4'd15:  sp <= {{16{resW[15]}},resW[15:0]};
1018
  endcase
1019
end
1020
else if (rfwrB)
1021
  case(Rt)
1022
  4'd0:   d0[7:0] <= resB[7:0];
1023
  4'd1:   d1[7:0] <= resB[7:0];
1024
  4'd2:   d2[7:0] <= resB[7:0];
1025
  4'd3:   d3[7:0] <= resB[7:0];
1026
  4'd4:   d4[7:0] <= resB[7:0];
1027
  4'd5:   d5[7:0] <= resB[7:0];
1028
  4'd6:   d6[7:0] <= resB[7:0];
1029
  4'd7:   d7[7:0] <= resB[7:0];
1030
  default:    ;
1031
  endcase
1032
 
1033
case(state)
1034
 
1035
IFETCH:
1036
        begin
1037
                case(flag_update)
1038
                FU_MUL:
1039
                        begin
1040
                                cf <= 1'b0;
1041
                                vf <= 1'b0;
1042
                                nf <= resL[31];
1043
                                zf <= resL[31:0]==32'd0;
1044
                        end
1045
                FU_TST:
1046
                        begin
1047
                                cf <= 1'b0;
1048
                                vf <= 1'b0;
1049
                                case(sz)
1050
                                2'b00:  begin zf <= d[7:0]==8'h00; nf <= d[7]; end
1051
                                2'b01:  begin zf <= d[15:0]==16'h00; nf <= d[15]; end
1052
                                2'b10:  begin zf <= d[31:0]==32'h00; nf <= d[31]; end
1053
                                default:        ;
1054
                                endcase
1055
                        end
1056
                FU_CMP:
1057
                        begin
1058
                                case(sz)
1059
                                2'b00:  begin zf <= resB[ 7:0]== 8'd0; nf <= resB[ 7]; cf <= resB[ 8]; vf <= fnSubOverflow(resB[ 7],d[ 7],s[ 7]); end
1060
                                2'b01:  begin zf <= resW[15:0]==16'd0; nf <= resW[15]; cf <= resW[16]; vf <= fnSubOverflow(resW[15],d[15],s[15]); end
1061
                                2'b10:  begin zf <= resL[31:0]==32'd0; nf <= resL[31]; cf <= resL[32]; vf <= fnSubOverflow(resL[31],d[31],s[31]); end
1062
                                2'b11:  begin zf <= resL[31:0]==32'd0; nf <= resL[31]; cf <= resL[32]; vf <= fnSubOverflow(resL[31],d[31],s[31]); end   // CMPA
1063
                                endcase
1064
                        end
1065
                FU_ADD:
1066
                        begin
1067
                                case(sz)
1068
                                2'b00:
1069
                                        begin
1070
                                                cf <= resB[8];
1071
                                                nf <= resB[7];
1072
                                                zf <= resB[7:0]==8'h00;
1073
                                                vf <= fnAddOverflow(resB[7],dd[7],s[7]);
1074
                                                xf <= resB[8];
1075
                                        end
1076
                                2'b01:
1077
                                        begin
1078
                                                cf <= resW[16];
1079
                                                nf <= resW[15];
1080
                                                zf <= resW[15:0]==16'h0000;
1081
                                                vf <= fnAddOverflow(resW[15],dd[15],s[15]);
1082
                                                xf <= resW[16];
1083
                                        end
1084
                                2'b10:
1085
                                        begin
1086
                                                cf <= resL[32];
1087
                                                nf <= resL[31];
1088
                                                zf <= resL[31:0]==32'h00000000;
1089
                                                vf <= fnAddOverflow(resL[31],dd[31],s[31]);
1090
                                                xf <= resL[32];
1091
                                        end
1092
                                default:        ;
1093
                                endcase
1094
                        end
1095
                FU_ADDX:
1096
                        begin
1097
                                case(sz)
1098
                                2'b00:
1099
                                        begin
1100
                                                cf <= resB[8];
1101
                                                nf <= resB[7];
1102
                                                if (resB[7:0]!=8'h00)
1103
                                                        zf <= 1'b0;
1104
                                                vf <= fnAddOverflow(resB[7],dd[7],s[7]);
1105
                                                xf <= resB[8];
1106
                                        end
1107
                                2'b01:
1108
                                        begin
1109
                                                cf <= resW[16];
1110
                                                nf <= resW[15];
1111
                                                if (resW[15:0]!=16'h00)
1112
                                                        zf <= 1'b0;
1113
                                                vf <= fnAddOverflow(resW[15],dd[15],s[15]);
1114
                                                xf <= resW[16];
1115
                                        end
1116
                                2'b10:
1117
                                        begin
1118
                                                cf <= resL[32];
1119
                                                nf <= resL[31];
1120
                                                if (resL[31:0]!=32'h00)
1121
                                                        zf <= 1'b0;
1122
                                                vf <= fnAddOverflow(resL[31],dd[31],s[31]);
1123
                                                xf <= resL[32];
1124
                                        end
1125
                                default:        ;
1126
                                endcase
1127
                        end
1128
                FU_SUBX:
1129
                        begin
1130
                                case(sz)
1131
                                2'b00:
1132
                                        begin
1133
                                                cf <= resB[8];
1134
                                                nf <= resB[7];
1135
                                                if (resB[7:0]!=8'h00)
1136
                                                        zf <= 1'b0;
1137
                                                vf <= fnSubOverflow(resB[7],dd[7],s[7]);
1138
                                                xf <= resB[8];
1139
                                        end
1140
                                2'b01:
1141
                                        begin
1142
                                                cf <= resW[16];
1143
                                                nf <= resW[15];
1144
                                                if (resW[15:0]!=16'h00)
1145
                                                        zf <= 1'b0;
1146
                                                vf <= fnSubOverflow(resW[15],dd[15],s[15]);
1147
                                                xf <= resW[16];
1148
                                        end
1149
                                2'b10:
1150
                                        begin
1151
                                                cf <= resL[32];
1152
                                                nf <= resL[31];
1153
                                                if (resL[31:0]!=32'h00)
1154
                                                        zf <= 1'b0;
1155
                                                vf <= fnSubOverflow(resL[31],dd[31],s[31]);
1156
                                                xf <= resL[32];
1157
                                        end
1158
                                default:        ;
1159
                                endcase
1160
                        end
1161
                FU_SUB:
1162
                        begin
1163
                                case(sz)
1164
                                2'b00:
1165
                                        begin
1166
                                                cf <= resB[8];
1167
                                                nf <= resB[7];
1168
                                                zf <= resB[7:0]==8'h00;
1169
                                                vf <= fnSubOverflow(resB[7],dd[7],s[7]);
1170
                                                xf <= resB[8];
1171
                                        end
1172
                                2'b01:
1173
                                        begin
1174
                                                cf <= resW[16];
1175
                                                nf <= resW[15];
1176
                                                zf <= resW[15:0]==16'h0000;
1177
                                                vf <= fnSubOverflow(resW[15],dd[15],s[15]);
1178
                                                xf <= resW[16];
1179
                                        end
1180
                                2'b10:
1181
                                        begin
1182
                                                cf <= resL[32];
1183
                                                nf <= resL[31];
1184
                                                zf <= resL[31:0]==32'h00000000;
1185
                                                vf <= fnSubOverflow(resL[31],dd[31],s[31]);
1186
                                                xf <= resL[32];
1187
                                        end
1188
                                default:        ;
1189
                                endcase
1190
                        end
1191
                FU_LOGIC:
1192
                        begin
1193
                                cf <= 1'b0;
1194
                                vf <= 1'b0;
1195
                                case(sz)
1196
                                2'b00:
1197
                                        begin
1198
                                                nf <= resB[7];
1199
                                                zf <= resB[7:0]==8'h00;
1200
                                        end
1201
                                2'b01:
1202
                                        begin
1203
                                                nf <= resW[15];
1204
                                                zf <= resW[15:0]==16'h0000;
1205
                                        end
1206
                                2'b10:
1207
                                        begin
1208
                                                nf <= resL[31];
1209
                                                zf <= resL[31:0]==32'h00000000;
1210
                                        end
1211
                                default:        ;
1212
                                endcase
1213
                        end
1214
                FU_ADDQ:
1215
                        begin
1216
                                case(sz)
1217
                                2'b00:
1218
                                        begin
1219
                                                 xf <= resB[8];
1220
                                                 cf <= resB[8];
1221
                                                 vf <= resB[8]!=resB[7];
1222
                                                vf <= fnAddOverflow(resB[7],dd[7],s[7]);
1223
                                                 //zf <= resB[7:0]==8'd0;
1224
                                                 nf <= resB[7];
1225
                                        end
1226
                                2'b01:
1227
                                        begin
1228
                                                 xf <= resW[16];
1229
                                                 cf <= resW[16];
1230
                                                vf <= fnAddOverflow(resW[15],dd[15],s[15]);
1231
                                                 //vf <= resW[16]!=resW[15];
1232
                                                 zf <= resW[15:0]==16'd0;
1233
                                                 nf <= resW[15];
1234
                                        end
1235
                                2'b10:
1236
                                        begin
1237
                                                 xf <= resL[32];
1238
                                                 cf <= resL[32];
1239
                                                vf <= fnAddOverflow(resL[31],dd[31],s[31]);
1240
                                                // vf <= resL[32]!=resL[31];
1241
                                                 zf <= resL[31:0]==32'd0;
1242
                                                 nf <= resL[31];
1243
                                        end
1244
                                endcase
1245
                        end
1246
                FU_SUBQ:
1247
                        begin
1248
                                case(sz)
1249
                                2'b00:
1250
                                        begin
1251
                                                 xf <= resB[8];
1252
                                                 cf <= resB[8];
1253
                                                 vf <= resB[8]!=resB[7];
1254
                                                vf <= fnSubOverflow(resB[7],dd[7],s[7]);
1255
                                                 //zf <= resB[7:0]==8'd0;
1256
                                                 nf <= resB[7];
1257
                                        end
1258
                                2'b01:
1259
                                        begin
1260
                                                 xf <= resW[16];
1261
                                                 cf <= resW[16];
1262
                                                vf <= fnSubOverflow(resW[15],dd[15],s[15]);
1263
                                                 //vf <= resW[16]!=resW[15];
1264
                                                 zf <= resW[15:0]==16'd0;
1265
                                                 nf <= resW[15];
1266
                                        end
1267
                                2'b10:
1268
                                        begin
1269
                                                 xf <= resL[32];
1270
                                                 cf <= resL[32];
1271
                                                vf <= fnSubOverflow(resL[31],dd[31],s[31]);
1272
                                                // vf <= resL[32]!=resL[31];
1273
                                                 zf <= resL[31:0]==32'd0;
1274
                                                 nf <= resL[31];
1275
                                        end
1276
                                endcase
1277
                        end
1278
                FU_ADDI:
1279
                        begin
1280
                                case(ir[11:8])
1281
                                4'h0,4'h2,4'hA:
1282
                                                begin   // ORI,ANDI,EORI
1283
                                                        cf <= 1'b0;
1284
                                                        vf <= 1'b0;
1285
                                                        case(sz)
1286
                                                        2'b00:  zf <= resB[7:0]==8'h00;
1287
                                                        2'b01:  zf <= resW[15:0]==16'h00;
1288
                                                        2'b10:  zf <= resL[31:0]==32'd0;
1289
                                                        endcase
1290
                                                        case(sz)
1291
                                                        2'b00:  nf <= resB[7];
1292
                                                        2'b01:  nf <= resW[15];
1293
                                                        2'b10:  nf <= resL[31];
1294
                                                        endcase
1295
                                                end
1296
                                4'h4:   // SUBI
1297
                                        begin
1298
                                                case(sz)
1299
                                                2'b00:
1300
                                                        begin
1301
                                                                xf <= resB[8];
1302
                                                                cf <= resB[8];
1303
                                                                vf <= fnSubOverflow(resB[7],dd[7],immx[7]);
1304
                                                                //vf <= resB[8]!=resB[7];
1305
                                                                zf <= resB[7:0]==8'd0;
1306
                                                                nf <= resB[7];
1307
                                                        end
1308
                                                2'b01:
1309
                                                        begin
1310
                                                                xf <= resW[16];
1311
                                                                cf <= resW[16];
1312
                                                                vf <= fnSubOverflow(resW[15],dd[15],immx[15]);
1313
                                                                //vf <= resW[16]!=resW[15];
1314
                                                                zf <= resW[15:0]==16'd0;
1315
                                                                nf <= resW[15];
1316
                                                        end
1317
                                                2'b10:
1318
                                                        begin
1319
                                                                xf <= resL[32];
1320
                                                                cf <= resL[32];
1321
                                                                vf <= fnSubOverflow(resL[31],dd[31],immx[31]);
1322
                                                                //vf <= resL[32]!=resL[31];
1323
                                                                zf <= resL[31:0]==32'd0;
1324
                                                                nf <= resL[31];
1325
                                                        end
1326
                                                endcase
1327
                                        end
1328
                                4'h6:   // ADDI
1329
                                        begin
1330
                                                case(sz)
1331
                                                2'b00:
1332
                                                        begin
1333
                                                                xf <= resB[8];
1334
                                                                cf <= resB[8];
1335
                                                                vf <= fnAddOverflow(resB[7],dd[7],immx[7]);
1336
                                                                //vf <= resB[8]!=resB[7];
1337
                                                                zf <= resB[7:0]==8'd0;
1338
                                                                nf <= resB[7];
1339
                                                        end
1340
                                                2'b01:
1341
                                                        begin
1342
                                                                xf <= resW[16];
1343
                                                                cf <= resW[16];
1344
                                                                vf <= fnAddOverflow(resW[15],dd[15],immx[15]);
1345
                                                                //vf <= resW[16]!=resW[15];
1346
                                                                zf <= resW[15:0]==16'd0;
1347
                                                                nf <= resW[15];
1348
                                                        end
1349
                                                2'b10:
1350
                                                        begin
1351
                                                                xf <= resL[32];
1352
                                                                cf <= resL[32];
1353
                                                                vf <= fnAddOverflow(resL[31],dd[31],immx[31]);
1354
                                                                //vf <= resL[32]!=resL[31];
1355
                                                                zf <= resL[31:0]==32'd0;
1356
                                                                nf <= resL[31];
1357
                                                        end
1358
                                                endcase
1359
                                        end
1360
                                4'hC:   // CMPI
1361
                                        begin
1362
                                                case(sz)
1363
                                                2'b00:
1364
                                                        begin
1365
                                                                cf <= resB[8];
1366
                                                                vf <= fnSubOverflow(resB[7],dd[7],immx[7]);
1367
                                                                zf <= resB[7:0]==8'd0;
1368
                                                                nf <= resB[7];
1369
                                                        end
1370
                                                2'b01:
1371
                                                        begin
1372
                                                                cf <= resW[16];
1373
                                                                vf <= fnSubOverflow(resW[15],dd[15],immx[15]);
1374
                                                                //vf <= resW[16]!=resW[15];
1375
                                                                zf <= resW[15:0]==16'd0;
1376
                                                                nf <= resW[15];
1377
                                                        end
1378
                                                2'b10:
1379
                                                        begin
1380
                                                                cf <= resL[32];
1381
                                                                vf <= fnSubOverflow(resL[31],dd[31],immx[31]);
1382
                                                                //vf <= resL[32]!=resL[31];
1383
                                                                zf <= resL[31:0]==32'd0;
1384
                                                                nf <= resL[31];
1385
                                                        end
1386
                                                endcase
1387
                                        end
1388
                                endcase
1389
                        end
1390
                FU_ANDI_CCR:
1391
                        begin
1392
                                cf <= cf & imm[0];
1393
                                vf <= vf & imm[1];
1394
                                zf <= zf & imm[2];
1395
                                nf <= nf & imm[3];
1396
                                xf <= xf & imm[4];
1397
                        end
1398
                FU_ANDI_SR:
1399
                        begin
1400
                                cf <= cf & imm[0];
1401
                                vf <= vf & imm[1];
1402
                                zf <= zf & imm[2];
1403
                                nf <= nf & imm[3];
1404
                                xf <= xf & imm[4];
1405
                                im[0] <= im[0] & imm[8];
1406
                                im[1] <= im[1] & imm[9];
1407
                                im[2] <= im[2] & imm[10];
1408
                                sf <= sf & imm[13];
1409
                                tf <= tf & imm[15];
1410
                        end
1411
                FU_ANDI_SRX:
1412
                        begin
1413
                                cf <= cf & imm[0];
1414
                                vf <= vf & imm[1];
1415
                                zf <= zf & imm[2];
1416
                                nf <= nf & imm[3];
1417
                                xf <= xf & imm[4];
1418
                                im[0] <= im[0] & imm[8];
1419
                                im[1] <= im[1] & imm[9];
1420
                                im[2] <= im[2] & imm[10];
1421
                                sf <= sf & imm[13];
1422
                                tf <= tf & imm[15];
1423
                        end
1424
                FU_EORI_CCR:
1425
                        begin
1426
                                cf <= cf ^ imm[0];
1427
                                vf <= vf ^ imm[1];
1428
                                zf <= zf ^ imm[2];
1429
                                nf <= nf ^ imm[3];
1430
                                xf <= xf ^ imm[4];
1431
                        end
1432
                FU_EORI_SR:
1433
                        begin
1434
                                cf <= cf ^ imm[0];
1435
                                vf <= vf ^ imm[1];
1436
                                zf <= zf ^ imm[2];
1437
                                nf <= nf ^ imm[3];
1438
                                xf <= xf ^ imm[4];
1439
                                im[0] <= im[0] ^ imm[8];
1440
                                im[1] <= im[1] ^ imm[9];
1441
                                im[2] <= im[2] ^ imm[10];
1442
                                sf <= sf ^ imm[13];
1443
                                tf <= tf ^ imm[15];
1444
                        end
1445
                FU_EORI_SRX:
1446
                        begin
1447
                                cf <= cf ^ imm[0];
1448
                                vf <= vf ^ imm[1];
1449
                                zf <= zf ^ imm[2];
1450
                                nf <= nf ^ imm[3];
1451
                                xf <= xf ^ imm[4];
1452
                                im[0] <= im[0] ^ imm[8];
1453
                                im[1] <= im[1] ^ imm[9];
1454
                                im[2] <= im[2] ^ imm[10];
1455
                                sf <= sf ^ imm[13];
1456
                                tf <= tf ^ imm[15];
1457
                        end
1458
                FU_ORI_CCR:
1459
                        begin
1460
                                cf <= cf | imm[0];
1461
                                vf <= vf | imm[1];
1462
                                zf <= zf | imm[2];
1463
                                nf <= nf | imm[3];
1464
                                xf <= xf | imm[4];
1465
                        end
1466
                FU_ORI_SR:
1467
                        begin
1468
                                cf <= cf | imm[0];
1469
                                vf <= vf | imm[1];
1470
                                zf <= zf | imm[2];
1471
                                nf <= nf | imm[3];
1472
                                xf <= xf | imm[4];
1473
                                im[0] <= im[0] | imm[8];
1474
                                im[1] <= im[1] | imm[9];
1475
                                im[2] <= im[2] | imm[10];
1476
                                sf <= sf | imm[13];
1477
                                tf <= tf | imm[15];
1478
                        end
1479
                FU_ORI_SRX:
1480
                        begin
1481
                                cf <= cf | imm[0];
1482
                                vf <= vf | imm[1];
1483
                                zf <= zf | imm[2];
1484
                                nf <= nf | imm[3];
1485
                                xf <= xf | imm[4];
1486
                                im[0] <= im[0] | imm[8];
1487
                                im[1] <= im[1] | imm[9];
1488
                                im[2] <= im[2] | imm[10];
1489
                                sf <= sf | imm[13];
1490
                                tf <= tf | imm[15];
1491
                        end
1492
                FU_MOVE2CCR:
1493
                        begin
1494
                                cf <= s[0];
1495
                                vf <= s[1];
1496
                                zf <= s[2];
1497
                                nf <= s[3];
1498
                                xf <= s[4];
1499
                                ccr57 <= s[7:5];
1500
                        end
1501
                FU_MOVE2SR:
1502
                        begin
1503
                                cf <= s[0];
1504
                                vf <= s[1];
1505
                                zf <= s[2];
1506
                                nf <= s[3];
1507
                                xf <= s[4];
1508
                                ccr57 <= s[7:5];
1509
                                im[0] <= s[8];
1510
                                im[1] <= s[9];
1511
                                im[2] <= s[10];
1512
                                sr1112 <= s[12:11];
1513
                                sf <= s[13];
1514
                                sr14 <= s[14];
1515
                                tf <= s[15];
1516
                        end
1517
                FU_MOVE2SRX:
1518
                        begin
1519
                                cf <= s[0];
1520
                                vf <= s[1];
1521
                                zf <= s[2];
1522
                                nf <= s[3];
1523
                                xf <= s[4];
1524
                                ccr57 <= s[7:5];
1525
                                im[0] <= s[8];
1526
                                im[1] <= s[9];
1527
                                im[2] <= s[10];
1528
                                sr1112 <= s[12:11];
1529
                                sf <= s[13];
1530
                                sr14 <= s[14];
1531
                                tf <= s[15];
1532
                        end
1533
                default:        ;
1534
                endcase
1535
                flag_update <= FU_NONE;
1536
                MMMRRR <= 1'b0;
1537
                rtr <= 1'b0;
1538
                bsr <= 1'b0;
1539
                lea <= 1'b0;
1540
                bcdsub <= 1'b0;
1541
                bcdneg <= 1'b0;
1542
                is_illegal <= 1'b0;
1543
                use_sfc <= 1'b0;
1544
                use_dfc <= 1'b0;
1545
                if (!cyc_o) begin
1546
                        is_nmi <= 1'b0;
1547
                        is_irq <= 1'b0;
1548
                        /*
1549
                        if (pe_nmi) begin
1550
                                pe_nmi <= 1'b0;
1551
                                is_nmi <= 1'b1;
1552
                                goto(TRAP);
1553
                        end
1554
                        else
1555
                        */
1556
                        if (ipl_i > im) begin
1557
                                is_irq <= 1'b1;
1558
                                gosub(TRAP);
1559
                        end
1560
                        else if (pc[0]) begin
1561
                                is_adr_err <= 1'b1;
1562
                                gosub(TRAP);
1563
                        end
1564
                        else begin
1565
                                fc_o <= {sf,2'b10};
1566
                                cyc_o <= 1'b1;
1567
                                stb_o <= 1'b1;
1568
                                sel_o <= 4'b1111;
1569
                                adr_o <= pc;
1570 3 robfinch
                                goto (IFETCH);
1571 2 robfinch
                        end
1572
                end
1573
                else if (ack_i) begin
1574
                        cyc_o <= 1'b0;
1575
                        stb_o <= 1'b0;
1576
                        sel_o <= 2'b00;
1577
                        ir <= iri;
1578
                        mmm <= iri[5:3];
1579
                        rrr <= iri[2:0];
1580
                        rrrr <= iri[3:0];
1581
                        gosub (DECODE);
1582
                end
1583
        end
1584
IFETCH2:
1585
        if (!cyc_o) begin
1586
                fc_o <= {sf,2'b10};
1587
                cyc_o <= 1'b1;
1588
                stb_o <= 1'b1;
1589
                sel_o <= 4'b1111;
1590
                adr_o <= pc;
1591 3 robfinch
                goto (IFETCH2);
1592 2 robfinch
        end
1593
        else if (ack_i) begin
1594
                cyc_o <= 1'b0;
1595
                stb_o <= 1'b0;
1596
                sel_o <= 2'b00;
1597
                ext_ir <= 1'b1;
1598
                ir2 <= iri;
1599
                goto (DECODE);
1600
        end
1601
 
1602
//-----------------------------------------------------------------------------
1603
//-----------------------------------------------------------------------------
1604
DECODE:
1605
        begin
1606
                pc <= pc + 4'd2;
1607
                opc <= pc + 4'd2;
1608
                icnt <= icnt + 2'd1;
1609
        case({ext_ir,ir[15:12]})
1610
        5'h0:
1611
                case(ir[11:8])
1612
                4'h0:
1613
                        case(ir[7:0])
1614
                        8'h3C:  state <= ORI_CCR;
1615
                        8'h7C:
1616
                                if (sf)
1617
                                        goto (ORI_SR);
1618
                                else
1619
                                        tPrivilegeViolation();
1620
                        8'hBC:
1621
                                if (sf)
1622
                                        goto (ORI_SRX);
1623
                                else
1624
                                        tPrivilegeViolation();
1625
                        default:        state <= ADDI;  // ORI
1626
                        endcase
1627
                4'h2:
1628
                        case(ir[7:0])
1629
                        8'h3C:  state <= ANDI_CCR;
1630
                        8'h7C:
1631
                                if (sf)
1632
                                        goto (ANDI_SR);
1633
                                else
1634
                                        tPrivilegeViolation();
1635
                        8'hBC:
1636
                                if (sf)
1637
                                        goto (ANDI_SRX);
1638
                                else
1639
                                        tPrivilegeViolation();
1640
                        default:        state <= ADDI;  // ANDI
1641
                        endcase
1642
                4'h4:   state <= ADDI;  // SUBI
1643
                4'h6:   state <= ADDI;  // ADDI
1644
                4'hA:
1645
                        case(ir[7:0])
1646
                        8'h3C:  state <= EORI_CCR;
1647
                        8'h7C:
1648
                                if (sf)
1649
                                        goto (EORI_SR);
1650
                                else
1651
                                        tPrivilegeViolation();
1652
                        8'hBC:
1653
                                if (sf)
1654
                                        goto (EORI_SRX);
1655
                                else
1656
                                        tPrivilegeViolation();
1657
                        default:        state <= ADDI;  // EORI
1658
                        endcase
1659
                4'hC:   state <= ADDI;  // CMPI
1660
`ifdef SUPPORT_010
1661
                4'hE:   // MOVES
1662
                        begin
1663
                                call(FETCH_IMM16,MOVES);
1664
                        end
1665
`endif
1666
                default:
1667
                        if (mmm==3'b001 && ir[8]) begin
1668
                                push(MOVEP);
1669
                                fs_data(3'b101,rrr,FETCH_NOP_WORD,S);
1670
                        end
1671
                        else
1672
                                goto (BIT);
1673
                endcase
1674
//-----------------------------------------------------------------------------
1675
// MOVE.B
1676
//-----------------------------------------------------------------------------
1677
        5'h1:
1678
                begin
1679
                        push(STORE_IN_DEST);
1680
                        fs_data(mmm,rrr,FETCH_BYTE,S);
1681
                end
1682
//-----------------------------------------------------------------------------
1683
// MOVE.L
1684
//-----------------------------------------------------------------------------
1685
  5'h2:
1686
        begin
1687
                        push(STORE_IN_DEST);
1688
        fs_data(mmm,rrr,FETCH_LWORD,S);
1689
    end
1690
//-----------------------------------------------------------------------------
1691
// MOVE.W
1692
//-----------------------------------------------------------------------------
1693
        5'h3:
1694
                begin
1695
                        push(STORE_IN_DEST);
1696
                        fs_data(mmm,rrr,FETCH_WORD,S);
1697
                end
1698
//-----------------------------------------------------------------------------
1699
//-----------------------------------------------------------------------------
1700
        5'h4:
1701
                casez(ir[11:3])
1702
                9'b0000?????:
1703
                        case(sz)
1704
                        2'b00:  begin push(NEGX); fs_data(mmm,rrr,FETCH_BYTE,D); end
1705
                        2'b01:  begin push(NEGX); fs_data(mmm,rrr,FETCH_WORD,D); end
1706
                        2'b10:  begin push(NEGX); fs_data(mmm,rrr,FETCH_LWORD,D); end
1707
                        2'b11:  // MOVE sr,
1708
                                if (sf) begin
1709
                                        d <= sr;
1710
                                        resW <= sr;
1711
                                        fs_data(mmm,rrr,STORE_WORD,S);
1712
                                end
1713
                                else
1714
                                        tPrivilegeViolation();
1715
                        endcase
1716
                9'b000110???:   // MOVE.L srx,
1717
                                if (sf) begin
1718
                                        d <= srx;
1719
                                        resL <= srx;
1720
                                        fs_data(mmm,rrr,STORE_LWORD,S);
1721
                                end
1722
                                else
1723
                                        tPrivilegeViolation();
1724
                9'b0010?????:
1725
                        begin           // 42xx CLR
1726
                                cf <= 1'b0;
1727
                                vf <= 1'b0;
1728
                                zf <= 1'b1;
1729
                                nf <= 1'b0;
1730
                                d <= 'd0;
1731
                                case(sz)
1732
                                2'b00:  fs_data(mmm,rrr,STORE_BYTE,D);
1733
                                2'b01:  fs_data(mmm,rrr,STORE_WORD,D);
1734
                                2'b10:  fs_data(mmm,rrr,STORE_LWORD,D);
1735
                                default:        tIllegal();
1736
                                endcase
1737
                        end
1738
                9'b0100?????:
1739
                        casez(sz)
1740
                        2'b00:  begin push(NEG); fs_data(mmm,rrr,FETCH_BYTE,D); end
1741
                        2'b01:  begin push(NEG); fs_data(mmm,rrr,FETCH_WORD,D); end
1742
                        2'b10:  begin push(NEG); fs_data(mmm,rrr,FETCH_LWORD,D); end
1743
                        2'b11:  // MOVE ,ccr
1744
                                begin
1745
                                        flag_update <= FU_MOVE2CCR;
1746
                                        fs_data(mmm,rrr,FETCH_WORD,S);
1747
                                end
1748
                        endcase
1749
                9'b0110?????:
1750
                        case(sz)
1751
                        2'b00:  begin push(NOT); fs_data(mmm,rrr,FETCH_BYTE,D); end
1752
                        2'b01:  begin push(NOT); fs_data(mmm,rrr,FETCH_WORD,D); end
1753
                        2'b10:  begin push(NOT); fs_data(mmm,rrr,FETCH_LWORD,D); end
1754
                        2'b11:
1755
                                if (sf) begin   // MOVE ,sr
1756
                                        flag_update <= FU_MOVE2SR;
1757
                                        fs_data(mmm,rrr,FETCH_WORD,S);
1758
                                end
1759
                                else
1760
                                        tPrivilegeViolation();
1761
                        default:        ;
1762
                        endcase
1763
/*
1764
                9'b0111?????:
1765
                        case(sz)
1766
                        2'b00:  tIllegal();
1767
                        2'b01:  tIllegal();
1768
                        2'b10:  tIllegal();
1769
                        2'b11:
1770
                                if (sf) begin   // MOVE ,srx
1771
                                        flag_update <= FU_MOVE2SRX;
1772
                                        fs_data(mmm,rrr,FETCH_LWORD,S);
1773
                                end
1774
                                else
1775
                                        tPrivilegeViolation();
1776
                        default:        ;
1777
                        endcase
1778
*/
1779
                9'b10001?000:
1780
                        if (ir[6]) begin        // EXT.L
1781
                                cf <= 1'b0;
1782
                                vf <= 1'b0;
1783
                                nf <= rfoRnn[15];
1784
                                zf <= rfoRnn[15:0]==16'h0000;
1785
                                rfwrL <= 1'b1;
1786
                                Rt <= {1'b0,ir[2:0]};
1787
                                resL <= {{16{rfoRnn[15]}},rfoRnn[15:0]};
1788
                                ret();
1789
                        end
1790
                        else begin      // EXT.W
1791
                                cf <= 1'b0;
1792
                                vf <= 1'b0;
1793
                                nf <= rfoRnn[7];
1794
                                zf <= rfoRnn[7:0]==8'h00;
1795
                                rfwrW <= 1'b1;
1796
                                Rt <= {1'b0,ir[2:0]};
1797
                                resW <= {rfoRnn[31:16],{8{rfoRnn[7]}},rfoRnn[7:0]};
1798
                                ret();
1799
                        end
1800
`ifdef SUPPORT_BCD
1801
                9'b100000???:   // NBCD
1802
                        begin
1803
                                bcdneg <= 1'b1;
1804
                                push(BCD1);
1805
                                fs_data(mmm,rrr,FETCH_BYTE,D);
1806
                        end
1807
`endif
1808
                9'b100001000:   // 484x         SWAP
1809
                        begin
1810
                                cf <= 1'b0;
1811
                                vf <= 1'b0;
1812
                                zf <= rfoDnn==32'd0;
1813
                                nf <= rfoDnn[15];
1814
                                resL <= {rfoDnn[15:0],rfoDnn[31:16]};
1815
                                Rt <= {1'b0,rrr};
1816
                                rfwrL <= 1'b1;
1817
                                ret();
1818
                        end
1819
                9'b100001???:   // PEA
1820
                        begin
1821
                                lea <= 1'b1;
1822
                                goto (PEA1);
1823
                        end
1824
                9'b101011111:
1825
                        case(ir[3:0])
1826
                        4'hC:   tIllegal();     // 4AFC Illegal
1827
                        endcase
1828
                9'b1010?????:   // TST / TAS
1829
                        case(sz)
1830
                        2'b00:  begin flag_update <= FU_TST; fs_data(mmm,rrr,FETCH_BYTE,D); end
1831
                        2'b01:  begin flag_update <= FU_TST; fs_data(mmm,rrr,FETCH_WORD,D); end
1832
                        2'b10:  begin flag_update <= FU_TST; fs_data(mmm,rrr,FETCH_LWORD,D); end
1833
                        2'b11:  begin push(TAS); fs_data(mmm,rrr,LFETCH_BYTE,D); end            // TAS
1834
                        endcase
1835
                9'b11100100?:
1836
                        goto (TRAP);
1837
                9'b111001010:
1838
                        goto (LINK);
1839
                9'b111001011:
1840
                        begin           // UNLK
1841
                                sp <= rfoAn;
1842
                                goto (UNLNK);
1843
                        end
1844
                9'b11100110?:
1845
                        if (ir[3]) begin
1846
                                ret();
1847
                                Rt <= {1'b1,rrr};
1848
                                rfwrL <= 1'b1;
1849
                                resL <= usp;
1850
                        end
1851
                        else begin
1852
                                ret();
1853
                                usp <= rfoAn;
1854
                        end
1855
                9'b111001110:   // 4E70 RESET
1856
                        case(ir[2:0])
1857
                        3'b000:
1858
                                if (sf) begin
1859
                                        rst_o <= 1'b1;
1860
                                        rst_cnt <= 5'd10;
1861
                                        ret();
1862
                                end
1863
                                else
1864
                                        tPrivilegeViolation();
1865
                        3'b001: ret();  // NOP
1866
                        3'b010:
1867
                                if (sf)
1868
                                        goto (STOP);
1869
                                else
1870
                                        tPrivilegeViolation();
1871
                        3'b011:
1872
                                if (sf)
1873
                                        goto (RTE1);
1874
                                else
1875
                                        tPrivilegeViolation();
1876
                        3'b101:
1877
                                begin
1878
                                        ea <= sp;
1879
                                        sp <= sp + 4'd4;
1880
                                        ds <= S;
1881
                                        call (FETCH_LWORD,RTS1);
1882
                                end
1883
                        3'b110:
1884
                                if (vf) begin
1885
                        isr <= srx;
1886
                        tf <= 1'b0;
1887
                        sf <= 1'b1;
1888
                            vecno <= `TRAPV_VEC;
1889
                        goto (TRAP3);
1890
                                end
1891
                                else
1892
                                        ret();          // 4E76 TRAPV
1893
                        3'b111:
1894
                                begin
1895
                                        rtr <= 1'b1;
1896
                                        goto (RTE1); // RTR
1897
                                end
1898
                        endcase
1899
                9'b111001111:
1900
                        case(ir[2:0])
1901
                        3'b010:         call(FETCH_IMM16,MOVERc2Rn);
1902
                        3'b011:         call(FETCH_IMM16,MOVERn2Rc);
1903
                        default:        tIllegal();
1904
                        endcase
1905
                9'b111010???:   // JSR
1906
                        begin
1907
                                push(JSR);
1908
                                fs_data(mmm,rrr,FETCH_LWORD,D);
1909
                        end
1910
                9'b111011???:   // JMP
1911
                        begin
1912
                                push(JMP);
1913
                                fs_data(mmm,rrr,FETCH_NOP_LWORD,D);
1914
                        end
1915
                9'b1?001????:
1916
                        if (ir[10])
1917
                                call(FETCH_IMM16,MOVEM_s2Xn);
1918
                        else
1919
                                call(FETCH_IMM16,MOVEM_Xn2D);
1920
                9'b???111???:
1921
                        begin // LEA
1922
                                lea <= 1'b1;    // ToDo: fix this, lea needs to be set one cycle before fs_data is called
1923
                                goto (LEA);
1924
                        end
1925
                9'b???110???:
1926
                        begin   // CHK
1927
                                d <= rfoDn;
1928
                                push(CHK);
1929
                                fs_data(mmm,rrr,FETCH_WORD,S);
1930
                        end
1931
                default:
1932
                        tIllegal();
1933
                endcase
1934
//***           4'hF:   state <= RTD1;  // 4Fxx = rtd
1935
 
1936
//-----------------------------------------------------------------------------
1937
// ADDQ / SUBQ / DBRA / Scc
1938
//-----------------------------------------------------------------------------
1939
        5'h5:
1940
                begin
1941 3 robfinch
                        casez(ir[7:3])
1942 2 robfinch
                        // When optimizing DBRA for performance, the memory access cycle to fetch
1943
                        // the displacement constant is not done, instead the PC is incremented by
1944
                        // two if not doing the DBRA. This is an extra PC increment that increases
1945
                        // the code size. It is slower, but more hardware efficient to just always
1946
                        // fetch the displacement.
1947 3 robfinch
                        5'b11001:                                       // DBRA
1948 2 robfinch
`ifdef OPT_PERF
1949
                                if (~takb) begin
1950
                                        call(FETCH_IMM16,DBRA);
1951
                                end
1952
                                else begin
1953
                                        pc <= pc + 32'd4;       // skip over displacement
1954
                                        ret();
1955
                                end
1956
`else
1957
                                call(FETCH_IMM16,DBRA);
1958
`endif
1959 3 robfinch
                        5'b11???:               // Scc
1960 2 robfinch
                                begin
1961
                                        resL <= {32{takb}};
1962
                                        resW <= {16{takb}};
1963
                                        resB <= {8{takb}};
1964
                                        d <= {32{takb}};
1965
                                        if (mmm==3'b000) begin
1966
                                                rfwrB <= 1'b1;
1967
                                                Rt <= {1'b0,rrr};
1968
                                                ret();
1969
                                        end
1970
                                        else begin
1971
                                                fs_data(mmm,rrr,STORE_BYTE,S);
1972
                                        end
1973
                                end
1974
                        default:
1975
                                begin
1976
                                        case(QQQ)
1977
                                        3'd0:   begin imm <= 32'd8; immx <= 32'd8; end
1978
                                        default:        begin imm <= {29'd0,QQQ}; immx <= {29'd0,QQQ}; end
1979
                                        endcase
1980
                                        case(sz)
1981
                                        2'b00:  begin push(ADDQ); fs_data(mmm,rrr,FETCH_BYTE,D); end
1982
                                        2'b01:  begin push(ADDQ); fs_data(mmm,rrr,FETCH_WORD,D); end
1983
                                        2'b10:  begin push(ADDQ); fs_data(mmm,rrr,FETCH_LWORD,D); end
1984
                                        default:        tIllegal();
1985
                                        endcase
1986
                                end
1987
                        endcase
1988
                end
1989
 
1990
//-----------------------------------------------------------------------------
1991
// Branches
1992
//-----------------------------------------------------------------------------
1993
        5'h6:
1994
                begin
1995
                        opc <= pc + 4'd2;
1996
                        ea <= pc + {{24{ir[7]}},ir[7:1],1'b0} + 4'd2;
1997
                        if (ir[11:0]==12'h100) begin            // 6100 = BSR
1998
                                bsr <= 1'b1;
1999
                                call(FETCH_BRDISP,JSR);
2000
                        end
2001
                        else if (ir[11:8]==4'h1)        // 61xx = BSR
2002
                                goto(JSR);
2003
                        else if (takb) begin
2004
                                // If branch back to self, trap
2005
                          if (ir[7:0]==8'hFE)
2006
                                tBadBranchDisp();
2007
                                else
2008
`ifdef SUPPORT_B24
2009
                                if (ir[7:0]==8'h00 || ir[0]) begin
2010
`else
2011
                                if (ir[7:0]==8'h00) begin
2012
`endif
2013
                                        goto(FETCH_BRDISP);
2014
                                end
2015
                                else begin
2016
                                        pc <= pc + {{24{ir[7]}},ir[7:1],1'b0} + 4'd2;
2017
                                        ret();
2018
                                end
2019
                        end
2020
                        else begin
2021
`ifdef SUPPORT_B24
2022
                                if (ir[7:0]==8'h00 || ir[0])            // skip over long displacement
2023
`else
2024
                                if (ir[7:0]==8'h00)             // skip over long displacement
2025
`endif
2026
                                        pc <= pc + 4'd4;
2027
                                ret();
2028
                        end
2029
                end
2030
 
2031
//-----------------------------------------------------------------------------
2032
// MOVEQ
2033
//-----------------------------------------------------------------------------
2034
        5'h7:
2035
                // MOVEQ only if ir[8]==0, but it is otherwise not used for the 68k.
2036
                // So some decode and fmax is saved by not decoding ir[8]
2037
                //if (ir[8]==1'b0)
2038
                begin
2039
                        vf <= 1'b0;
2040
                        cf <= 1'b0;
2041
                        nf <= ir[7];
2042
                        zf <= ir[7:0]==8'h00;
2043
                        rfwrL <= 1'b1;
2044
                        Rt <= {1'b0,ir[11:9]};
2045
                        resL <= {{24{ir[7]}},ir[7:0]};
2046
                        ret();
2047
                end
2048
//-----------------------------------------------------------------------------
2049
// OR / DIVU / DIVS / SBCD
2050
//-----------------------------------------------------------------------------
2051
        5'h8:
2052
                begin
2053
                        casez(ir[11:0])
2054
`ifdef SUPPORT_DIV
2055
                        12'b????_11??_????:     // DIVU / DIVS
2056
                                begin
2057
                                        divs <= ir[8];
2058
                                        d <= rfoDn;
2059
                                        push(DIV1);
2060
                                        fs_data(mmm,rrr,FETCH_WORD,S);
2061
                                end
2062
`endif
2063
`ifdef SUPPORT_BCD
2064
                        12'b???1_0000_????:     // SBCD
2065
                                begin
2066
                                        bcdsub <= 1'b1;
2067
                                        if (ir[3])
2068
                                                goto (BCD);
2069
                                        else begin
2070
                                                s <= rfoDnn;
2071
                                                d <= rfoDn;
2072
                                                goto (BCD1);
2073
                                        end
2074
                                end
2075
`endif
2076
                        default:
2077
                                begin
2078
                case(sz)
2079
                2'b00:    begin push(OR); fs_data(mmm,rrr,FETCH_BYTE,ir[8]?D:S); end
2080
                2'b01:    begin push(OR); fs_data(mmm,rrr,FETCH_WORD,ir[8]?D:S); end
2081
                2'b10:    begin push(OR); fs_data(mmm,rrr,FETCH_LWORD,ir[8]?D:S); end
2082
                default:        ;       // can't get here, picked off by DIV
2083
                                        endcase
2084
                                end
2085
                        endcase
2086
                end
2087
//-----------------------------------------------------------------------------
2088
// SUB / SUBA / SUBX
2089
//-----------------------------------------------------------------------------
2090
  5'h9:
2091
    begin
2092
      if (ir[8])
2093
        s <= rfoDn;
2094
      else
2095
        d <= rfoDn;
2096
      if (ir[8] && ir[5:4]==2'b00)
2097
                                case(sz)
2098
                                2'b00:
2099
                                        if (ir[3])
2100
                                                goto (SUBX);
2101
                                        else begin
2102
                                                s <= rfoDnn;
2103
                                                d <= rfoDn;
2104
                                                goto (SUBX3);
2105
                                        end
2106
                                2'b01:
2107
                                        if (ir[3])
2108
                                                goto (SUBX);
2109
                                        else begin
2110
                                                s <= rfoDnn;
2111
                                                d <= rfoDn;
2112
                                                goto (SUBX3);
2113
                                        end
2114
                                2'b10:
2115
                                        if (ir[3])
2116
                                                goto (SUBX);
2117
                                        else begin
2118
                                                s <= rfoDnn;
2119
                                                d <= rfoDn;
2120
                                                goto (SUBX3);
2121
                                        end
2122
                                2'b11:
2123
                begin
2124
                        d <= rfoAna;
2125
                        push(SUB);
2126
                        if (ir[8]) fs_data(mmm,rrr,FETCH_LWORD,S);
2127
                        else fs_data(mmm,rrr,FETCH_WORD,S);
2128
                end
2129
                                endcase
2130
      else
2131
              case(sz)
2132
              2'b00:    begin push(SUB); fs_data(mmm,rrr,FETCH_BYTE,ir[8]?D:S); end
2133
              2'b01:    begin push(SUB); fs_data(mmm,rrr,FETCH_WORD,ir[8]?D:S); end
2134
              2'b10:    begin push(SUB); fs_data(mmm,rrr,FETCH_LWORD,ir[8]?D:S); end
2135
              2'b11:
2136
                begin
2137
                        d <= rfoAna;
2138
                        push(SUB);
2139
                        if (ir[8]) fs_data(mmm,rrr,FETCH_LWORD,S);
2140
                        else fs_data(mmm,rrr,FETCH_WORD,S);
2141
                end
2142
              endcase
2143
    end
2144
//-----------------------------------------------------------------------------
2145
//-----------------------------------------------------------------------------
2146
  5'hA:
2147
        if (ir[11:8]==4'h2)
2148
                goto (IFETCH2);
2149
                else begin
2150
                isr <= srx;
2151
                tf <= 1'b0;
2152
                sf <= 1'b1;
2153
        vecno <= `LINE10_VEC;
2154
        goto (TRAP3);
2155
        end
2156
//-----------------------------------------------------------------------------
2157
// CMP / CMPA / CMPM / EOR
2158
//-----------------------------------------------------------------------------
2159
        5'hB:
2160
                begin
2161
                        if (ir[8]) begin        // EOR
2162
                                if (mmm==001)
2163
                                        case(sz)
2164
                                        2'b00:  begin push(CMPM); fs_data(3'b011,rrr,FETCH_BYTE,S); end
2165
                                        2'b01:  begin push(CMPM); fs_data(3'b011,rrr,FETCH_WORD,S); end
2166
                                        2'b10:  begin push(CMPM); fs_data(3'b011,rrr,FETCH_LWORD,S); end
2167
                                        2'b11:  begin d <= rfoAna; push(CMPA); fs_data(mmm,rrr,FETCH_LWORD,S); end      // CMPA
2168
                                        endcase
2169
                                else
2170
                                        case(sz)
2171
                                        2'b00:  begin push(EOR); fs_data(mmm,rrr,FETCH_BYTE,D); end
2172
                                        2'b01:  begin push(EOR); fs_data(mmm,rrr,FETCH_WORD,D); end
2173
                                        2'b10:  begin push(EOR); fs_data(mmm,rrr,FETCH_LWORD,D); end
2174
                                        2'b11:  begin d <= rfoAna; push(CMPA); fs_data(mmm,rrr,FETCH_LWORD,S); end      // CMPA
2175
                                        endcase
2176
                        end
2177
                        else    // CMP
2178
                                case(sz)
2179
                                2'b00:  begin d <= rfoDn; push(CMP); fs_data(mmm,rrr,FETCH_BYTE,S); end
2180
                                2'b01:  begin d <= rfoDn; push(CMP); fs_data(mmm,rrr,FETCH_WORD,S); end
2181
                                2'b10:  begin d <= rfoDn; push(CMP); fs_data(mmm,rrr,FETCH_LWORD,S); end
2182
                                2'b11:  begin d <= rfoAna; push(CMPA); fs_data(mmm,rrr,FETCH_WORD,S); end       // CMPA
2183
                                endcase
2184
                end
2185
//-----------------------------------------------------------------------------
2186
// AND / EXG / MULU / MULS / ABCD
2187
//-----------------------------------------------------------------------------
2188
        5'hC:
2189
                begin
2190
                        casez(ir[11:0])
2191
`ifdef SUPPORT_BCD
2192
                        12'b???1_0000_????:     // ABCD
2193
                                if (ir[3])
2194
                                        goto (BCD);
2195
                                else begin
2196
                                        s <= rfoDnn;
2197
                                        d <= rfoDn;
2198
                                        goto (BCD1);
2199
                                end
2200
`endif
2201
                        12'b????_11??_????:     // MULS / MULU
2202
                                begin
2203
                                        push(ir[8] ? MULS1 : MULU1);
2204
                                        fs_data(mmm,rrr,FETCH_WORD,S);
2205
                                end
2206
                        12'b???1_0100_0???:     // EXG  Dx,Dy
2207
                        begin
2208
                                Rt <= {1'b0,DDD};
2209
                                rfwrL <= 1'b1;
2210
                                resL <= rfoRnn;
2211
                                s <= rfoDn;
2212
                                goto (EXG1);
2213
                        end
2214
                        12'b???1_0100_1???:     // EXG Ax,Ay
2215
                        begin
2216
                                Rt <= {1'b1,AAA};
2217
                                rfwrL <= 1'b1;
2218
                                resL <= rfoRnn;
2219
                                s <= rfoAna;
2220
                                goto (EXG1);
2221
                        end
2222
                        12'b???1_1000_1???:     // EXG Dx,Ay
2223
                        begin
2224
                                Rt <= {1'b0,DDD};
2225
                                rfwrL <= 1'b1;
2226
                                resL <= rfoRnn;
2227
                                s <= rfoDn;
2228
                                goto (EXG1);
2229
                        end
2230
                        default:
2231
                                case(sz)
2232
                                2'b00:  begin push(AND); fs_data(mmm,rrr,FETCH_BYTE,ir[8]?D:S); end
2233
                                2'b01:  begin push(AND); fs_data(mmm,rrr,FETCH_WORD,ir[8]?D:S); end
2234
                                2'b10:  begin push(AND); fs_data(mmm,rrr,FETCH_LWORD,ir[8]?D:S); end
2235
                                default:        ;       // Can't get here, picked off by MUL
2236
                                endcase
2237
                        endcase
2238
                end
2239
 
2240
//-----------------------------------------------------------------------------
2241
// ADD / ADDA / ADDX
2242
//-----------------------------------------------------------------------------
2243
        5'hD:
2244
                begin
2245
                        if (ir[8])
2246
                                s <= rfoDn;
2247
                        else
2248
                                d <= rfoDn;
2249
                        if (ir[8] && ir[5:4]==2'b00)
2250
                                case(sz)
2251
                                2'b00:
2252
                                        if (ir[3])
2253
                                                goto (ADDX);
2254
                                        else begin
2255
                                                s <= rfoDnn;
2256
                                                d <= rfoDn;
2257
                                                goto (ADDX3);
2258
                                        end
2259
                                2'b01:
2260
                                        if (ir[3])
2261
                                                goto (ADDX);
2262
                                        else begin
2263
                                                s <= rfoDnn;
2264
                                                d <= rfoDn;
2265
                                                goto (ADDX3);
2266
                                        end
2267
                                2'b10:
2268
                                        if (ir[3])
2269
                                                goto (ADDX);
2270
                                        else begin
2271
                                                s <= rfoDnn;
2272
                                                d <= rfoDn;
2273
                                                goto (ADDX3);
2274
                                        end
2275
                                2'b11:
2276
                                        begin
2277
                                                d <= rfoAna;
2278
                                                push(ADD);
2279
                                                if (ir[8]) fs_data(mmm,rrr,FETCH_LWORD,S);
2280
                                                else fs_data(mmm,rrr,FETCH_WORD,S);
2281
                                        end
2282
                                endcase
2283
                        else
2284
                                case(sz)
2285
                                2'b00:  begin push(ADD); fs_data(mmm,rrr,FETCH_BYTE,ir[8]?D:S); end
2286
                                2'b01:  begin push(ADD); fs_data(mmm,rrr,FETCH_WORD,ir[8]?D:S); end
2287
                                2'b10:  begin push(ADD); fs_data(mmm,rrr,FETCH_LWORD,ir[8]?D:S); end
2288
                                2'b11:
2289
                                        begin
2290
                                                d <= rfoAna;
2291
                                                push(ADD);
2292
                                                if (ir[8]) fs_data(mmm,rrr,FETCH_LWORD,S);
2293
                                                else fs_data(mmm,rrr,FETCH_WORD,S);
2294
                                        end
2295
                                endcase
2296
                end
2297
//-----------------------------------------------------------------------------
2298
// ASL / LSL / ASR / LSR / ROL / ROR / ROXL / ROXR
2299
//-----------------------------------------------------------------------------
2300
        5'hE:
2301
                begin
2302
                        if (sz==2'b11) begin
2303
                                cnt <= 6'd1;    // memory shifts only by one
2304
                                shift_op <= {ir[8],ir[10:9]};
2305
                                push(SHIFT1);
2306
                                fs_data(mmm,rrr,FETCH_WORD,D);
2307
                        end
2308
                        else begin
2309
                                shift_op <= {ir[8],ir[4:3]};
2310
                                goto (SHIFT1);
2311
                                if (ir[5])
2312
                                        cnt <= rfoDn[5:0];
2313
                                else
2314
                                        cnt <= {2'b0,~|QQQ,QQQ};
2315
                                // Extend by a bit for ASL overflow detection.
2316
                                resL <= {rfoDnn[31],rfoDnn};
2317
                                resB <= {rfoDnn[7],rfoDnn[7:0]};
2318
                                resW <= {rfoDnn[15],rfoDnn[15:0]};
2319
                                d <= rfoDnn;
2320
                        end
2321
                end
2322
//-----------------------------------------------------------------------------
2323
//-----------------------------------------------------------------------------
2324
  5'hF:
2325
    begin
2326
                isr <= srx;
2327
                tf <= 1'b0;
2328
                sf <= 1'b1;
2329
        vecno <= `LINE15_VEC;
2330
        goto (TRAP3);
2331
    end
2332
//-----------------------------------------------------------------------------
2333
//-----------------------------------------------------------------------------
2334
        5'h1A:
2335
                begin
2336
                        ext_ir <= 1'b0;
2337
                        if (ir[11:8]==4'h2) begin
2338
                                case(ir2[15:0])
2339
                                16'h0000:
2340
                                        begin
2341
                                                dd32in <= rfoDnn;
2342
                                                goto (BIN2BCD1);
2343
                                        end
2344
                                16'h0001:
2345
                                        begin
2346
                                                d <= rfoDnn;
2347
                                                goto (BCD2BIN1);
2348
                                        end
2349
                                default:        tIllegal();
2350
                                endcase
2351
                        end
2352
                end
2353
        default: tIllegal();
2354
        endcase
2355
        end
2356
 
2357
//-----------------------------------------------------------------------------
2358
//-----------------------------------------------------------------------------
2359
`ifdef SUPPORT_010
2360
MOVES:
2361
        begin
2362
                ir2 <= imm[15:0];
2363
                rrrr <= imm[15:12];
2364
                Rt <= imm[15:12];
2365
                if (imm[11])
2366
                        goto (MOVES2);
2367
                else begin
2368
                        push(MOVES3);
2369
                        use_sfc <= 1'b1;
2370
                        case(sz)
2371
                        2'd0:   fs_data(mmm,rrr,FETCH_BYTE,S);
2372
                        2'd1:   fs_data(mmm,rrr,FETCH_WORD,S);
2373
                        2'd2:   fs_data(mmm,rrr,FETCH_LWORD,S);
2374
                        endcase
2375
                end
2376
        end
2377
MOVES2:
2378
        begin
2379
                d <= rfoRnn;
2380
                use_dfc <= 1'b1;
2381
                case(sz)
2382
                2'd0:   fs_data(mmm,rrr,STORE_BYTE,D);
2383
                2'd1:   fs_data(mmm,rrr,STORE_WORD,D);
2384
                2'd2:   fs_data(mmm,rrr,STORE_LWORD,D);
2385
                default:        tIllegal();
2386
                endcase
2387
        end
2388
MOVES3:
2389
        begin
2390
                case(sz)
2391
                2'd0:
2392
                        begin
2393
                                resB <= s[7:0];
2394
                                rfwrB <= 1'b1;
2395
                        end
2396
                2'd1:
2397
                        begin
2398
                                resW <= s[15:0];
2399
                                rfwrW <= 1'b1;
2400
                        end
2401
                2'd2:
2402
                        begin
2403
                                resL <= s[31:0];
2404
                                rfwrL <= 1'b1;
2405
                        end
2406
                default:        ;
2407
                endcase
2408
                ret();
2409
        end
2410
`endif
2411
 
2412
//-----------------------------------------------------------------------------
2413
// BCD arithmetic
2414
// ABCD / SBCD / NBCD
2415
//-----------------------------------------------------------------------------
2416
`ifdef SUPPORT_BCD
2417
BCD:
2418
        begin
2419
                push(BCD0);
2420
                fs_data(3'b100,rrr,FETCH_BYTE,S);
2421
        end
2422
BCD0:
2423
        begin
2424
                if (ir[3]) begin
2425
                        push(BCD1);
2426
                        fs_data(3'b100,RRR,FETCH_BYTE,D);
2427
                end
2428
                else
2429
                        goto (BCD1);
2430
        end
2431
BCD1:   goto (BCD2);    // clock to convert BCD to binary.
2432
BCD2:
2433
        begin
2434
                if (bcdsub)
2435
                        bcdres <= dbin - sbin - xf;
2436
                else if (bcdneg)
2437
                        bcdres <= 8'h00 - dbin - xf;
2438
                else
2439
                        bcdres <= dbin + sbin + xf;
2440
                goto (BCD3);
2441
        end
2442
BCD3:   goto (BCD4);    // clock to load binary to BCD conversion
2443
BCD4:
2444
        if (dd_done) begin
2445
                if (ir[3] || (bcdneg && mmm!=3'b000 && mmm != 3'b001))
2446
                        goto (STORE_BYTE);
2447
                else begin
2448
                        rfwrB <= 1'b1;
2449
                        if (bcdneg)
2450
                                Rt <= {1'b0,rrr};
2451
                        else
2452
                                Rt <= {1'b0,RRR};
2453
                        resB <= bcdreso[7:0];
2454
                        ret();
2455
                end
2456
                d <= bcdreso[7:0];
2457
                cf <= |bcdreso[11:8];
2458
                xf <= |bcdreso[11:8];
2459
                nf <= bcdreso[7];
2460
                if (bcdreso[7:0]!=8'h00)
2461
                        zf <= 1'b0;
2462
        end
2463
`endif
2464
 
2465
//-----------------------------------------------------------------------------
2466
//-----------------------------------------------------------------------------
2467
STOP:
2468
        begin
2469
                if (!sf) begin
2470
                isr <= srx;
2471
                tf <= 1'b0;
2472
                sf <= 1'b1;
2473
                        vecno <= `PRIV_VEC;
2474
                        goto (TRAP3);
2475
                end
2476
                else
2477
                        call (FETCH_IMM16, STOP1);
2478
        end
2479
STOP1:
2480
        begin
2481
                cf <= imm[0];
2482
                vf <= imm[1];
2483
                zf <= imm[2];
2484
                nf <= imm[3];
2485
                xf <= imm[4];
2486
                im[0] <= imm[8];
2487
                im[1] <= imm[9];
2488
                im[2] <= imm[10];
2489
                sf <= imm[13];
2490
                tf <= imm[15];
2491
                if (ipl_i > imm[10:8] || ipl_i==3'd7)
2492
                        ret();
2493
        end
2494
 
2495
//-----------------------------------------------------------------------------
2496
// MULU / MULS
2497
// - a couple of regs may be needed.
2498
//-----------------------------------------------------------------------------
2499
MULS1:
2500
        begin
2501
                resMS1 <= $signed(rfoDn[15:0]) * $signed(s[15:0]);
2502
                goto (MULS2);
2503
        end
2504
MULS2:
2505
        begin
2506
                resMS2 <= resMS1;
2507
                goto (MULS3);
2508
        end
2509
MULS3:
2510
        begin
2511
                flag_update <= FU_MUL;
2512
                rfwrL <= 1'b1;
2513
                Rt <= {1'b0,DDD};
2514
                resL <= resMS2;
2515
                ret();
2516
        end
2517
MULU1:
2518
        begin
2519
                resMU1 <= rfoDn[15:0] * s[15:0];
2520
                goto (MULU2);
2521
        end
2522
MULU2:
2523
        begin
2524
                resMU2 <= resMU1;
2525
                goto (MULU3);
2526
        end
2527
MULU3:
2528
        begin
2529
                flag_update <= FU_MUL;
2530
                rfwrL <= 1'b1;
2531
                Rt <= {1'b0,DDD};
2532
                resL <= resMU2;
2533
                ret();
2534
        end
2535
 
2536
//-----------------------------------------------------------------------------
2537
// DIVU / DIVS
2538
// - the target register is not updated if overflow occurs.
2539
//-----------------------------------------------------------------------------
2540
DIV1:
2541
        if (s[15:0]==16'd0) begin
2542
                isr <= srx;
2543
                tf <= 1'b0;
2544
                sf <= 1'b1;
2545
                vecno <= `DBZ_VEC;
2546
                goto (TRAP3);
2547
        end
2548
        else
2549
                goto (DIV2);
2550
DIV2:
2551
        if (dvdone) begin
2552
                cf <= 1'b0;
2553
                if (dvovf)
2554
                        vf <= 1'b1;
2555
                else begin
2556
                        nf <= divq[15];
2557
                        zf <= divq[15:0]==16'h0000;
2558
                        vf <= 1'b0;
2559
                        Rt <= {1'b0,DDD};
2560
                        resL <= {divr[15:0],divq[15:0]};
2561
                        rfwrL <= 1'b1;
2562
                end
2563
                ret();
2564
        end
2565
 
2566
//-----------------------------------------------------------------------------
2567
// NOT
2568
//-----------------------------------------------------------------------------
2569
NOT:
2570
        begin
2571
                resB <= ~d[7:0];
2572
                resW <= ~d[15:0];
2573
                resL <= ~d;
2574
                d <= ~d;
2575
                cf <= 1'b0;
2576
                vf <= 1'b0;
2577
                case(sz)
2578
                2'b00:  begin zf <= d[7:0]==8'hFF; nf <= ~d[7]; end
2579
                2'b01:  begin zf <= d[15:0]==16'hFFFF; nf <= ~d[15]; end
2580
                2'b10:  begin zf <= d[31:0]==32'hFFFFFFFF; nf <= ~d[31]; end
2581
                default:        ;
2582
                endcase
2583
                if (mmm==3'b000) begin
2584
                        Rt <= {1'b0,rrr};
2585
                        case(sz)
2586
                        2'b00:  rfwrB <= 1'b1;
2587
                        2'b01:  rfwrW <= 1'b1;
2588
                        2'b10:  rfwrL <= 1'b1;
2589
                        default:        ;
2590
                        endcase
2591
                        ret();
2592
                end
2593
                else if (mmm==3'b001)
2594
                        ret();
2595
                else begin
2596
                        case(sz)
2597
                        2'b00:  begin goto(STORE_BYTE); end
2598
                        2'b01:  begin goto(STORE_WORD); end
2599
                        2'b10:  begin goto(STORE_LWORD); end
2600
                        default:        ;
2601
                        endcase
2602
                end
2603
        end
2604
 
2605
//-----------------------------------------------------------------------------
2606
// NEG / NEGX
2607
//-----------------------------------------------------------------------------
2608
NEG:
2609
        begin
2610
                resL <= -d;
2611
                resW <= -d[15:0];
2612
                resB <= -d[7:0];
2613
                d <= -d;
2614
                s <= d;
2615
                dd <= 'd0;
2616
                goto (NEGX1);
2617
        end
2618
NEGX:
2619
        begin
2620
                resL <= -d - xf;
2621
                resW <= -d[15:0] - xf;
2622
                resB <= -d[7:0] - xf;
2623
                d <= -d - xf;
2624
                s <= d + xf;
2625
                dd <= 'd0;
2626
                goto (NEGX1);
2627
        end
2628
NEGX1:
2629
        begin
2630
                case(sz)
2631
                2'b00:  begin cf <= resB[8]; nf <= resB[7]; vf <= fnSubOverflow(resB[7],dd[7],s[7]); zf <= resB[7:0]==8'h00; xf <= resB[8]; end
2632
                2'b01:  begin cf <= resW[16]; nf <= resW[15]; vf <= fnSubOverflow(resW[15],dd[15],s[15]); zf <= resW[15:0]==16'h00; xf <= resW[16]; end
2633
                2'b10:  begin cf <= resL[32]; nf <= resL[31]; vf <= fnSubOverflow(resL[31],dd[31],s[31]); zf <= resL[31:0]==32'h00; xf <= resL[32]; end
2634
                endcase
2635
                if (mmm==3'b000) begin
2636
                        Rt <= {1'b0,rrr};
2637
                        case(sz)
2638
                        2'b00:  rfwrB <= 1'b1;
2639
                        2'b01:  rfwrW <= 1'b1;
2640
                        2'b10:  rfwrL <= 1'b1;
2641
                        default:        ;
2642
                        endcase
2643
                        ret();
2644
                end
2645
                else if (mmm==3'b001)
2646
                        ret();
2647
                else
2648
                        case(sz)
2649
                        2'b00:  begin goto(STORE_BYTE); end
2650
                        2'b01:  begin goto(STORE_WORD); end
2651
                        2'b10:  begin goto(STORE_LWORD); end
2652
                        default:        ;
2653
                        endcase
2654
        end
2655
 
2656
//-----------------------------------------------------------------------------
2657
//-----------------------------------------------------------------------------
2658
TAS:
2659
        begin
2660
                resB <= {1'b1,d[6:0]};
2661
                cf <= 1'b0;
2662
                vf <= 1'b0;
2663
                zf <= d[7:0]==8'h00;
2664
                nf <= d[7];
2665
                d <= {1'b1,d[6:0]};
2666
                goto(USTORE_BYTE);
2667
        end
2668
 
2669
//-----------------------------------------------------------------------------
2670
// Link
2671
//-----------------------------------------------------------------------------
2672
LINK:
2673
        begin
2674
                d <= rfoAn;
2675
                ea <= sp - 4'd4;
2676
                call (STORE_LWORD,LINK1);
2677
        end
2678
LINK1:
2679
        begin
2680
                call(FETCH_IMM16,LINK2);
2681
        end
2682
LINK2:
2683
        begin
2684
                resL <= sp - 32'd4;
2685
                rfwrL <= 1'b1;
2686
                Rt <= {1'b1,rrr};
2687
                sp <= sp + imm - 32'd4;
2688
                ret();
2689
        end
2690
 
2691
//-----------------------------------------------------------------------------
2692
// LEA
2693
//-----------------------------------------------------------------------------
2694
LEA:
2695
        begin
2696
                push(LEA2);
2697
                fs_data(mmm,rrr,FETCH_NOP_LWORD,S);
2698
        end
2699
LEA2:
2700
        begin
2701
                Rt <= {1'b1,AAA};
2702
                rfwrL <= 1'b1;
2703
                resL <= ea;
2704
                ret();
2705
        end
2706
 
2707
//-----------------------------------------------------------------------------
2708
// PEA
2709
//-----------------------------------------------------------------------------
2710
PEA1:
2711
        begin
2712
                push(PEA2);
2713
                fs_data(mmm,rrr,FETCH_NOP_LWORD,S);
2714
        end
2715
PEA2:
2716
        begin
2717
                d <= ea;
2718
                ea <= sp - 32'd4;
2719
                call (STORE_LWORD,PEA3);
2720
        end
2721
PEA3:
2722
        begin
2723
                sp <= sp - 32'd4;
2724
                ret();
2725
        end
2726
 
2727
//-----------------------------------------------------------------------------
2728
// DBRA
2729
//-----------------------------------------------------------------------------
2730
DBRA:
2731
`ifndef OPT_PERF
2732
        if (~takb)
2733
`endif
2734
        begin
2735
                resW <= rfoDnn - 4'd1;
2736
                Rt <= {1'b0,rrr};
2737
                rfwrW <= 1'b1;
2738
                if (rfoDnn[15:0]!=0)
2739
                        pc <= opc + imm;
2740
                ret();
2741
        end
2742
`ifndef OPT_PERF
2743
        else
2744
                ret();
2745
`endif
2746
 
2747
//-----------------------------------------------------------------------------
2748
// EXG
2749
//-----------------------------------------------------------------------------
2750
EXG1:
2751
        begin
2752
                rfwrL <= 1'b1;
2753
                resL <= s;
2754
                Rt <= rrrr;
2755
                ret();
2756
        end
2757
 
2758
//-----------------------------------------------------------------------------
2759
//-----------------------------------------------------------------------------
2760
STORE_IN_DEST:
2761
        begin
2762
//              state <= IFETCH;        // In event of bad ir
2763
//              ret();
2764
                resL <= s;
2765
                resW <= s[15:0];
2766
                resB <= s[7:0];
2767
                d <= s;
2768
                case(ir[15:12])
2769
                4'd1:   begin zf <= s[ 7:0]== 8'h00; nf <= s[7]; end
2770
                4'd3:   begin zf <= s[15:0]==16'h00; nf <= s[15]; end
2771
                4'd2:   begin zf <= s[31:0]==32'd0;  nf <= s[31]; end
2772
                default:        ;
2773
                endcase
2774
                cf <= 1'b0;
2775
                vf <= 1'b0;
2776
                case(ir[15:12])
2777
                4'd1:   fs_data(MMM,RRR,STORE_BYTE,D);
2778
                4'd2:   fs_data(MMM,RRR,STORE_LWORD,D);
2779
                4'd3:   fs_data(MMM,RRR,STORE_WORD,D);
2780
                default:        ;       // cant get here
2781
                endcase
2782
        end
2783
 
2784
 
2785
//-----------------------------------------------------------------------------
2786
// Compares
2787
//-----------------------------------------------------------------------------
2788
CMP:
2789
        begin
2790
                flag_update <= FU_CMP;
2791
                case(sz)
2792
                2'b00:  resB <= d[ 7:0] - s[ 7:0];
2793
                2'b01:  resW <= d[15:0] - s[15:0];
2794
                2'b10:  resL <= d[31:0] - s[31:0];
2795
                2'b11:  ;
2796
                endcase
2797
                ret();
2798
        end
2799
 
2800
CMPA:
2801
        begin
2802
                flag_update <= FU_CMP;
2803
                case(ir[8])
2804
                1'b0:   resL <= d[31:0] - {{16{s[15]}},s[15:0]};
2805
                1'b1:   resL <= d[31:0] - s[31:0];
2806
                endcase
2807
                ret();
2808
        end
2809
 
2810
CMPM:
2811
        begin
2812
                push (CMP);
2813
                case(sz)
2814
                2'd0:   fs_data(3'b011,RRR,FETCH_BYTE,D);
2815
                2'd1:   fs_data(3'b011,RRR,FETCH_WORD,D);
2816
                2'd2:   fs_data(3'b011,RRR,FETCH_LWORD,D);
2817
                default:        ;       // cant get here
2818
                endcase
2819
        end
2820
 
2821
//-----------------------------------------------------------------------------
2822
// Shifts
2823
// Rotate instructions ROL,ROR do not affect the X flag.
2824
//-----------------------------------------------------------------------------
2825
SHIFT1:
2826
        begin
2827
                vf <= 1'b0;
2828
                case(shift_op)
2829
                3'b010, // ROXL, ROXR
2830
                3'b110: cf <= xf;
2831
                default:
2832
                        begin
2833
                                if (cnt=='d0)
2834
                                        cf <= 1'b0;
2835
                        end
2836
                endcase
2837
                // Extend by a bit for ASL overflow detection.
2838
                resB <= {d[7],d[7:0]};
2839
                resW <= {d[15],d[15:0]};
2840
                resL <= {d[31],d[31:0]};
2841
                state <= SHIFT;
2842
        end
2843
SHIFT:
2844
        if (cnt!='d0) begin
2845
                cnt <= cnt - 2'd1;
2846
                case(shift_op)
2847
                3'b000: // ASR
2848
                        case(sz)
2849
                        2'b00:  begin resB <= {resB[ 7],resB[ 7:1]}; cf <= resB[0]; xf <= resB[0]; end
2850
                        2'b01:  begin resW <= {resW[15],resW[15:1]}; cf <= resW[0]; xf <= resW[0]; end
2851
                        2'b10:  begin resL <= {resL[31],resL[31:1]}; cf <= resL[0]; xf <= resL[0]; end
2852
                        2'b11:  begin resW <= {resW[15],resW[15:1]}; cf <= resW[0]; xf <= resW[0]; end
2853
                        endcase
2854
                3'b001: // LSR
2855
                        case(sz)
2856
                        2'b00:  begin resB <= {1'b0,resB[ 7:1]}; cf <= resB[0]; xf <= resB[0]; end
2857
                        2'b01:  begin resW <= {1'b0,resW[15:1]}; cf <= resW[0]; xf <= resW[0]; end
2858
                        2'b10:  begin resL <= {1'b0,resL[31:1]}; cf <= resL[0]; xf <= resL[0]; end
2859
                        2'b11:  begin resW <= {1'b0,resW[15:1]}; cf <= resW[0]; xf <= resW[0]; end
2860
                        endcase
2861
                3'b010: // ROXR
2862
                        case(sz)
2863
                        2'b00:  begin resB <= {xf,resB[ 7:1]}; cf <= resB[0]; xf <= resB[0]; end
2864
                        2'b01:  begin resW <= {xf,resW[15:1]}; cf <= resW[0]; xf <= resW[0]; end
2865
                        2'b10:  begin resL <= {xf,resL[31:1]}; cf <= resL[0]; xf <= resL[0]; end
2866
                        2'b11:  begin resW <= {xf,resW[15:1]}; cf <= resW[0]; xf <= resW[0]; end
2867
                        endcase
2868
                3'b011: // ROR
2869
                        case(sz)
2870
                        2'b00:  begin resB <= {resB[0],resB[ 7:1]}; cf <= resB[0]; end
2871
                        2'b01:  begin resW <= {resW[0],resW[15:1]}; cf <= resW[0]; end
2872
                        2'b10:  begin resL <= {resL[0],resL[31:1]}; cf <= resL[0]; end
2873
                        2'b11:  begin resW <= {resW[0],resW[15:1]}; cf <= resW[0]; end
2874
                        endcase
2875
                3'b100: // ASL
2876
                        case(sz)
2877
                        2'b00:  begin resB <= {resB[ 7:0],1'b0}; cf <= resB[ 7]; xf <= resB[ 7]; if (resB[ 7] != resB[ 8]) vf <= 1'b1; end
2878
                        2'b01:  begin resW <= {resW[15:0],1'b0}; cf <= resW[15]; xf <= resW[15]; if (resW[15] != resW[16]) vf <= 1'b1; end
2879
                        2'b10:  begin resL <= {resL[31:0],1'b0}; cf <= resL[31]; xf <= resL[31]; if (resL[31] != resL[32]) vf <= 1'b1; end
2880
                        2'b11:  begin resW <= {resW[15:0],1'b0}; cf <= resW[15]; xf <= resW[15]; if (resW[15] != resW[16]) vf <= 1'b1; end
2881
                        endcase
2882
                3'b101: // LSL
2883
                        case(sz)
2884
                        2'b00:  begin resB <= {resB[ 6:0],1'b0}; cf <= resB[ 7]; xf <= resB[ 7]; end
2885
                        2'b01:  begin resW <= {resW[14:0],1'b0}; cf <= resW[15]; xf <= resW[15]; end
2886
                        2'b10:  begin resL <= {resL[30:0],1'b0}; cf <= resL[31]; xf <= resL[31]; end
2887
                        2'b11:  begin resW <= {resW[14:0],1'b0}; cf <= resW[15]; xf <= resW[15]; end
2888
                        endcase
2889
                3'b110: // ROXL
2890
                        case(sz)
2891
                        2'b00:  begin resB <= {resB[ 6:0],xf}; cf <= resB[ 7]; xf <= resB[ 7]; end
2892
                        2'b01:  begin resW <= {resW[14:0],xf}; cf <= resW[15]; xf <= resW[15]; end
2893
                        2'b10:  begin resL <= {resL[30:0],xf}; cf <= resL[31]; xf <= resL[31]; end
2894
                        2'b11:  begin resW <= {resW[14:0],xf}; cf <= resW[15]; xf <= resW[15]; end
2895
                        endcase
2896
                3'b111: // ROL
2897
                        case(sz)
2898
                        2'b00:  begin resB <= {resB[ 6:0],resB[ 7]}; cf <= resB[ 7]; end
2899
                        2'b01:  begin resW <= {resW[14:0],resW[15]}; cf <= resW[15]; end
2900
                        2'b10:  begin resL <= {resL[30:0],resL[31]}; cf <= resL[31]; end
2901
                        2'b11:  begin resW <= {resW[14:0],resW[15]}; cf <= resW[15]; end
2902
                        endcase
2903
                endcase
2904
        end
2905
        else begin
2906
                if (shift_op==3'b100)   // ASL
2907
                        case(sz)
2908
                        2'b00:  if (resB[ 7] != resB[ 8]) vf <= 1'b1;
2909
                        2'b01:  if (resW[15] != resW[16]) vf <= 1'b1;
2910
                        2'b10:  if (resL[31] != resL[32]) vf <= 1'b1;
2911
                        2'b11:  if (resW[15] != resW[16]) vf <= 1'b1;
2912
                        /*
2913
                        2'b00:  vf <= resB[ 7] != d[ 7];
2914
                        2'b01:  vf <= resW[15] != d[15];
2915
                        2'b10:  vf <= resL[31] != d[31];
2916
                        2'b11:  vf <= resW[15] != d[15];
2917
                        */
2918
                        endcase
2919
                case(sz)
2920
                2'b00:  d <= resB;
2921
                2'b01:  d <= resW;
2922
                2'b10:  d <= resL;
2923
                2'b11:  d <= resW;
2924
                endcase
2925
                Rt <= {1'b0,rrr};
2926
                case(sz)
2927
                2'b00:  begin zf <= resB[7:0]== 8'h00; nf <= resB[ 7]; end
2928
                2'b01:  begin zf <= resW[15:0]==16'h00; nf <= resW[15]; end
2929
                2'b10:  begin zf <= resL[31:0]==32'h00; nf <= resL[31]; end
2930
                2'b11:  begin zf <= resW[15:0]==16'h00; nf <= resW[15]; end
2931
                endcase
2932
                case(sz)
2933
                2'b00:  begin rfwrB <= 1'b1; ret(); end
2934
                2'b01:  begin rfwrW <= 1'b1; ret(); end
2935
                2'b10:  begin rfwrL <= 1'b1; ret(); end
2936
                2'b11:  fs_data(mmm,rrr,STORE_WORD,D);  // word operations only if memory operate
2937
                endcase
2938
        end
2939
 
2940
//-----------------------------------------------------------------------------
2941
// ADD / SUB / ADDA / SUBA / ADDX / SUBX
2942
//-----------------------------------------------------------------------------
2943
ADD:
2944
        begin
2945
                flag_update <= FU_ADD;
2946
                if (sz==2'b11) begin
2947
                        Rt <= {1'b1,AAA};
2948
                        if (ir[8]) begin
2949
                                rfwrL <= 1'b1;
2950
                                resL <= d + s;
2951
                        end
2952
                        else begin
2953
                                resW <= d[15:0] + s[15:0];
2954
                                rfwrW <= 1'b1;
2955
                        end
2956
                        d <= d + s;
2957
                        dd <= d;
2958
                        ret();
2959
                end
2960
                else if (ir[8]) begin
2961
                        resB <= d[7:0] + s[7:0];
2962
                        resW <= d[15:0] + s[15:0];
2963
                        resL <= d + s;
2964
                        d <= d + s;
2965
                        dd <= d;
2966
                        if (mmm==3'd0 || mmm==3'd1) begin
2967
                                Rt <= {mmm[0],rrr};
2968
                                case(sz)
2969
                                2'b00:  rfwrB <= 1'b1;
2970
                                2'b01:  rfwrW <= 1'b1;
2971
                                2'b10:  rfwrL <= 1'b1;
2972
                                default:        ;
2973
                                endcase
2974
                                ret();
2975
                        end
2976
                        else begin
2977
                                case(sz)
2978
                                2'b00:  goto(STORE_BYTE);
2979
                                2'b01:  goto(STORE_WORD);
2980
                                2'b10:  goto(STORE_LWORD);
2981
                                default:        ;
2982
                                endcase
2983
                        end
2984
                end
2985
                else begin
2986
                        Rt <= {1'b0,DDD};
2987
                        resB <= d[7:0] + s[7:0];
2988
                        resW <= d[15:0] + s[15:0];
2989
                        resL <= d + s;
2990
                        d <= d + s;
2991
                        dd <= d;
2992
                        case(sz)
2993
                        2'b00:  rfwrB <= 1'b1;
2994
                        2'b01:  rfwrW <= 1'b1;
2995
                        2'b10:  rfwrL <= 1'b1;
2996
                        default:        ;
2997
                        endcase
2998
                        ret();
2999
                end
3000
        end
3001
 
3002
//-----------------------------------------------------------------------------
3003
//-----------------------------------------------------------------------------
3004
SUB:
3005
        begin
3006
                flag_update <= FU_SUB;
3007
                if (sz==2'b11) begin
3008
                        Rt <= {1'b1,AAA};
3009
                        if (ir[8]) begin
3010
                                rfwrL <= 1'b1;
3011
                                resL <= d - s;
3012
                        end
3013
                        else begin
3014
                                resW <= d[15:0] - s[15:0];
3015
                                rfwrW <= 1'b1;
3016
                        end
3017
                        d <= d - s;
3018
                        dd <= d;
3019
                        ret();
3020
                end
3021
                else if (ir[8]) begin
3022
                        resB <= d[7:0] - s[7:0];
3023
                        resW <= d[15:0] - s[15:0];
3024
                        resL <= d - s;
3025
                        d <= d - s;
3026
                        dd <= d;
3027
                        if (mmm==3'd0 || mmm==3'd1) begin
3028
                                Rt <= {mmm[0],rrr};
3029
                                case(sz)
3030
                                2'b00:  rfwrB <= 1'b1;
3031
                                2'b01:  rfwrW <= 1'b1;
3032
                                2'b10:  rfwrL <= 1'b1;
3033
                                default:        ;
3034
                                endcase
3035
                                ret();
3036
                        end
3037
                        else begin
3038
                                case(sz)
3039
                                2'b00:  goto(STORE_BYTE);
3040
                                2'b01:  goto(STORE_WORD);
3041
                                2'b10:  goto(STORE_LWORD);
3042
                                default:        ;
3043
                                endcase
3044
                        end
3045
                end
3046
                else begin
3047
                        Rt <= {1'b0,DDD};
3048
                        resB <= d[7:0] - s[7:0];
3049
                        resW <= d[15:0] - s[15:0];
3050
                        resL <= d - s;
3051
                        dd <= d;
3052
                        case(sz)
3053
                        2'b00:  rfwrB <= 1'b1;
3054
                        2'b01:  rfwrW <= 1'b1;
3055
                        2'b10:  rfwrL <= 1'b1;
3056
                        default:        ;
3057
                        endcase
3058
                        ret();
3059
                end
3060
        end
3061
 
3062
ADDX:
3063
        begin
3064
                push (ADDX2);
3065
                case(sz)
3066
                2'd0:   fs_data(3'b100,rrr,FETCH_BYTE,S);
3067
                2'd1:   fs_data(3'b100,rrr,FETCH_WORD,S);
3068
                2'd2:   fs_data(3'b100,rrr,FETCH_LWORD,S);
3069
                default:        ;
3070
                endcase
3071
        end
3072
ADDX2:
3073
        begin
3074
                push(ADDX3);
3075
                case(sz)
3076
                2'd0:   fs_data(3'b100,RRR,FETCH_BYTE,D);
3077
                2'd1:   fs_data(3'b100,RRR,FETCH_WORD,D);
3078
                2'd2:   fs_data(3'b100,RRR,FETCH_LWORD,D);
3079
                default:        ;
3080
                endcase
3081
        end
3082
ADDX3:
3083
        begin
3084
                flag_update <= FU_ADDX;
3085
                resB <= d[ 7:0] + s[ 7:0] + xf;
3086
                resW <= d[15:0] + s[15:0] + xf;
3087
                resL <= d[31:0] + s[31:0] + xf;
3088
                dd <= d;
3089
                d <= d + s + xf;
3090
                if (ir[3])
3091
                        case(sz)
3092
                        2'b00:  goto(STORE_BYTE);
3093
                        2'b01:  goto(STORE_WORD);
3094
                        2'b10:  goto(STORE_LWORD);
3095
                        default:        ;
3096
                        endcase
3097
                else begin
3098
                        Rt <= {1'b0,RRR};
3099
                        case(sz)
3100
                        2'd0:   rfwrB <= 1'b1;
3101
                        2'd1:   rfwrW <= 1'b1;
3102
                        2'd2:   rfwrL <= 1'b1;
3103
                        default:        ;
3104
                        endcase
3105
                        ret();
3106
                end
3107
        end
3108
 
3109
SUBX:
3110
        begin
3111
                push (SUBX2);
3112
                case(sz)
3113
                2'd0:   fs_data(3'b100,rrr,FETCH_BYTE,S);
3114
                2'd1:   fs_data(3'b100,rrr,FETCH_WORD,S);
3115
                2'd2:   fs_data(3'b100,rrr,FETCH_LWORD,S);
3116
                default:        ;
3117
                endcase
3118
        end
3119
SUBX2:
3120
        begin
3121
                push(SUBX3);
3122
                case(sz)
3123
                2'd0:   fs_data(3'b100,RRR,FETCH_BYTE,D);
3124
                2'd1:   fs_data(3'b100,RRR,FETCH_WORD,D);
3125
                2'd2:   fs_data(3'b100,RRR,FETCH_LWORD,D);
3126
                default:        ;
3127
                endcase
3128
        end
3129
SUBX3:
3130
        begin
3131
                flag_update <= FU_SUBX;
3132
                resB <= d[7:0] - s[7:0] - xf;
3133
                resW <= d[15:0] - s[15:0] - xf;
3134
                resL <= d[31:0] - s[31:0] - xf;
3135
                dd <= d;
3136
                d <= d - s - xf;
3137
                if (ir[3])
3138
                        case(sz)
3139
                        2'b00:  goto(STORE_BYTE);
3140
                        2'b01:  goto(STORE_WORD);
3141
                        2'b10:  goto(STORE_LWORD);
3142
                        default:        ;
3143
                        endcase
3144
                else begin
3145
                        Rt <= {1'b0,RRR};
3146
                        case(sz)
3147
                        2'd0:   rfwrB <= 1'b1;
3148
                        2'd1:   rfwrW <= 1'b1;
3149
                        2'd2:   rfwrL <= 1'b1;
3150
                        default:        ;
3151
                        endcase
3152
                        ret();
3153
                end
3154
        end
3155
 
3156
//-----------------------------------------------------------------------------
3157
//-----------------------------------------------------------------------------
3158
AND:
3159
        begin
3160
                flag_update <= FU_LOGIC;
3161
                if (ir[8]) begin
3162
                        resB <= d[7:0] & rfoDn[7:0];
3163
                        resW <= d[15:0] & rfoDn[15:0];
3164
                        resL <= d & rfoDn;
3165
                        d <= d & rfoDn;
3166
                        if (mmm==3'd0 || mmm==3'd1) begin
3167
                                Rt <= {mmm[0],rrr};
3168
                                case(sz)
3169
                                2'b00:  rfwrB <= 1'b1;
3170
                                2'b01:  rfwrW <= 1'b1;
3171
                                2'b10:  rfwrL <= 1'b1;
3172
                                default:        ;
3173
                                endcase
3174
                                ret();
3175
                        end
3176
                        else begin
3177
                                case(sz)
3178
                                2'b00:  goto(STORE_BYTE);
3179
                                2'b01:  goto(STORE_WORD);
3180
                                2'b10:  goto(STORE_LWORD);
3181
                                default:        ;
3182
                                endcase
3183
                        end
3184
                end
3185
                else begin
3186
                        Rt <= {1'b0,DDD};
3187
                        resB <= rfoDn[7:0] & s[7:0];
3188
                        resW <= rfoDn[15:0] & s[15:0];
3189
                        resL <= rfoDn & s;
3190
                        case(sz)
3191
                        2'b00:  rfwrB <= 1'b1;
3192
                        2'b01:  rfwrW <= 1'b1;
3193
                        2'b10:  rfwrL <= 1'b1;
3194
                        default:        ;
3195
                        endcase
3196
                        ret();
3197
                end
3198
        end
3199
 
3200
//-----------------------------------------------------------------------------
3201
// OR
3202
//-----------------------------------------------------------------------------
3203
OR:
3204
        begin
3205
                flag_update <= FU_LOGIC;
3206
                if (ir[8]) begin
3207
                        resB <= d[7:0] | rfoDn[7:0];
3208
                        resW <= d[15:0] | rfoDn[15:0];
3209
                        resL <= d | rfoDn;
3210
                        d <= d | rfoDn;
3211
                        if (mmm==3'd0 || mmm==3'd1) begin
3212
                                Rt <= {mmm[0],rrr};
3213
                                case(sz)
3214
                                2'b00:  rfwrB <= 1'b1;
3215
                                2'b01:  rfwrW <= 1'b1;
3216
                                2'b10:  rfwrL <= 1'b1;
3217
                                default:        ;       // DIV
3218
                                endcase
3219
                                ret();
3220
                        end
3221
                        else begin
3222
                                case(sz)
3223
                                2'b00:  goto(STORE_BYTE);
3224
                                2'b01:  goto(STORE_WORD);
3225
                                2'b10:  goto(STORE_LWORD);
3226
                                default:        ;       // DIV
3227
                                endcase
3228
                        end
3229
                end
3230
                else begin
3231
                        Rt <= {1'b0,DDD};
3232
                        resB <= rfoDn[7:0] | s[7:0];
3233
                        resW <= rfoDn[15:0] | s[15:0];
3234
                        resL <= rfoDn | s;
3235
                        case(sz)
3236
                        2'b00:  rfwrB <= 1'b1;
3237
                        2'b01:  rfwrW <= 1'b1;
3238
                        2'b10:  rfwrL <= 1'b1;
3239
                        default:        ;
3240
                        endcase
3241
                        ret();
3242
                end
3243
        end
3244
 
3245
//-----------------------------------------------------------------------------
3246
// EOR
3247
//-----------------------------------------------------------------------------
3248
EOR:
3249
        begin
3250
                flag_update <= FU_LOGIC;
3251
                resB <= d[7:0] ^ rfoDn[7:0];
3252
                resW <= d[15:0] ^ rfoDn[15:0];
3253
                resL <= d ^ rfoDn;
3254
                d <= d ^ rfoDn;
3255
                if (mmm[2:1]==2'd0) begin
3256
                        Rt <= {mmm[0],rrr};
3257
                        case(sz)
3258
                        2'b00:  rfwrB <= 1'b1;
3259
                        2'b01:  rfwrW <= 1'b1;
3260
                        2'b10:  rfwrL <= 1'b1;
3261
                        default:        ;
3262
                        endcase
3263
                        ret();
3264
                end
3265
                else begin
3266
                        case(sz)
3267
                        2'b00:  goto(STORE_BYTE);
3268
                        2'b01:  goto(STORE_WORD);
3269
                        2'b10:  goto(STORE_LWORD);
3270
                        default:        ;
3271
                        endcase
3272
                end
3273
        end
3274
 
3275
//-----------------------------------------------------------------------------
3276
// ADDQ / SUBQ
3277
// Flags are not updated if the target is an address register.
3278
// If the target is an address register, the entire register is updated.
3279
//-----------------------------------------------------------------------------
3280
ADDQ:
3281
        begin
3282
                if (ir[8]) begin
3283
                        if (mmm!=3'b001)
3284
                                flag_update <= FU_SUBQ;
3285
                        resL <= d - immx;
3286
                        resB <= d[7:0] - immx[7:0];
3287
                        resW <= d[15:0] - immx[15:0];
3288
                        d <= d - immx;
3289
                        dd <= d;
3290
                        s <= immx;
3291
                end
3292
                else begin
3293
                        if (mmm!=3'b001)
3294
                                flag_update <= FU_ADDQ;
3295
                        resL <= d + immx;
3296
                        resB <= d[7:0] + immx[7:0];
3297
                        resW <= d[15:0] + immx[15:0];
3298
                        d <= d + immx;
3299
                        dd <= d;
3300
                        s <= immx;
3301
                end
3302
                if (mmm==3'd0) begin
3303
                        ret();
3304
                        Rt <= {mmm[0],rrr};
3305
                        case(sz)
3306
                        2'b00:  rfwrB <= 1'b1;
3307
                        2'b01:  rfwrW <= 1'b1;
3308
                        2'b10:  rfwrL <= 1'b1;
3309
                        default:        ;
3310
                        endcase
3311
                end
3312
                // If the target is an address register, the entire register is updated.
3313
                else if (mmm==3'b001) begin
3314
                        ret();
3315
                        Rt <= {mmm[0],rrr};
3316
                        rfwrL <= 1'b1;
3317
                end
3318
                else
3319
                        case(sz)
3320
                        2'b00:  goto(STORE_BYTE);
3321
                        2'b01:  goto(STORE_WORD);
3322
                        2'b10:  goto(STORE_LWORD);
3323
                        default:        ;       // Scc / DBRA
3324
                        endcase
3325
        end
3326
 
3327
//-----------------------------------------------------------------------------
3328
// ADDI / SUBI / CMPI / ANDI / ORI / EORI
3329
//-----------------------------------------------------------------------------
3330
ADDI:
3331
        case(sz)
3332
        2'b00:  call(FETCH_IMM8,ADDI2);
3333
        2'b01:  call(FETCH_IMM16,ADDI2);
3334
        2'b10:  call(FETCH_IMM32,ADDI2);
3335
        default:        tIllegal();
3336
        endcase
3337
ADDI2:
3338
        begin
3339
        immx <= imm;
3340
        case(sz)
3341
        2'b00:  begin push(ADDI3); fs_data(mmm,rrr,FETCH_BYTE,D); end
3342
        2'b01:  begin push(ADDI3); fs_data(mmm,rrr,FETCH_WORD,D); end
3343
        2'b10:  begin push(ADDI3); fs_data(mmm,rrr,FETCH_LWORD,D); end
3344
        default:        ;       // Cant get here
3345
        endcase
3346
        end
3347
ADDI3:
3348
        begin
3349
                flag_update <= FU_ADDI;
3350
                dd <= d;
3351
                s <= immx;
3352
                // Odd numbers are BIT insns.
3353
                case(ir[11:8])
3354
                4'h0:   resL <= d | immx;       // ORI
3355
                4'h2:   resL <= d & immx;     // ANDI
3356
                4'h4:   resL <= d - immx;       // SUBI
3357
                4'h6:   resL <= d + immx;       // ADDI
3358
                4'hA:   resL <= d ^ immx;       // EORI
3359
                4'hC:   resL <= d - immx;       // CMPI
3360
                default:        ;
3361
                endcase
3362
                case(ir[11:8])
3363
                4'h0:   resW <= d[15:0] | immx[15:0];   // ORI
3364
                4'h2:   resW <= d[15:0] & immx[15:0];       // ANDI
3365
                4'h4:   resW <= d[15:0] - immx[15:0];   // SUBI
3366
                4'h6:   resW <= d[15:0] + immx[15:0];   // ADDI
3367
                4'hA:   resW <= d[15:0] ^ immx[15:0];   // EORI
3368
                4'hC:   resW <= d[15:0] - immx[15:0];   // CMPI
3369
                default:        ;
3370
                endcase
3371
                case(ir[11:8])
3372
                4'h0:   resB <= d[7:0] | immx[7:0];     // ORI
3373
                4'h2:   resB <= d[7:0] & immx[7:0];        // ANDI
3374
                4'h4:   resB <= d[7:0] - immx[7:0];     // SUBI
3375
                4'h6:   resB <= d[7:0] + immx[7:0];     // ADDI
3376
                4'hA:   resB <= d[7:0] ^ immx[7:0];     // EORI
3377
                4'hC:   resB <= d[7:0] - immx[7:0];     // CMPI
3378
                default:        ;
3379
                endcase
3380
                case(ir[11:8])
3381
                4'h0:   d <= d | immx;  // ORI
3382
                4'h2:   d <= d & immx;        // ANDI
3383
                4'h4:   d <= d - immx;  // SUBI
3384
                4'h6:   d <= d + immx;  // ADDI
3385
                4'hA:   d <= d ^ immx;  // EORI
3386
                4'hC:   d <= d - immx;  // CMPI
3387
                default:        ;
3388
                endcase
3389
                if (ir[11:8]==4'hC)
3390
                        ret();
3391
                else if (mmm==3'b000 || mmm==3'b001) begin
3392
                        case(sz)
3393
                        2'b00:  rfwrB <= 1'b1;
3394
                        2'b01:  rfwrW <= 1'b1;
3395
                        2'b10:  rfwrL <= 1'b1;
3396
                        default:        ;
3397
                        endcase
3398
                        Rt <= {mmm[0],rrr};
3399
                        ret();
3400
                end
3401
                else
3402
                        case(sz)
3403
                        2'b00:  goto(STORE_BYTE);
3404
                        2'b01:  goto(STORE_WORD);
3405
                        2'b10:  goto(STORE_LWORD);
3406
                        default:        ret();
3407
                        endcase
3408
        end
3409
 
3410
//-----------------------------------------------------------------------------
3411
// ANDI_CCR / ANDI_SR / EORI_CCR / EORI_SR / ORI_CCR / ORI_SR
3412
//-----------------------------------------------------------------------------
3413
//
3414
ANDI_CCR:
3415
        begin flag_update <= FU_ANDI_CCR; goto(FETCH_IMM8); end
3416
ANDI_SR:
3417
        begin flag_update <= FU_ANDI_SR; goto(FETCH_IMM16); end
3418
ANDI_SRX:
3419
        begin flag_update <= FU_ANDI_SRX; goto(FETCH_IMM32); end
3420
EORI_CCR:
3421
        begin flag_update <= FU_EORI_CCR; goto(FETCH_IMM8); end
3422
EORI_SR:
3423
        begin flag_update <= FU_EORI_SR; goto(FETCH_IMM16); end
3424
EORI_SRX:
3425
        begin flag_update <= FU_EORI_SRX; goto(FETCH_IMM32); end
3426
ORI_CCR:
3427
        begin flag_update <= FU_ORI_CCR; goto(FETCH_IMM8); end
3428
ORI_SR:
3429
        begin flag_update <= FU_ORI_SR; goto(FETCH_IMM16); end
3430
ORI_SRX:
3431
        begin flag_update <= FU_ORI_SRX; goto(FETCH_IMM32); end
3432
 
3433
//-----------------------------------------------------------------------------
3434
// Bit manipulation
3435
//-----------------------------------------------------------------------------
3436
BIT:
3437
        begin
3438
                mmm_save <= mmm;
3439
                if (ir[11:8]==4'h8) begin
3440
                        call(FETCH_IMM16,BIT1);
3441
                end
3442
                else begin
3443
                        imm <= rfoDn;
3444
                        goto(BIT1);
3445
                end
3446
        end
3447
BIT1:
3448
        begin
3449
                bit2test <= imm;
3450
                if (mmm_save==3'b000) begin     // Dn
3451
                        goto(BIT2);
3452
                        d <= rfob;
3453
                end
3454
                else begin
3455
                        push(BIT2);
3456
                        // This might fetch an immediate
3457
                        // might also alter mmm
3458
                        fs_data(mmm,rrr,FETCH_BYTE,D);
3459
                end
3460
        end
3461
// ToDo: Speed this up by a clock cycle by placing the update in IFETCH.
3462
BIT2:
3463
        begin
3464
                // Targets a data register then the size is 32-bit, test is mod 32.
3465
                if (mmm_save==3'b000)
3466
                        case(sz)
3467
                        2'b00:  // BTST
3468
                                begin
3469
`ifdef SUPPORT_BITPAIRS
3470
                                        if (bit2test[7]) begin
3471
                                                zf <= (d >> {bit2test[3:0],1'b0} & 4'd3) == 2'b00;
3472
                                                cf <= (d >> {bit2test[3:0],1'b0} & 4'd3) == 2'b01;
3473
                                                nf <= (d >> {bit2test[3:0],1'b0} & 4'd3) == 2'b10;
3474
                                                vf <= (d >> {bit2test[3:0],1'b0} & 4'd3) == 2'b11;
3475
                                        end
3476
                                        else
3477
`endif
3478
                                                zf <= ~d[bit2test[4:0]];
3479
                                        ret();
3480
                                end
3481
                        2'b01:  // BCHG
3482
                                begin
3483
`ifdef SUPPORT_BITPAIRS
3484
                                        if (bit2test[7]) begin
3485
                                                zf <= (d >> {bit2test[3:0],1'b0} & 4'd3) == 2'b00;
3486
                                                cf <= (d >> {bit2test[3:0],1'b0} & 4'd3) == 2'b01;
3487
                                                nf <= (d >> {bit2test[3:0],1'b0} & 4'd3) == 2'b10;
3488
                                                vf <= (d >> {bit2test[3:0],1'b0} & 4'd3) == 2'b11;
3489
                                                resL <= d ^ (32'd3 << {bit2test[3:0],1'b0});
3490
                                        end
3491
                                        else
3492
`endif
3493
                                        begin
3494
                                                zf <= ~d[bit2test[4:0]];
3495
                                                resL <= d ^  (32'd1 << bit2test[4:0]);
3496
                                        end
3497
                                        rfwrL <= 1'b1;
3498
                                        Rt <= {1'b0,rrr};
3499
                                        ret();
3500
                                end
3501
                        2'b10:  // BCLR
3502
                                begin
3503
`ifdef SUPPORT_BITPAIRS
3504
                                        if (bit2test[7]) begin
3505
                                                zf <= (d >> {bit2test[3:0],1'b0} & 4'd3) == 2'b00;
3506
                                                cf <= (d >> {bit2test[3:0],1'b0} & 4'd3) == 2'b01;
3507
                                                nf <= (d >> {bit2test[3:0],1'b0} & 4'd3) == 2'b10;
3508
                                                vf <= (d >> {bit2test[3:0],1'b0} & 4'd3) == 2'b11;
3509
                                                resL <= d & ~(32'd3 << {bit2test[3:0],1'b0});
3510
                                        end
3511
                                        else
3512
`endif
3513
                                        begin
3514
                                                zf <= ~d[bit2test[4:0]];
3515
                                                resL <= d & ~(32'd1 << bit2test[4:0]);
3516
                                        end
3517
                                        rfwrL <= 1'b1;
3518
                                        Rt <= {1'b0,rrr};
3519
                                        ret();
3520
                                end
3521
                        2'b11:  // BSET
3522
                                begin
3523
`ifdef SUPPORT_BITPAIRS
3524
                                        if (bit2test[7]) begin
3525
                                                zf <= (d >> {bit2test[3:0],1'b0} & 4'd3) == 2'b00;
3526
                                                cf <= (d >> {bit2test[3:0],1'b0} & 4'd3) == 2'b01;
3527
                                                nf <= (d >> {bit2test[3:0],1'b0} & 4'd3) == 2'b10;
3528
                                                vf <= (d >> {bit2test[3:0],1'b0} & 4'd3) == 2'b11;
3529
                                                resL <= (d & ~(32'd3 << {bit2test[3:0],1'b0})) | (bit2test[5:4] << {bit2test[3:0],1'b0});
3530
                                        end
3531
                                        else
3532
`endif
3533
                                        begin
3534
                                                zf <= ~d[bit2test[4:0]];
3535
                                                resL <= d |  (32'd1 << bit2test[4:0]);
3536
                                        end
3537
                                        rfwrL <= 1'b1;
3538
                                        Rt <= {1'b0,rrr};
3539
                                        ret();
3540
                                end
3541
                        endcase
3542
                // Target is memory, size is byte, test is mod 8.
3543
                else
3544
                        case(sz)
3545
                        2'b00:  // BTST
3546
                                begin
3547
`ifdef SUPPORT_BITPAIRS
3548
                                        if (bit2test[7]) begin
3549
                                                zf <= (d >> {bit2test[1:0],1'b0} & 4'd3) == 2'b00;
3550
                                                cf <= (d >> {bit2test[1:0],1'b0} & 4'd3) == 2'b01;
3551
                                                nf <= (d >> {bit2test[1:0],1'b0} & 4'd3) == 2'b10;
3552
                                                vf <= (d >> {bit2test[1:0],1'b0} & 4'd3) == 2'b11;
3553
                                        end
3554
                                        else
3555
`endif
3556
                                                zf <= ~d[bit2test[2:0]];
3557
                                        ret();
3558
                                end
3559
                        2'b01:  // BCHG
3560
                                begin
3561
`ifdef SUPPORT_BITPAIRS
3562
                                        if (bit2test[7]) begin
3563
                                                zf <= (d >> {bit2test[1:0],1'b0} & 4'd3) == 2'b00;
3564
                                                cf <= (d >> {bit2test[1:0],1'b0} & 4'd3) == 2'b01;
3565
                                                nf <= (d >> {bit2test[1:0],1'b0} & 4'd3) == 2'b10;
3566
                                                vf <= (d >> {bit2test[1:0],1'b0} & 4'd3) == 2'b11;
3567
                                                d <= d ^ (32'd3 << {bit2test[1:0],1'b0});
3568
                                        end
3569
                                        else
3570
`endif
3571
                                        begin
3572
                                                zf <= ~d[bit2test[2:0]];
3573
                                                d <= d ^  (32'd1 << bit2test[2:0]);
3574
                                        end
3575
                                        goto(STORE_BYTE);
3576
                                end
3577
                        2'b10:  // BCLR
3578
                                begin
3579
`ifdef SUPPORT_BITPAIRS
3580
                                        if (bit2test[7]) begin
3581
                                                zf <= (d >> {bit2test[1:0],1'b0} & 4'd3) == 2'b00;
3582
                                                cf <= (d >> {bit2test[1:0],1'b0} & 4'd3) == 2'b01;
3583
                                                nf <= (d >> {bit2test[1:0],1'b0} & 4'd3) == 2'b10;
3584
                                                vf <= (d >> {bit2test[1:0],1'b0} & 4'd3) == 2'b11;
3585
                                                d <= d & ~(32'd3 << {bit2test[1:0],1'b0});
3586
                                        end
3587
                                        else
3588
`endif
3589
                                        begin
3590
                                                zf <= ~d[bit2test[2:0]];
3591
                                                d <= d & ~(32'd1 << bit2test[2:0]);
3592
                                        end
3593
                                        goto(STORE_BYTE);
3594
                                end
3595
                        2'b11:  // BSET
3596
                                begin
3597
`ifdef SUPPORT_BITPAIRS
3598
                                        if (bit2test[7]) begin
3599
                                                zf <= (d >> {bit2test[1:0],1'b0} & 4'd3) == 2'b00;
3600
                                                cf <= (d >> {bit2test[1:0],1'b0} & 4'd3) == 2'b01;
3601
                                                nf <= (d >> {bit2test[1:0],1'b0} & 4'd3) == 2'b10;
3602
                                                vf <= (d >> {bit2test[1:0],1'b0} & 4'd3) == 2'b11;
3603
                                                d <= (d & ~(32'd3 << {bit2test[1:0],1'b0})) | (bit2test[5:4] << {bit2test[1:0],1'b0});
3604
                                        end
3605
                                        else
3606
`endif
3607
                                        begin
3608
                                                zf <= ~d[bit2test[2:0]];
3609
                                                d <= d |  (32'd1 << bit2test[2:0]);
3610
                                        end
3611
                                        goto(STORE_BYTE);
3612
                                end
3613
                        endcase
3614
        end
3615
 
3616
//-----------------------------------------------------------------------------
3617
//-----------------------------------------------------------------------------
3618
CHK:
3619
        begin
3620
                if (d[15] || $signed(d[15:0]) > $signed(s[15:0])) begin
3621
                isr <= srx;
3622
                tf <= 1'b0;
3623
                sf <= 1'b1;
3624
                        vecno <= `CHK_VEC;
3625
            state <= TRAP3;
3626
                end
3627
                else
3628
                        ret();
3629
        end
3630
 
3631
//-----------------------------------------------------------------------------
3632
//-----------------------------------------------------------------------------
3633
FETCH_NOP_BYTE,FETCH_NOP_WORD,FETCH_NOP_LWORD:
3634
        ret();
3635
 
3636
FETCH_BRDISP:
3637
        begin
3638
/*
3639
                if (fnInCache(pc)) begin
3640
                        tFindInCache(pc,disp);
3641
                        goto (FETCH_BRDISP1);
3642
                end
3643
                else
3644
*/
3645
                if (!cyc_o) begin
3646
                        fc_o <= {sf,2'b10};
3647
                        cyc_o <= 1'b1;
3648
                        stb_o <= 1'b1;
3649
                        sel_o <= 4'b1111;
3650
                        adr_o <= pc;
3651
                end
3652
                else if (ack_i) begin
3653
                        cyc_o <= 1'b0;
3654
                        stb_o <= 1'b0;
3655
                        sel_o <= 4'b00;
3656
                        d <= {16'd0,iri};
3657
                        goto (FETCH_BRDISPa);
3658
                end
3659
        end
3660
FETCH_BRDISPa:
3661
        begin
3662
                // Record 'd' for bsr
3663
`ifdef SUPPORT_B24
3664
                if (ir[0]) begin
3665
                        d <= pc + {{9{ir[7]}},ir[7:1],d[15:0],1'b0};
3666
                        ea <= pc + {{9{ir[7]}},ir[7:1],d[15:0],1'b0};
3667
                end
3668
                else
3669
`endif
3670
                        d <= pc + {{16{d[15]}},d[15:0]};
3671
                        ea <= pc + {{16{d[15]}},d[15:0]};
3672
                // Want to point PC to return after displacement, it will be stacked
3673
                if (bsr)
3674
                        pc <= pc + 4'd2;
3675
                // else branch
3676
                else begin
3677
`ifdef SUPPORT_B24
3678
                        if (ir[0])
3679
                                pc <= pc + {{9{ir[7]}},ir[7:1],d[15:0],1'b0};
3680
                        else
3681
`endif
3682
                                pc <= pc + {{16{d[15]}},d[15:0]};
3683
                end
3684
                ret();
3685
        end
3686
 
3687
// Fetch 8 bit immediate
3688
//
3689
FETCH_IMM8:
3690
        if (!cyc_o) begin
3691
                fc_o <= {sf,2'b10};
3692
                cyc_o <= 1'b1;
3693
                stb_o <= 1'b1;
3694
                sel_o <= 4'b1111;
3695
                adr_o <= pc;
3696
        end
3697
        else if (ack_i) begin
3698
                cyc_o <= 1'b0;
3699
                stb_o <= 1'b0;
3700
                sel_o <= 4'b00;
3701
                imm <= {{24{iri[7]}},iri[7:0]};
3702
                if (ds==D)
3703
                        d <= {{24{iri[7]}},iri[7:0]};
3704
                else
3705
                        s <= {{24{iri[7]}},iri[7:0]};
3706
                goto (FETCH_IMM8a);
3707
        end
3708
FETCH_IMM8a:
3709
        begin
3710
                pc <= pc + 32'd2;
3711
                ret();
3712
        end
3713
 
3714
// Fetch 16 bit immediate
3715
//
3716
FETCH_IMM16:
3717
        if (!cyc_o) begin
3718
                fc_o <= {sf,2'b10};
3719
                cyc_o <= 1'b1;
3720
                stb_o <= 1'b1;
3721
                sel_o <= 4'b1111;
3722
                adr_o <= pc;
3723
        end
3724
        else if (ack_i) begin
3725
                cyc_o <= 1'b0;
3726
                stb_o <= 1'b0;
3727
                sel_o <= 4'b00;
3728
                imm <= {{16{iri[15]}},iri};
3729
                if (ds==D)
3730
                        d <= {{16{iri[15]}},iri};
3731
                else
3732
                        s <= {{16{iri[15]}},iri};
3733
                goto (FETCH_IMM16a);
3734
        end
3735
FETCH_IMM16a:
3736
        begin
3737
                pc <= pc + 32'd2;
3738
                ret();
3739
        end
3740
 
3741
// Fetch 32 bit immediate
3742
//
3743
FETCH_IMM32:
3744
        if (!cyc_o) begin
3745
                fc_o <= {sf,2'b10};
3746
                cyc_o <= 1'b1;
3747
                stb_o <= 1'b1;
3748
                sel_o <= 4'b1111;
3749
                adr_o <= pc;
3750
        end
3751
        else if (ack_i) begin
3752
                stb_o <= 1'b0;
3753
                sel_o <= 4'b00;
3754
                if (pc[1]) begin
3755
`ifdef BIG_ENDIAN
3756
                        imm[31:16] <= {dat_i[23:16],dat_i[31:24]};
3757
                        if (ds==D)
3758
                                d[31:16] <= {dat_i[23:16],dat_i[31:24]};
3759
                        else
3760
                                s[31:16] <= {dat_i[23:16],dat_i[31:24]};
3761
`else
3762
      imm[15:0] <= dat_i[31:16];
3763
      if (ds==D)
3764
        d[15:0] <= dat_i[31:16];
3765
        else
3766
        s[15:0] <= dat_i[31:16];
3767
`endif
3768
                  goto(FETCH_IMM32a);
3769
                end
3770
                else begin
3771
`ifdef BIG_ENDIAN
3772
                        imm <= rbo(dat_i);
3773
                        if (ds==D)
3774
                                d <= rbo(dat_i);
3775
                        else
3776
                                s <= rbo(dat_i);
3777
`else
3778
      imm <= dat_i;
3779
      if (ds==D)
3780
        d <= dat_i;
3781
      else
3782
        s <= dat_i;
3783
`endif
3784
                  cyc_o <= 1'b0;
3785
                  goto (FETCH_IMM32b);
3786
                end
3787
        end
3788
FETCH_IMM32a:
3789
        if (!stb_o) begin
3790
                stb_o <= 1'b1;
3791
                sel_o <= 4'b1111;
3792
                adr_o <= pc + 4'd2;
3793
        end
3794
        else if (ack_i) begin
3795
                cyc_o <= 1'b0;
3796
                stb_o <= 1'b0;
3797
                sel_o <= 4'b00;
3798
`ifdef BIG_ENDIAN
3799
                imm[15:0] <= {dat_i[7:0],dat_i[15:8]};
3800
                if (ds==D)
3801
                        d[15:0] <= {dat_i[7:0],dat_i[15:8]};
3802
                else
3803
                        s[15:0] <= {dat_i[7:0],dat_i[15:8]};
3804
`else
3805
                imm[31:16] <= dat_i[15:0];
3806
                if (ds==D)
3807
                        d[31:26] <= dat_i[15:0];
3808
                else
3809
                        s[31:26] <= dat_i[15:0];
3810
`endif
3811
                goto (FETCH_IMM32b);
3812
        end
3813
FETCH_IMM32b:
3814
        begin
3815
                pc <= pc + 32'd4;
3816
                ret();
3817
        end
3818
 
3819
// Fetch 32 bit displacement
3820
//
3821
FETCH_D32:
3822
        if (!cyc_o) begin
3823
                fc_o <= {sf,2'b10};
3824
                cyc_o <= 1'b1;
3825
                stb_o <= 1'b1;
3826
                sel_o <= 4'b1111;
3827
                adr_o <= pc;
3828
        end
3829
        else if (ack_i) begin
3830
    if (pc[1]) begin
3831
      stb_o <= 1'b0;
3832
      sel_o <= 4'b0000;
3833
`ifdef BIG_ENDIAN
3834
                        disp[31:16] <= {dat_i[23:16],dat_i[31:24]};
3835
`else
3836
      disp[15:0] <= dat_i[31:16];
3837
`endif
3838
                goto (FETCH_D32a);
3839
                end
3840
                else begin
3841
            cyc_o <= `LOW;
3842
      stb_o <= 1'b0;
3843
      sel_o <= 4'b0000;
3844
`ifdef BIG_ENDIAN
3845
                        disp <= rbo(dat_i);
3846
`else
3847
      disp <= dat_i;
3848
`endif
3849
      goto (FETCH_D32b);
3850
                end
3851
        end
3852
FETCH_D32a:
3853
        if (!stb_o) begin
3854
                stb_o <= 1'b1;
3855
                sel_o <= 4'b1111;
3856
                adr_o <= pc + 4'd2;
3857
        end
3858
        else if (ack_i) begin
3859
    cyc_o <= `LOW;
3860
                stb_o <= 1'b0;
3861
                sel_o <= 2'b00;
3862
`ifdef BIG_ENDIAN
3863
                disp[15:0] <= {dat_i[7:0],dat_i[15:8]};
3864
`else
3865
                disp[31:16] <= dat_i[15:0];
3866
`endif
3867
                goto (FETCH_D32b);
3868
        end
3869
FETCH_D32b:
3870
        begin
3871
                pc <= pc + 4'd4;
3872
                ea <= ea + disp;
3873
                ret();
3874
        end
3875
 
3876
// Fetch 16 bit displacement
3877
//
3878
FETCH_D16:
3879
        if (!cyc_o) begin
3880
                fc_o <= {sf,2'b10};
3881
                cyc_o <= 1'b1;
3882
                stb_o <= 1'b1;
3883
                sel_o <= 4'b1111;
3884
                adr_o <= pc;
3885
        end
3886
        else if (ack_i) begin
3887
                cyc_o <= 1'b0;
3888
                stb_o <= 1'b0;
3889
                sel_o <= 4'b0;
3890
                disp <= {{16{iri[15]}},iri};
3891
                state <= FETCH_D16a;
3892
        end
3893
FETCH_D16a:
3894
        begin
3895
                pc <= pc + 32'd2;
3896
                ea <= ea + disp;
3897
                ret();
3898
        end
3899
 
3900
// Fetch index word
3901
//
3902
FETCH_NDX:
3903
        if (!cyc_o) begin
3904
                fc_o <= {sf,2'b10};
3905
                cyc_o <= 1'b1;
3906
                stb_o <= 1'b1;
3907
                sel_o <= 4'b1111;
3908
                adr_o <= pc;
3909
        end
3910
        else if (ack_i) begin
3911
                cyc_o <= 1'b0;
3912
                stb_o <= 1'b0;
3913
                sel_o <= 2'b00;
3914
                disp <= {{24{iri[7]}},iri[7:0]};
3915
                mmm <= {2'b00,iri[15]}; // to get reg
3916
                rrr <= iri[14:12];
3917
                wl <= iri[11];
3918
                state <= FETCH_NDXa;
3919
        end
3920
FETCH_NDXa:
3921
        begin
3922
                pc <= pc + 32'd2;
3923
                if (wl)
3924
                        ea <= ea + rfob + disp;
3925
                else
3926
                        ea <= ea + {{16{rfob[15]}},rfob[15:0]} + disp;
3927
                ret();
3928
        end
3929
 
3930
FETCH_BYTE:
3931
        if (!cyc_o) begin
3932
                if (use_sfc)
3933
                        fc_o <= sfc[2:0];
3934
                else if (use_dfc)
3935
                        fc_o <= dfc[2:0];
3936
                else
3937
                        fc_o <= {sf,2'b01};
3938
                cyc_o <= `HIGH;
3939
                stb_o <= `HIGH;
3940
                adr_o <= ea;
3941
                sel_o <= 4'b1111;
3942
        end
3943
        else if (ack_i) begin
3944
                cyc_o <= `LOW;
3945
                stb_o <= `LOW;
3946
                sel_o <= 4'b0000;
3947
                if (ds==D) begin
3948
            case(ea[1:0])
3949
            2'b00:  d <= {{24{dat_i[7]}},dat_i[7:0]};
3950
            2'b01:  d <= {{24{dat_i[15]}},dat_i[15:8]};
3951
            2'b10:  d <= {{24{dat_i[23]}},dat_i[23:16]};
3952
            2'b11:  d <= {{24{dat_i[31]}},dat_i[31:24]};
3953
            default:  ;
3954
            endcase
3955
                end
3956
                else begin
3957
            case(ea[1:0])
3958
      2'b00:  s <= {{24{dat_i[7]}},dat_i[7:0]};
3959
      2'b01:  s <= {{24{dat_i[15]}},dat_i[15:8]};
3960
      2'b10:  s <= {{24{dat_i[23]}},dat_i[23:16]};
3961
      2'b11:  s <= {{24{dat_i[31]}},dat_i[31:24]};
3962
      default:    ;
3963
      endcase
3964
                end
3965
                ret();
3966
        end
3967
 
3968
// Fetch byte, but hold onto bus
3969
//
3970
LFETCH_BYTE:
3971
        if (!cyc_o) begin
3972
                if (use_sfc)
3973
                        fc_o <= sfc[2:0];
3974
                else if (use_dfc)
3975
                        fc_o <= dfc[2:0];
3976
                else
3977
                        fc_o <= {sf,2'b01};
3978
                lock_o <= `HIGH;
3979
                cyc_o <= `HIGH;
3980
                stb_o <= `HIGH;
3981
                adr_o <= ea;
3982
                sel_o <= 4'b1111;
3983
        end
3984
        else if (ack_i) begin
3985
                stb_o <= 1'b0;
3986
                sel_o <= 4'b0;
3987
                if (ds==D) begin
3988
      case(ea[1:0])
3989
      2'b00:  d <= {{24{dat_i[7]}},dat_i[7:0]};
3990
      2'b01:  d <= {{24{dat_i[15]}},dat_i[15:8]};
3991
      2'b10:  d <= {{24{dat_i[23]}},dat_i[23:16]};
3992
      2'b11:  d <= {{24{dat_i[31]}},dat_i[31:24]};
3993
      default:    ;
3994
      endcase
3995
    end
3996
    else begin
3997
      case(ea[1:0])
3998
      2'b00:  s <= {{24{dat_i[7]}},dat_i[7:0]};
3999
      2'b01:  s <= {{24{dat_i[15]}},dat_i[15:8]};
4000
      2'b10:  s <= {{24{dat_i[23]}},dat_i[23:16]};
4001
      2'b11:  s <= {{24{dat_i[31]}},dat_i[31:24]};
4002
      default:    ;
4003
      endcase
4004
    end
4005
                ret();
4006
        end
4007
 
4008
FETCH_WORD:
4009
        if (!cyc_o) begin
4010
                if (use_sfc)
4011
                        fc_o <= sfc[2:0];
4012
                else if (use_dfc)
4013
                        fc_o <= dfc[2:0];
4014
                else
4015
                        fc_o <= {sf,2'b01};
4016
                cyc_o <= `HIGH;
4017
                stb_o <= `HIGH;
4018
                adr_o <= ea;
4019
                sel_o <= 4'b1111;
4020
        end
4021
        else if (ack_i) begin
4022
                cyc_o <= 1'b0;
4023
                stb_o <= 1'b0;
4024
                sel_o <= 4'b00;
4025
`ifdef BIG_ENDIAN
4026
                if (ds==D)
4027
                  d <= ea[1] ? {{16{dat_i[23]}},dat_i[23:16],dat_i[31:24]} : {{16{dat_i[7]}},dat_i[7:0],dat_i[15:8]};
4028
                else
4029
                  s <= ea[1] ? {{16{dat_i[23]}},dat_i[23:16],dat_i[31:24]} : {{16{dat_i[7]}},dat_i[7:0],dat_i[15:8]};
4030
`else
4031
                if (ds==D)
4032
                  d <= ea[1] ? {{16{dat_i[31]}},dat_i[31:16]} : {{16{dat_i[15]}},dat_i[15:0]};
4033
                else
4034
                  s <= ea[1] ? {{16{dat_i[31]}},dat_i[31:16]} : {{16{dat_i[15]}},dat_i[15:0]};
4035
`endif
4036
                ret();
4037
        end
4038
 
4039
FETCH_LWORD:
4040
  if (!cyc_o) begin
4041
                if (use_sfc)
4042
                        fc_o <= sfc[2:0];
4043
                else if (use_dfc)
4044
                        fc_o <= dfc[2:0];
4045
                else
4046
                        fc_o <= {sf,2'b01};
4047
                cyc_o <= 1'b1;
4048
                stb_o <= 1'b1;
4049
                adr_o <= ea;
4050
                sel_o <= 4'b1111;
4051
        end
4052
        else if (ack_i) begin
4053
                stb_o <= 1'b0;
4054
                sel_o <= 4'b00;
4055
                if (ea[1]) begin
4056
`ifdef BIG_ENDIAN
4057
      if (ds==D)
4058
        d[31:16] <= {dat_i[23:16],dat_i[31:24]};
4059
      else
4060
        s[31:16] <= {dat_i[23:16],dat_i[31:24]};
4061
`else
4062
      if (ds==D)
4063
        d[15:0] <= dat_i[31:16];
4064
      else
4065
        s[15:0] <= dat_i[31:16];
4066
`endif
4067
                goto (FETCH_LWORDa);
4068
    end
4069
    else begin
4070
      cyc_o <= `LOW;
4071
`ifdef BIG_ENDIAN
4072
      if (ds==D)
4073
          d <= rbo(dat_i);
4074
      else
4075
          s <= rbo(dat_i);
4076
`else
4077
      if (ds==D)
4078
          d <= dat_i;
4079
      else
4080
          s <= dat_i;
4081
`endif
4082
      ret();
4083
    end
4084
        end
4085
FETCH_LWORDa:
4086
        if (!stb_o) begin
4087
                cyc_o <= 1'b1;
4088
                stb_o <= 1'b1;
4089
                adr_o <= adr_o + 32'd2;
4090
                sel_o <= 4'b1111;
4091
        end
4092
        else if (ack_i) begin
4093
                cyc_o <= 1'b0;
4094
                stb_o <= 1'b0;
4095
                sel_o <= 4'b00;
4096
`ifdef BIG_ENDIAN
4097
                if (ds==D)
4098
                        d[15:0] <= {dat_i[7:0],dat_i[15:8]};
4099
                else
4100
                        s[15:0] <= {dat_i[7:0],dat_i[15:8]};
4101
`else
4102
                if (ds==D)
4103
                        d[31:16] <= dat_i[15:0];
4104
                else
4105
                        s[31:16] <= dat_i[15:0];
4106
`endif
4107
                ret();
4108
        end
4109
 
4110
 
4111
STORE_BYTE:
4112
        if (!cyc_o) begin
4113
                if (use_sfc)
4114
                        fc_o <= sfc[2:0];
4115
                else if (use_dfc)
4116
                        fc_o <= dfc[2:0];
4117
                else
4118
                        fc_o <= {sf,2'b01};
4119
                cyc_o <= 1'b1;
4120
                stb_o <= 1'b1;
4121
                we_o <= 1'b1;
4122
                adr_o <= ea;
4123
                case(ea[1:0])
4124
                2'b00:  sel_o <= 4'b0001;
4125
                2'b01:  sel_o <= 4'b0010;
4126
                2'b10:  sel_o <= 4'b0100;
4127
                2'b11:  sel_o <= 4'b1000;
4128
                endcase
4129
//              dat_o <= {4{resB[7:0]}};
4130
                dat_o <= {4{d[7:0]}};
4131
        end
4132
        else if (ack_i) begin
4133
                cyc_o <= 1'b0;
4134
                stb_o <= 1'b0;
4135
                we_o <= 1'b0;
4136
                sel_o <= 4'b0;
4137
                ret();
4138
        end
4139
 
4140
// Store byte and unlock
4141
//
4142
USTORE_BYTE:
4143
        if (!stb_o) begin
4144
                if (use_sfc)
4145
                        fc_o <= sfc[2:0];
4146
                else if (use_dfc)
4147
                        fc_o <= dfc[2:0];
4148
                else
4149
                        fc_o <= {sf,2'b01};
4150
                stb_o <= 1'b1;
4151
                we_o <= 1'b1;
4152
                adr_o <= ea;
4153
                case(ea[1:0])
4154
                2'b00:  sel_o <= 4'b0001;
4155
                2'b01:  sel_o <= 4'b0010;
4156
                2'b10:  sel_o <= 4'b0100;
4157
                2'b11:  sel_o <= 4'b1000;
4158
                endcase
4159
//              dat_o <= {4{resB[7:0]}};
4160
                dat_o <= {4{d[7:0]}};
4161
        end
4162
        else if (ack_i) begin
4163
                lock_o <= 1'b0;
4164
                cyc_o <= 1'b0;
4165
                stb_o <= 1'b0;
4166
                we_o <= 1'b0;
4167
                sel_o <= 2'b00;
4168
                ret();
4169
        end
4170
 
4171
STORE_WORD:
4172
        if (!cyc_o) begin
4173
                if (use_sfc)
4174
                        fc_o <= sfc[2:0];
4175
                else if (use_dfc)
4176
                        fc_o <= dfc[2:0];
4177
                else
4178
                        fc_o <= {sf,2'b01};
4179
                cyc_o <= 1'b1;
4180
                stb_o <= 1'b1;
4181
                we_o <= 1'b1;
4182
                adr_o <= ea;
4183
                sel_o <= ea[1] ? 4'b1100 : 4'b0011;
4184
`ifdef BIG_ENDIAN
4185
//              dat_o <= {2{resW[7:0],resW[15:8]}};
4186
                dat_o <= {2{d[7:0],d[15:8]}};
4187
`else
4188
//              dat_o <= {2{resW[15:0]}};
4189
                dat_o <= {2{d[15:0]}};
4190
`endif
4191
        end
4192
        else if (ack_i) begin
4193
                cyc_o <= 1'b0;
4194
                stb_o <= 1'b0;
4195
                we_o <= 1'b0;
4196
                sel_o <= 2'b00;
4197
                ret();
4198
        end
4199
STORE_LWORD:
4200
        if (!cyc_o) begin
4201
                if (use_sfc)
4202
                        fc_o <= sfc[2:0];
4203
                else if (use_dfc)
4204
                        fc_o <= dfc[2:0];
4205
                else
4206
                        fc_o <= {sf,2'b01};
4207
                cyc_o <= 1'b1;
4208
                stb_o <= 1'b1;
4209
                we_o <= 1'b1;
4210
                adr_o <= ea;
4211
                sel_o <= ea[1] ? 4'b1100 : 4'b1111;
4212
`ifdef BIG_ENDIAN
4213
//              dat_o <= ea[1] ? {resL[23:16],resL[31:24],resL[7:0],resL[15:8]} : rbo(resL);
4214
                dat_o <= ea[1] ? {d[23:16],d[31:24],d[7:0],d[15:8]} : rbo(d);
4215
`else
4216
//              dat_o <= ea[1] ? {resL[15:0],resL[31:16]} : resL;
4217
                dat_o <= ea[1] ? {d[15:0],d[31:16]} : d;
4218
`endif
4219
        end
4220
        else if (ack_i) begin
4221
    if (ea[1]) begin
4222
      stb_o <= 1'b0;
4223
      we_o <= 1'b0;
4224
      sel_o <= 4'b00;
4225
      state <= STORE_LWORDa;
4226
                end
4227
                else begin
4228
            cyc_o <= `LOW;
4229
      stb_o <= 1'b0;
4230
      we_o <= 1'b0;
4231
      sel_o <= 4'b00;
4232
      ret();
4233
                end
4234
        end
4235
STORE_LWORDa:
4236
        if (!stb_o) begin
4237
                stb_o <= 1'b1;
4238
                we_o <= 1'b1;
4239
                adr_o <= adr_o + 32'd2;
4240
                sel_o <= 4'b0011;
4241
        end
4242
        else if (ack_i) begin
4243
                cyc_o <= 1'b0;
4244
                stb_o <= 1'b0;
4245
                we_o <= 1'b0;
4246
                sel_o <= 4'b0000;
4247
                ret();
4248
        end
4249
 
4250
//----------------------------------------------------
4251
//----------------------------------------------------
4252
RESET:
4253
  begin
4254
    pc <= `RESET_VECTOR;
4255
    push(IFETCH);
4256
    goto(TRAP);
4257
        end
4258
 
4259
//----------------------------------------------------
4260
//----------------------------------------------------
4261
TRAP:
4262
  begin
4263
    goto (TRAP3);
4264
    /*
4265
    if (is_nmi)
4266
        vecno <= `NMI_VEC;
4267
    else
4268
    */
4269
    case(1'b1)
4270
    // group 0
4271
    is_rst:
4272
        begin
4273
                is_rst <= 1'b0;
4274
                tf <= 1'b0;
4275
                sf <= 1'b1;
4276
                im <= 3'd7;
4277
                vecno <= `RESET_VEC;
4278
                goto(TRAP6);
4279
        end
4280
    is_adr_err:
4281
        begin
4282
                isr <= srx;
4283
                tf <= 1'b0;
4284
                sf <= 1'b1;
4285
                vecno <= `ADDRERR_VEC;
4286
        goto (TRAP3);
4287
        end
4288
    is_bus_err:
4289
        begin
4290
                isr <= srx;
4291
                tf <= 1'b0;
4292
                sf <= 1'b1;
4293
                vecno <= `BUSERR_VEC;
4294
        goto (TRAP3);
4295
        end
4296
    // group 1
4297
    is_trace:
4298
        begin
4299
                isr <= srx;
4300
                tf <= 1'b0;
4301
                sf <= 1'b1;
4302
                vecno <= `TRACE_VEC;
4303
        goto (TRAP3);
4304
        end
4305
    is_irq:
4306
        begin
4307
                isr <= srx;
4308
                tf <= 1'b0;
4309
                sf <= 1'b1;
4310
        vecno <= `IRQ_VEC + ipl_i;
4311
        im <= ipl_i;
4312
        goto (INTA);
4313
        end
4314
    is_priv:
4315
        begin
4316
                isr <= srx;
4317
                tf <= 1'b0;
4318
                sf <= 1'b1;
4319
                vecno <= `PRIV_VEC;
4320
        goto (TRAP3);
4321
        end
4322
    is_illegal:
4323
        begin
4324
                isr <= srx;
4325
                tf <= 1'b0;
4326
                sf <= 1'b1;
4327
                vecno <= `ILLEGAL_VEC;
4328
        goto (TRAP3);
4329
        end
4330
    default:
4331
        begin
4332
                isr <= srx;
4333
                tf <= 1'b0;
4334
                sf <= 1'b1;
4335
        vecno <= `TRAP_VEC + ir[3:0];
4336
        end
4337
    endcase
4338
  end
4339
INTA:
4340
  if (!cyc_o) begin
4341
        fc_o <= 3'b111;
4342
    cyc_o <= `HIGH;
4343
    stb_o <= `HIGH;
4344
    sel_o <= 4'b1111;
4345
    adr_o <= {28'hFFFFFFF,ipl_i,1'b0};
4346
  end
4347
  else if (ack_i|err_i|vpa_i) begin
4348
    cyc_o <= `LOW;
4349
    stb_o <= `LOW;
4350
    sel_o <= 4'b0;
4351
    if (err_i)
4352
        vecno <= `SPURIOUS_VEC;
4353
    else if (!vpa_i)
4354
        vecno <= iri[7:0];
4355
    goto (TRAP3);
4356
  end
4357
TRAP3:
4358
        begin
4359
                // If was in user mode, capture stack pointer in usp.
4360
                if (!isr[13]) begin
4361
                        usp <= sp;
4362
                        sp <= ssp;
4363
                end
4364
`ifdef SUPPORT_010
4365
                if (is_bus_err | is_adr_err)
4366
                        goto (TRAP20);
4367
                else
4368
                        goto (TRAP3a);
4369
`else
4370
                goto (TRAP3b);
4371
`endif
4372
        end
4373
// First 16 words of internal state are stored
4374
TRAP20:
4375
        begin
4376
                sp <= sp - 6'd32;
4377
                goto (TRAP21);
4378
        end
4379
// Next instruction input buffer.
4380
TRAP21:
4381
        begin
4382
                d <= ir;
4383
                ea <= sp - 4'd2;
4384
                sp <= sp - 4'd2;
4385
                call (STORE_WORD, TRAP22);
4386
        end
4387
TRAP22:
4388
        begin
4389
                d <= dati_buf;
4390
                ea <= sp - 4'd4;
4391
                sp <= sp - 4'd4;
4392
                call (STORE_LWORD, TRAP23);
4393
        end
4394
TRAP23:
4395
        begin
4396
                d <= dato_buf;
4397
                ea <= sp - 4'd4;
4398
                sp <= sp - 4'd4;
4399
                call (STORE_LWORD, TRAP24);
4400
        end
4401
// 1 word Unused
4402
TRAP24:
4403
        begin
4404
                sp <= sp - 4'd2;
4405
                goto (TRAP25);
4406
        end
4407
TRAP25:
4408
        begin
4409
                d <= bad_addr;
4410
                ea <= sp - 4'd4;
4411
                sp <= sp - 4'd4;
4412
                call (STORE_LWORD, TRAP26);
4413
        end
4414
TRAP26:
4415
        begin
4416
                d <= mac_cycle_type;
4417
                ea <= sp - 4'd2;
4418
                sp <= sp - 4'd2;
4419
                s <= sp - 4'd2;
4420
                call (STORE_WORD, TRAP3a);
4421
        end
4422
// For the 68010 and above push the format word.
4423
TRAP3a:
4424
        begin
4425
`ifdef SUPPORT_010
4426
                if (is_bus_err|is_adr_err)
4427
                        d <= {4'b1000,2'b00,vecno,2'b00};
4428
                else
4429
                        d <= {4'b0000,2'b00,vecno,2'b00};
4430
                ea <= sp - 4'd2;
4431
                sp <= sp - 4'd2;
4432
                call (STORE_WORD, TRAP3b);
4433
`else
4434
                goto (TRAP3b);
4435
`endif
4436
        end
4437
// Push the program counter
4438
TRAP3b:
4439
        begin
4440
                d <= pc;
4441
                ea <= sp - 4'd4;
4442
                sp <= sp - 4'd4;
4443
                call (STORE_LWORD, TRAP4);
4444
        end
4445
// And the status register
4446
TRAP4:
4447
        begin
4448
                d <= isr;
4449
                ea <= sp - 4'd2;
4450
                sp <= sp - 4'd2;
4451
                s <= sp - 4'd2;
4452
`ifdef SUPPORT_010
4453
                call (STORE_WORD, TRAP7);
4454
`else
4455
                call (STORE_WORD, is_bus_err|is_adr_err?TRAP8:TRAP7);
4456
`endif
4457
        end
4458
// Push IR
4459
TRAP8:
4460
        begin
4461
                d <= ir;
4462
                ea <= sp - 4'd2;
4463
                sp <= sp - 4'd2;
4464
                is_bus_err <= 1'b0;
4465
                is_adr_err <= 1'b0;
4466
                call (STORE_WORD, TRAP9);
4467
        end
4468
// Push bad address
4469
TRAP9:
4470
        begin
4471
                d <= bad_addr;
4472
                ea <= sp - 4'd4;
4473
                sp <= sp - 4'd4;
4474
                call (STORE_LWORD, TRAP10);
4475
        end
4476
TRAP10:
4477
        begin
4478
                d <= mac_cycle_type;
4479
                ea <= sp - 4'd2;
4480
                sp <= sp - 4'd2;
4481
                s <= sp - 4'd2;
4482
                call (STORE_WORD, TRAP7);
4483
        end
4484
// Load SP from vector table
4485
TRAP6:
4486
        begin
4487
                ea <= 'd0;
4488
                ds <= S;
4489
                call (FETCH_LWORD, TRAP7);
4490
        end
4491
// Load PC from vector table.
4492
TRAP7:
4493
        begin
4494
                sp <= s;
4495
                ssp <= s;
4496
                ea <= {vbr[31:2]+vecno,2'b00};
4497
                ds <= S;
4498
                call (FETCH_LWORD, TRAP7a);
4499
        end
4500
TRAP7a:
4501
        begin
4502
                pc <= s;
4503
                ret();
4504
        end
4505
 
4506
//----------------------------------------------------
4507
//----------------------------------------------------
4508
/*
4509
JMP_VECTOR:
4510
        if (!cyc_o) begin
4511
                fc_o <= {sf,2'b01};
4512
                cyc_o <= 1'b1;
4513
                stb_o <= 1'b1;
4514
                sel_o <= 2'b11;
4515
                adr_o <= vector;
4516
        end
4517
        else if (ack_i) begin
4518
                stb_o <= 1'b0;
4519
                sel_o <= 2'b00;
4520
                pc[15:0] <= dat_i;
4521
                state <= JMP_VECTOR2;
4522
        end
4523
JMP_VECTOR2:
4524
        if (!stb_o) begin
4525
                fc_o <= {sf,2'b01};
4526
                cyc_o <= 1'b1;
4527
                stb_o <= 1'b1;
4528
                sel_o <= 2'b11;
4529
                adr_o <= adr_o + 32'd2;
4530
        end
4531
        else if (ack_i) begin
4532
                cyc_o <= 1'b0;
4533
                stb_o <= 1'b0;
4534
                sel_o <= 2'b00;
4535
                pc[31:16] <= dat_i;
4536
                state <= IFETCH;
4537
        end
4538
*/
4539
//----------------------------------------------------
4540
//----------------------------------------------------
4541
UNLNK:
4542
        begin
4543
                ds <= S;
4544
                ea <= sp;
4545
                sp <= sp + 4'd4;
4546
                call (FETCH_LWORD,UNLNK2);
4547
        end
4548
UNLNK2:
4549
        begin
4550
                rfwrL <= 1'b1;
4551
                Rt <= {1'b1,rrr};
4552
                resL <= s;
4553
                ret();
4554
        end
4555
 
4556
//----------------------------------------------------
4557
// JMP / JSR / BSR
4558
//----------------------------------------------------
4559
 
4560
JMP:
4561
        begin
4562
                pc <= ea;
4563
                ret();
4564
        end
4565
JSR:
4566
        begin
4567
                ea <= sp - 4'd4;
4568
                sp <= sp - 4'd4;
4569
                d <= pc;
4570
                pc <= ea;
4571
                goto (STORE_LWORD);
4572
        end
4573
/*
4574
        if (!cyc_o) begin
4575
                fc_o <= {sf,2'b01};
4576
                cyc_o <= 1'b1;
4577
                stb_o <= 1'b1;
4578
                we_o <= 1'b1;
4579
                sel_o <= 4'b1111;
4580
                adr_o <= sp - 32'd4;
4581
`ifdef BIG_ENDIAN
4582
                dat_o <= rbo(pc);
4583
`else
4584
                dat_o <= pc;
4585
`endif
4586
        end
4587
        else if (ack_i) begin
4588
                cyc_o <= 1'b0;
4589
                stb_o <= 1'b0;
4590
                we_o <= 1'b0;
4591
                sel_o <= 4'b00;
4592
                sp <= sp - 32'd4;
4593
                pc <= d;
4594
`ifdef SUPPORT_TASK
4595
`ifdef BIG_ENDIAN
4596
                if (d[24]) begin
4597
                        otr <= tr;
4598
                        tr <= d[29:25];
4599
        reg_copy_mask <= {d[7:0],d[15:8],d[16]};
4600
                        goto (THREAD2);
4601
    end
4602
                else
4603
                        ret();
4604
`else
4605
                if (d[0]) begin
4606
                        otr <= tr;
4607
                        tr <= d[5:1];
4608
                        reg_copy_mask <= d[31:16];
4609
                        goto (THREAD2);
4610
                end
4611
                else
4612
                        ret();
4613
`endif
4614
`else
4615
                ret();
4616
`endif
4617
        end
4618
*/
4619
 
4620
//----------------------------------------------------
4621
// RTE / RTR
4622
// Return from exception
4623
//----------------------------------------------------
4624
 
4625
RTE1:
4626
        begin
4627
                ds <= S;
4628
                ea <= sp;
4629
                sp <= sp + 4'd2;
4630
                call (FETCH_WORD,RTE2);
4631
        end
4632
RTE2:
4633
        begin
4634
                ds <= S;
4635
                ea <= sp;
4636
                sp <= sp + 4'd4;
4637
                cf <= s[0];
4638
                vf <= s[1];
4639
                zf <= s[2];
4640
                nf <= s[3];
4641
                xf <= s[4];
4642
                ccr57 <= s[7:5];
4643
                if (!rtr) begin
4644
                        im[0] <= s[8];
4645
                        im[1] <= s[9];
4646
                        im[2] <= s[10];
4647
                        sr1112 <= s[12:11];
4648
                        sf <= s[13];
4649
                        sr14 <= s[14];
4650
                        tf <= s[15];
4651
                        //pl <= s[31:24];
4652
                end
4653
                call (FETCH_LWORD,RTE3);
4654
        end
4655
RTE3:
4656
        begin
4657
                pc <= s;
4658
`ifdef SUPPORT_010
4659
                ea <= sp;
4660
                sp <= sp + 4'd2;
4661
                if (!rtr)
4662
                        call (FETCH_WORD,RTE4);
4663
                else
4664
                        ret();
4665
`else
4666
                if (!rtr && !sf) begin
4667
                        ssp <= sp;
4668
                        sp <= usp;
4669
                end
4670
                ret();
4671
`endif
4672
        end
4673
// The core might have been in supervisor mode already when the exception
4674
// occurred. Reset the working stack pointer accordingly.
4675
`ifdef SUPPORT_010
4676
RTE4:
4677
        begin
4678
                if (s[15:12]==4'b1000) begin
4679
                        ea <= sp;
4680
                        sp <= sp + 4'd2;
4681
                        call(FETCH_WORD,RTE5);
4682
                end
4683
                else begin
4684
                        if (!sf) begin
4685
                                ssp <= sp;
4686
                                sp <= usp;      // switch back to user stack
4687
                        end
4688
                        ret();
4689
                end
4690
        end
4691
RTE5:
4692
        begin
4693
                mac_cycle_type <= s;
4694
                ea <= sp;
4695
                sp <= sp + 4'd4;
4696
                call(FETCH_LWORD,RTE6);
4697
        end
4698
RTE6:
4699
        begin
4700
                bad_addr <= s;
4701
                ea <= sp;
4702
                sp <= sp + 4'd2;
4703
                call(FETCH_WORD,RTE7);
4704
        end
4705
RTE7:
4706
        begin
4707
                ea <= sp;
4708
                sp <= sp + 4'd4;
4709
                call(FETCH_LWORD,RTE8);
4710
        end
4711
RTE8:
4712
        begin
4713
                dato_buf <= s;
4714
                ea <= sp;
4715
                sp <= sp + 4'd4;
4716
                call(FETCH_LWORD,RTE9);
4717
        end
4718
RTE9:
4719
        begin
4720
                dati_buf <= s;
4721
                ea <= sp;
4722
                sp <= sp + 4'd2;
4723
                call(FETCH_WORD,RTE10);
4724
        end
4725
RTE10:
4726
        begin
4727
                ea <= sp;
4728
                sp <= sp + 6'd32;
4729
                goto (RTE11);
4730
        end
4731
RTE11:
4732
        begin
4733
                if (!sf) begin
4734
                        ssp <= sp;
4735
                        sp <= usp;      // switch back to user stack
4736
                end
4737
                ret();
4738
        end
4739
`endif
4740
 
4741
//----------------------------------------------------
4742
// Return from subroutine.
4743
//----------------------------------------------------
4744
 
4745
RTS1:
4746
        begin
4747
                pc <= s;
4748
                ret();
4749
        end
4750
 
4751
//----------------------------------------------------
4752
MOVEM_Xn2D:
4753
`ifdef OPT_PERF
4754
        if (imm[15:0]!=16'h0000) begin
4755
                push(MOVEM_Xn2D2);
4756
                fs_data(mmm,rrr,ir[6] ? FETCH_NOP_LWORD : FETCH_NOP_WORD,D);
4757
        end
4758
        else
4759
                fs_data(mmm,rrr,ir[6] ? FETCH_NOP_LWORD : FETCH_NOP_WORD,D);
4760
`else
4761
        begin
4762
                push(MOVEM_Xn2D2);
4763
                fs_data(mmm,rrr,ir[6] ? FETCH_NOP_LWORD : FETCH_NOP_WORD,D);
4764
        end
4765
`endif
4766
MOVEM_Xn2D2:
4767
        begin
4768
                if (imm[15:0]!=16'h0000)
4769
                        state <= MOVEM_Xn2D3;
4770
                else begin
4771
                        case(mmm)
4772
                        3'b100: // -(An)
4773
                                begin
4774
                                        Rt <= {1'b1,rrr};
4775
                                        resL <= ea + (ir[6] ? 32'd4 : 32'd2);
4776
                                        rfwrL <= 1'b1;
4777
                                end
4778
                        endcase
4779
                        ret();
4780
                end
4781
                if (mmm!=3'b100) begin
4782
                        if (imm[0]) begin
4783
                                imm[0] <= 1'b0;
4784
                                rrrr <= 4'd0;
4785
                        end
4786
                        else if (imm[1]) begin
4787
                                imm[1] <= 1'b0;
4788
                                rrrr <= 4'd1;
4789
                        end
4790
                        else if (imm[2]) begin
4791
                                imm[2] <= 1'b0;
4792
                                rrrr <= 4'd2;
4793
                        end
4794
                        else if (imm[3]) begin
4795
                                imm[3] <= 1'b0;
4796
                                rrrr <= 4'd3;
4797
                        end
4798
                        else if (imm[4]) begin
4799
                                imm[4] <= 1'b0;
4800
                                rrrr <= 4'd4;
4801
                        end
4802
                        else if (imm[5]) begin
4803
                                imm[5] <= 1'b0;
4804
                                rrrr <= 4'd5;
4805
                        end
4806
                        else if (imm[6]) begin
4807
                                imm[6] <= 1'b0;
4808
                                rrrr <= 4'd6;
4809
                        end
4810
                        else if (imm[7]) begin
4811
                                imm[7] <= 1'b0;
4812
                                rrrr <= 4'd7;
4813
                        end
4814
                        else if (imm[8]) begin
4815
                                imm[8] <= 1'b0;
4816
                                rrrr <= 4'd8;
4817
                        end
4818
                        else if (imm[9]) begin
4819
                                imm[9] <= 1'b0;
4820
                                rrrr <= 4'd9;
4821
                        end
4822
                        else if (imm[10]) begin
4823
                                imm[10] <= 1'b0;
4824
                                rrrr <= 4'd10;
4825
                        end
4826
                        else if (imm[11]) begin
4827
                                imm[11] <= 1'b0;
4828
                                rrrr <= 4'd11;
4829
                        end
4830
                        else if (imm[12]) begin
4831
                                imm[12] <= 1'b0;
4832
                                rrrr <= 4'd12;
4833
                        end
4834
                        else if (imm[13]) begin
4835
                                imm[13] <= 1'b0;
4836
                                rrrr <= 4'd13;
4837
                        end
4838
                        else if (imm[14]) begin
4839
                                imm[14] <= 1'b0;
4840
                                rrrr <= 4'd14;
4841
                        end
4842
                        else if (imm[15]) begin
4843
                                imm[15] <= 1'b0;
4844
                                rrrr <= 4'd15;
4845
                        end
4846
                end
4847
                else begin
4848
                        if (imm[0]) begin
4849
                                imm[0] <= 1'b0;
4850
                                rrrr <= 4'd15;
4851
                        end
4852
                        else if (imm[1]) begin
4853
                                imm[1] <= 1'b0;
4854
                                rrrr <= 4'd14;
4855
                        end
4856
                        else if (imm[2]) begin
4857
                                imm[2] <= 1'b0;
4858
                                rrrr <= 4'd13;
4859
                        end
4860
                        else if (imm[3]) begin
4861
                                imm[3] <= 1'b0;
4862
                                rrrr <= 4'd12;
4863
                        end
4864
                        else if (imm[4]) begin
4865
                                imm[4] <= 1'b0;
4866
                                rrrr <= 4'd11;
4867
                        end
4868
                        else if (imm[5]) begin
4869
                                imm[5] <= 1'b0;
4870
                                rrrr <= 4'd10;
4871
                        end
4872
                        else if (imm[6]) begin
4873
                                imm[6] <= 1'b0;
4874
                                rrrr <= 4'd9;
4875
                        end
4876
                        else if (imm[7]) begin
4877
                                imm[7] <= 1'b0;
4878
                                rrrr <= 4'd8;
4879
                        end
4880
                        else if (imm[8]) begin
4881
                                imm[8] <= 1'b0;
4882
                                rrrr <= 4'd7;
4883
                        end
4884
                        else if (imm[9]) begin
4885
                                imm[9] <= 1'b0;
4886
                                rrrr <= 4'd6;
4887
                        end
4888
                        else if (imm[10]) begin
4889
                                imm[10] <= 1'b0;
4890
                                rrrr <= 4'd5;
4891
                        end
4892
                        else if (imm[11]) begin
4893
                                imm[11] <= 1'b0;
4894
                                rrrr <= 4'd4;
4895
                        end
4896
                        else if (imm[12]) begin
4897
                                imm[12] <= 1'b0;
4898
                                rrrr <= 4'd3;
4899
                        end
4900
                        else if (imm[13]) begin
4901
                                imm[13] <= 1'b0;
4902
                                rrrr <= 4'd2;
4903
                        end
4904
                        else if (imm[14]) begin
4905
                                imm[14] <= 1'b0;
4906
                                rrrr <= 4'd1;
4907
                        end
4908
                        else if (imm[15]) begin
4909
                                imm[15] <= 1'b0;
4910
                                rrrr <= 4'd0;
4911
                        end
4912
                end
4913
        end
4914
MOVEM_Xn2D3:
4915
        begin
4916
                resL <= rfoRnn;
4917
                resW <= rfoRnn[15:0];
4918
                d <= rfoRnn;
4919
                ds <= D;
4920
                call(ir[6] ? STORE_LWORD : STORE_WORD,MOVEM_Xn2D4);
4921
        end
4922
MOVEM_Xn2D4:
4923
        begin
4924
                case(mmm)
4925
                3'b011: ea <= ea + (ir[6] ? 32'd4 : 32'd2);
4926
                3'b100: ea <= ea - (ir[6] ? 32'd4 : 32'd2);
4927
                default:
4928
                        ea <= ea + (ir[6] ? 32'd4 : 32'd2);
4929
                endcase
4930
                if (imm[15:0]!=16'h0000)
4931
                        state <= MOVEM_Xn2D3;
4932
                else begin
4933
                        case(mmm)
4934
                        3'b011:
4935
                                begin
4936
                                        Rt <= {1'b1,rrr};
4937
                                        resL <= ea + (ir[6] ? 32'd4 : 32'd2);
4938
                                        rfwrL <= 1'b1;
4939
                                end
4940
                        3'b100:
4941
                                begin
4942
                                        Rt <= {1'b1,rrr};
4943
                                        resL <= ea;
4944
                                        rfwrL <= 1'b1;
4945
                                end
4946
                        endcase
4947
                        ret();
4948
                end
4949
                if (mmm!=3'b100) begin
4950
                        if (imm[0]) begin
4951
                                imm[0] <= 1'b0;
4952
                                rrrr <= 4'd0;
4953
                        end
4954
                        else if (imm[1]) begin
4955
                                imm[1] <= 1'b0;
4956
                                rrrr <= 4'd1;
4957
                        end
4958
                        else if (imm[2]) begin
4959
                                imm[2] <= 1'b0;
4960
                                rrrr <= 4'd2;
4961
                        end
4962
                        else if (imm[3]) begin
4963
                                imm[3] <= 1'b0;
4964
                                rrrr <= 4'd3;
4965
                        end
4966
                        else if (imm[4]) begin
4967
                                imm[4] <= 1'b0;
4968
                                rrrr <= 4'd4;
4969
                        end
4970
                        else if (imm[5]) begin
4971
                                imm[5] <= 1'b0;
4972
                                rrrr <= 4'd5;
4973
                        end
4974
                        else if (imm[6]) begin
4975
                                imm[6] <= 1'b0;
4976
                                rrrr <= 4'd6;
4977
                        end
4978
                        else if (imm[7]) begin
4979
                                imm[7] <= 1'b0;
4980
                                rrrr <= 4'd7;
4981
                        end
4982
                        else if (imm[8]) begin
4983
                                imm[8] <= 1'b0;
4984
                                rrrr <= 4'd8;
4985
                        end
4986
                        else if (imm[9]) begin
4987
                                imm[9] <= 1'b0;
4988
                                rrrr <= 4'd9;
4989
                        end
4990
                        else if (imm[10]) begin
4991
                                imm[10] <= 1'b0;
4992
                                rrrr <= 4'd10;
4993
                        end
4994
                        else if (imm[11]) begin
4995
                                imm[11] <= 1'b0;
4996
                                rrrr <= 4'd11;
4997
                        end
4998
                        else if (imm[12]) begin
4999
                                imm[12] <= 1'b0;
5000
                                rrrr <= 4'd12;
5001
                        end
5002
                        else if (imm[13]) begin
5003
                                imm[13] <= 1'b0;
5004
                                rrrr <= 4'd13;
5005
                        end
5006
                        else if (imm[14]) begin
5007
                                imm[14] <= 1'b0;
5008
                                rrrr <= 4'd14;
5009
                        end
5010
                        else if (imm[15]) begin
5011
                                imm[15] <= 1'b0;
5012
                                rrrr <= 4'd15;
5013
                        end
5014
                end
5015
                else begin
5016
                        if (imm[0]) begin
5017
                                imm[0] <= 1'b0;
5018
                                rrrr <= 4'd15;
5019
                        end
5020
                        else if (imm[1]) begin
5021
                                imm[1] <= 1'b0;
5022
                                rrrr <= 4'd14;
5023
                        end
5024
                        else if (imm[2]) begin
5025
                                imm[2] <= 1'b0;
5026
                                rrrr <= 4'd13;
5027
                        end
5028
                        else if (imm[3]) begin
5029
                                imm[3] <= 1'b0;
5030
                                rrrr <= 4'd12;
5031
                        end
5032
                        else if (imm[4]) begin
5033
                                imm[4] <= 1'b0;
5034
                                rrrr <= 4'd11;
5035
                        end
5036
                        else if (imm[5]) begin
5037
                                imm[5] <= 1'b0;
5038
                                rrrr <= 4'd10;
5039
                        end
5040
                        else if (imm[6]) begin
5041
                                imm[6] <= 1'b0;
5042
                                rrrr <= 4'd9;
5043
                        end
5044
                        else if (imm[7]) begin
5045
                                imm[7] <= 1'b0;
5046
                                rrrr <= 4'd8;
5047
                        end
5048
                        else if (imm[8]) begin
5049
                                imm[8] <= 1'b0;
5050
                                rrrr <= 4'd7;
5051
                        end
5052
                        else if (imm[9]) begin
5053
                                imm[9] <= 1'b0;
5054
                                rrrr <= 4'd6;
5055
                        end
5056
                        else if (imm[10]) begin
5057
                                imm[10] <= 1'b0;
5058
                                rrrr <= 4'd5;
5059
                        end
5060
                        else if (imm[11]) begin
5061
                                imm[11] <= 1'b0;
5062
                                rrrr <= 4'd4;
5063
                        end
5064
                        else if (imm[12]) begin
5065
                                imm[12] <= 1'b0;
5066
                                rrrr <= 4'd3;
5067
                        end
5068
                        else if (imm[13]) begin
5069
                                imm[13] <= 1'b0;
5070
                                rrrr <= 4'd2;
5071
                        end
5072
                        else if (imm[14]) begin
5073
                                imm[14] <= 1'b0;
5074
                                rrrr <= 4'd1;
5075
                        end
5076
                        else if (imm[15]) begin
5077
                                imm[15] <= 1'b0;
5078
                                rrrr <= 4'd0;
5079
                        end
5080
                end
5081
        end
5082
 
5083
//----------------------------------------------------
5084
MOVEM_s2Xn:
5085
`ifdef OPT_PERF
5086
        if (imm[15:0]!=16'h0000) begin
5087
                push(MOVEM_s2Xn2);
5088
                fs_data(mmm,rrr,ir[6] ? FETCH_NOP_LWORD : FETCH_NOP_WORD,S);
5089
        end
5090
        else
5091
                fs_data(mmm,rrr,ir[6] ? FETCH_NOP_LWORD : FETCH_NOP_WORD,S);
5092
`else
5093
        begin
5094
                push(MOVEM_s2Xn2);
5095
                fs_data(mmm,rrr,ir[6] ? FETCH_NOP_LWORD : FETCH_NOP_WORD,S);
5096
        end
5097
`endif
5098
MOVEM_s2Xn2:
5099
        if (imm[15:0] != 16'h0000) begin
5100
                ds <= S;
5101
                call(ir[6] ? FETCH_LWORD : FETCH_WORD,MOVEM_s2Xn3);
5102
        end
5103
        else begin
5104
                case(mmm)
5105
                3'b011: // (An)+
5106
                        begin
5107
                                Rt <= {1'b1,rrr};
5108
                                resL <= ea;
5109
                                rfwrL <= 1'b1;
5110
                        end
5111
                3'b100: // -(An)
5112
                        begin
5113
                                Rt <= {1'b1,rrr};
5114
                                resL <= ea + (ir[6] ? 32'd4 : 32'd2);
5115
                                rfwrL <= 1'b1;
5116
                        end
5117
                endcase
5118
                ret();
5119
        end
5120
MOVEM_s2Xn3:
5121
        begin
5122
                case(mmm)
5123
                3'b011: ea <= ea + (ir[6] ? 32'd4 : 32'd2);
5124
                3'b100: ea <= ea - (ir[6] ? 32'd4 : 32'd2);
5125
                default:
5126
                        ea <= ea + (ir[6] ? 32'd4 : 32'd2);
5127
                endcase
5128
                goto (MOVEM_s2Xn2);
5129
                // Another bizzare gotcha. Word values moved to a data register are sign
5130
                // extended to long-word width.
5131
                rfwrL <= 1'b1;
5132
                if (ir[6])
5133
                        resL <= s;
5134
                else
5135
                        resL <= {{16{s[15]}},s[15:0]};
5136
                if (mmm!=3'b100) begin
5137
                        if (imm[0]) begin
5138
                                imm[0] <= 1'b0;
5139
                                Rt <= 4'd0;
5140
                        end
5141
                        else if (imm[1]) begin
5142
                                imm[1] <= 1'b0;
5143
                                Rt <= 4'd1;
5144
                        end
5145
                        else if (imm[2]) begin
5146
                                imm[2] <= 1'b0;
5147
                                Rt <= 4'd2;
5148
                        end
5149
                        else if (imm[3]) begin
5150
                                imm[3] <= 1'b0;
5151
                                Rt <= 4'd3;
5152
                        end
5153
                        else if (imm[4]) begin
5154
                                imm[4] <= 1'b0;
5155
                                Rt <= 4'd4;
5156
                        end
5157
                        else if (imm[5]) begin
5158
                                imm[5] <= 1'b0;
5159
                                Rt <= 4'd5;
5160
                        end
5161
                        else if (imm[6]) begin
5162
                                imm[6] <= 1'b0;
5163
                                Rt <= 4'd6;
5164
                        end
5165
                        else if (imm[7]) begin
5166
                                imm[7] <= 1'b0;
5167
                                Rt <= 4'd7;
5168
                        end
5169
                        else if (imm[8]) begin
5170
                                imm[8] <= 1'b0;
5171
                                Rt <= 4'd8;
5172
                        end
5173
                        else if (imm[9]) begin
5174
                                imm[9] <= 1'b0;
5175
                                Rt <= 4'd9;
5176
                        end
5177
                        else if (imm[10]) begin
5178
                                imm[10] <= 1'b0;
5179
                                Rt <= 4'd10;
5180
                        end
5181
                        else if (imm[11]) begin
5182
                                imm[11] <= 1'b0;
5183
                                Rt <= 4'd11;
5184
                        end
5185
                        else if (imm[12]) begin
5186
                                imm[12] <= 1'b0;
5187
                                Rt <= 4'd12;
5188
                        end
5189
                        else if (imm[13]) begin
5190
                                imm[13] <= 1'b0;
5191
                                Rt <= 4'd13;
5192
                        end
5193
                        else if (imm[14]) begin
5194
                                imm[14] <= 1'b0;
5195
                                Rt <= 4'd14;
5196
                        end
5197
                        else if (imm[15]) begin
5198
                                imm[15] <= 1'b0;
5199
                                Rt <= 4'd15;
5200
                        end
5201
                end
5202
                else begin
5203
                        if (imm[0]) begin
5204
                                imm[0] <= 1'b0;
5205
                                Rt <= 4'd15;
5206
                        end
5207
                        else if (imm[1]) begin
5208
                                imm[1] <= 1'b0;
5209
                                Rt <= 4'd14;
5210
                        end
5211
                        else if (imm[2]) begin
5212
                                imm[2] <= 1'b0;
5213
                                Rt <= 4'd13;
5214
                        end
5215
                        else if (imm[3]) begin
5216
                                imm[3] <= 1'b0;
5217
                                Rt <= 4'd12;
5218
                        end
5219
                        else if (imm[4]) begin
5220
                                imm[4] <= 1'b0;
5221
                                Rt <= 4'd11;
5222
                        end
5223
                        else if (imm[5]) begin
5224
                                imm[5] <= 1'b0;
5225
                                Rt <= 4'd10;
5226
                        end
5227
                        else if (imm[6]) begin
5228
                                imm[6] <= 1'b0;
5229
                                Rt <= 4'd9;
5230
                        end
5231
                        else if (imm[7]) begin
5232
                                imm[7] <= 1'b0;
5233
                                Rt <= 4'd8;
5234
                        end
5235
                        else if (imm[8]) begin
5236
                                imm[8] <= 1'b0;
5237
                                Rt <= 4'd7;
5238
                        end
5239
                        else if (imm[9]) begin
5240
                                imm[9] <= 1'b0;
5241
                                Rt <= 4'd6;
5242
                        end
5243
                        else if (imm[10]) begin
5244
                                imm[10] <= 1'b0;
5245
                                Rt <= 4'd5;
5246
                        end
5247
                        else if (imm[11]) begin
5248
                                imm[11] <= 1'b0;
5249
                                Rt <= 4'd4;
5250
                        end
5251
                        else if (imm[12]) begin
5252
                                imm[12] <= 1'b0;
5253
                                Rt <= 4'd3;
5254
                        end
5255
                        else if (imm[13]) begin
5256
                                imm[13] <= 1'b0;
5257
                                Rt <= 4'd2;
5258
                        end
5259
                        else if (imm[14]) begin
5260
                                imm[14] <= 1'b0;
5261
                                Rt <= 4'd1;
5262
                        end
5263
                        else if (imm[15]) begin
5264
                                imm[15] <= 1'b0;
5265
                                Rt <= 4'd0;
5266
                        end
5267
                end
5268
        end
5269
//----------------------------------------------------
5270
RETSTATE:
5271
        ret();
5272
 
5273
//------------------------------------------------------------------------------
5274
//------------------------------------------------------------------------------
5275
MOVEP:
5276
        if (!cyc_o) begin
5277
                cyc_o <= `HIGH;
5278
                stb_o <= `HIGH;
5279
                we_o <= ir[7];
5280
                casez({ir[7],ea[1:0]})
5281
                3'b0??: sel_o <= 4'b1111;
5282
                3'b100: sel_o <= 4'b0001;
5283
                3'b101: sel_o <= 4'b0010;
5284
                3'b110: sel_o <= 4'b0100;
5285
                3'b111: sel_o <= 4'b1000;
5286
                endcase
5287
                adr_o <= ea;
5288
                if (ir[6])
5289
                        dat_o <= {4{rfoDn[31:24]}};
5290
                else
5291
                        dat_o <= {4{rfoDn[15:8]}};
5292
        end
5293
        else if (ack_i) begin
5294
                stb_o <= `LOW;
5295
                if (ir[6])
5296
                        resL[31:24] <= dat_i >> {ea[1:0],3'b0};
5297
                else
5298
                        resW[15:8] <= dat_i >> {ea[1:0],3'b0};
5299
                goto (MOVEP1);
5300
        end
5301
MOVEP1:
5302
        if (!stb_o) begin
5303
                stb_o <= `HIGH;
5304
                we_o <= ir[7];
5305
                casez({ir[7],~ea[1],ea[0]})
5306
                3'b0??: sel_o <= 4'b1111;
5307
                3'b100: sel_o <= 4'b0001;
5308
                3'b101: sel_o <= 4'b0010;
5309
                3'b110: sel_o <= 4'b0100;
5310
                3'b111: sel_o <= 4'b1000;
5311
                endcase
5312
                adr_o <= ea + 4'd2;
5313
                if (ir[6])
5314
                        dat_o <= {4{rfoDn[23:16]}};
5315
                else
5316
                        dat_o <= {4{rfoDn[7:0]}};
5317
        end
5318
        else if (ack_i) begin
5319
                stb_o <= `LOW;
5320
                if (ir[6])
5321
                        resL[23:16] <= dat_i >> {ea[1:0]+4'd2,3'b0};
5322
                else
5323
                        resW[7:0] <= dat_i >> {ea[1:0]+4'd2,3'b0};
5324
                Rt <= {1'b0,DDD};
5325
                if (ir[6])
5326
                        goto (MOVEP2);
5327
                else begin
5328
                        cyc_o <= `LOW;
5329
                        we_o <= `LOW;
5330
                        sel_o <= 4'h0;
5331
                        rfwrW <= ~ir[7];
5332
                        ret();
5333
                end
5334
        end
5335
MOVEP2:
5336
        if (!stb_o) begin
5337
                stb_o <= `HIGH;
5338
                we_o <= ir[7];
5339
                casez({ir[7],ea[1:0]})
5340
                3'b0??: sel_o <= 4'b1111;
5341
                3'b100: sel_o <= 4'b0001;
5342
                3'b101: sel_o <= 4'b0010;
5343
                3'b110: sel_o <= 4'b0100;
5344
                3'b111: sel_o <= 4'b1000;
5345
                endcase
5346
                adr_o <= ea + 4'd4;
5347
                dat_o <= {4{rfoDn[15:8]}};
5348
        end
5349
        else if (ack_i) begin
5350
                stb_o <= `LOW;
5351
                resL[15:8] <= dat_i >> {ea[1:0],3'b0};
5352
                goto (MOVEP3);
5353
        end
5354
MOVEP3:
5355
        if (!stb_o) begin
5356
                stb_o <= `HIGH;
5357
                we_o <= ir[7];
5358
                casez({ir[7],~ea[1],ea[0]})
5359
                3'b0??: sel_o <= 4'b1111;
5360
                3'b100: sel_o <= 4'b0001;
5361
                3'b101: sel_o <= 4'b0010;
5362
                3'b110: sel_o <= 4'b0100;
5363
                3'b111: sel_o <= 4'b1000;
5364
                endcase
5365
                adr_o <= ea + 4'd6;
5366
                dat_o <= {4{rfoDn[7:0]}};
5367
        end
5368
        else if (ack_i) begin
5369
                cyc_o <= `LOW;
5370
                stb_o <= `LOW;
5371
                we_o <= `LOW;
5372
                sel_o <= 4'h0;
5373
                resL[7:0] <= dat_i >> {ea[1:0]+4'd2,3'b0};
5374
                Rt <= {1'b0,DDD};
5375
                rfwrL <= ~ir[7];
5376
                ret();
5377
        end
5378
 
5379
 
5380
FSDATA2:
5381
        fs_data2(mmmx,rrrx,sz_state,dsix);
5382
 
5383
// On a retry, wait some random number of cycle before retrying the bus
5384
// operation.
5385
`ifdef SUPPORT_RETRY
5386
RETRY:
5387
        begin
5388
                cnt <= {lfsr_o[3:0] + 4'd8};
5389
                goto (RETRY2);
5390
        end
5391
RETRY2:
5392
        begin
5393
                cnt <= cnt - 2'd1;
5394
                if (cnt=='d0)
5395
                        goto (rstate);
5396
        end
5397
`endif
5398
 
5399
MOVERn2Rc:
5400
        begin
5401
                rrrr <= imm[15:12];
5402
                goto (MOVERn2Rc2);
5403
        end
5404
MOVERn2Rc2:
5405
        case(imm[11:0])
5406
        12'h000:        begin sfc <= rfoRnn; ret(); end
5407
        12'h001:        begin dfc <= rfoRnn; ret(); end
5408 3 robfinch
        12'h003:  begin asid <= rfoRnn[7:0]; ret(); end
5409
        12'h010:  begin apc <= rfoRnn; ret(); end
5410
        12'h011:  begin cpl <= rfoRnn[7:0]; ret(); end
5411
        12'h012:  begin tr <= rfoRnn; ret(); end
5412
        12'h013:  begin tcba <= rfoRnn; ret(); end
5413
        12'h014:        begin mmus <= rfoRnn; ret(); end
5414
        12'h015:        begin ios <= rfoRnn; ret(); end
5415
        12'h016:        begin iops <= rfoRnn; ret(); end
5416 2 robfinch
        12'h800:        begin usp <= rfoRnn; ret(); end
5417
        12'h801:        begin vbr <= rfoRnn; ret(); end
5418
/*
5419
        12'hFE1:
5420
                begin
5421
                        cf <= rfoRnn[0];
5422
                        vf <= rfoRnn[1];
5423
                        zf <= rfoRnn[2];
5424
                        nf <= rfoRnn[3];
5425
                        xf <= rfoRnn[4];
5426
                        ccr57 <= rfoRnn[7:5];
5427
                        if (!rtr) begin
5428
                                im[0] <= rfoRnn[8];
5429
                                im[1] <= rfoRnn[9];
5430
                                im[2] <= rfoRnn[10];
5431
                                sr1112 <= rfoRnn[12:11];
5432
                                sf <= rfoRnn[13];
5433
                                sr14 <= rfoRnn[14];
5434
                                tf <= rfoRnn[15];
5435
                                //pl <= rfoRnn[31:24];
5436
                        end
5437
//                      tr <= rfoRnn[23:16];
5438
//                      pl <= rfoRnn[31:24];
5439
                end
5440
*/
5441
        default:        tIllegal();
5442
        endcase
5443
MOVERc2Rn:
5444
        case(imm[11:0])
5445
        12'h000:        begin resL <= sfc; Rt <= imm[15:12]; rfwrL <= 1'b1; ret(); end
5446
        12'h001:        begin resL <= dfc; Rt <= imm[15:12]; rfwrL <= 1'b1; ret(); end
5447
        12'h003:  begin resL <= {24'h0,asid}; Rt <= imm[15:12]; rfwrL <= 1'b1; ret(); end
5448
        12'h010:  begin resL <= apc; Rt <= imm[15:12]; rfwrL <= 1'b1; ret(); end
5449
        12'h011:  begin resL <= {24'h0,cpl}; Rt <= imm[15:12]; rfwrL <= 1'b1; ret(); end
5450
        12'h012:  begin resL <= tr; Rt <= imm[15:12]; rfwrL <= 1'b1; ret(); end
5451
        12'h013:  begin resL <= tcba; Rt <= imm[15:12]; rfwrL <= 1'b1; ret(); end
5452
        12'h014:  begin resL <= mmus; Rt <= imm[15:12]; rfwrL <= 1'b1; ret(); end
5453
        12'h015:  begin resL <= ios; Rt <= imm[15:12]; rfwrL <= 1'b1; ret(); end
5454
        12'h016:  begin resL <= iops; Rt <= imm[15:12]; rfwrL <= 1'b1; ret(); end
5455
        12'h800:        begin resL <= usp; Rt <= imm[15:12]; rfwrL <= 1'b1; ret(); end
5456
        12'h801:        begin resL <= vbr; Rt <= imm[15:12]; rfwrL <= 1'b1; ret(); end
5457
        12'hFE0:        begin resL <= coreno_i; Rt <= imm[15:12]; rfwrL <= 1'b1; ret(); end
5458
//      12'hFE1:        begin resL <= srx; Rt <= imm[15:12]; rfwrL <= 1'b1; ret(); end
5459
        12'hFF0:        begin resL <= tick; Rt <= imm[15:12]; rfwrL <= 1'b1; ret(); end
5460
        12'hFF8:        begin resL <= icnt; Rt <= imm[15:12]; rfwrL <= 1'b1; ret(); end
5461
        default:        tIllegal();
5462
        endcase
5463
 
5464
BIN2BCD1:
5465
        goto (BIN2BCD2);
5466
BIN2BCD2:
5467
        if (dd32done) begin
5468
                zf <= dd32in==32'h0;
5469
                vf <= dd32out[39:32]!=8'h00;
5470
                resL <= dd32out[31:0];
5471
                rfwrL <= 1'b1;
5472
                Rt <= {1'b0,rrr};
5473
                ret();
5474
        end
5475
BCD2BIN1:
5476
        begin
5477
                (* USE_DSP = "no" *)
5478
                resL1 <= d[3:0] +
5479
                     d[7:4] * 4'd10 +
5480
                     d[11:8] * 7'd100 +
5481
                     d[15:12] * 10'd1000 +
5482
                     d[19:16] * 14'd10000 +
5483
                     d[23:20] * 17'd100000 +
5484
                     d[27:24] * 20'd1000000 +
5485
                     d[31:28] * 24'd10000000
5486
                     ;
5487
                goto (BCD2BIN2);
5488
        end
5489
BCD2BIN2:
5490
        begin
5491
                resL2 <= resL1;
5492
                goto (BCD2BIN3);
5493
        end
5494
BCD2BIN3:
5495
        begin
5496
                resL <= resL2;
5497
                rfwrL <= 1'b1;
5498
                Rt <= {1'b0,rrr};
5499
                ret();
5500
        end
5501
default:
5502
        goto(RESET);
5503
endcase
5504
 
5505
        // Bus error: abort current cycle and trap.
5506
        if (cyc_o & err_i) begin
5507
                cyc_o <= `LOW;
5508
                stb_o <= `LOW;
5509
                we_o <= `LOW;
5510
                sel_o <= 4'h0;
5511
                mac_cycle_type <= {state[6:0],sel_o,~we_o,1'b0,fc_o};
5512
                bad_addr <= adr_o;
5513
                if (state != INTA) begin
5514
                        is_bus_err <= 1'b1;
5515
                        dati_buf <= dat_i;
5516
                        dato_buf <= dat_o;
5517
                        goto (TRAP);
5518
                end
5519
        end
5520
 
5521
`ifdef SUPPORT_RETRY
5522
        // Retry: abort current cycle and retry.
5523
        if (cyc_o & rty_i) begin
5524
                cyc_o <= `LOW;
5525
                stb_o <= `LOW;
5526
                we_o <= `LOW;
5527
                sel_o <= 4'h0;
5528
                rstate <= state;
5529
                goto (RETRY);
5530
        end
5531
`endif
5532
 
5533
end
5534
 
5535
//-----------------------------------------------------------------------------
5536
//-----------------------------------------------------------------------------
5537
task fs_data;
5538
input [2:0] mmm;
5539
input [2:0] rrr;
5540
input state_t size_state;
5541
input dsi;
5542
begin
5543
        ds <= dsi;
5544
        case(mmm)
5545
        3'd0:   begin
5546
                                if (dsi==D)
5547
                                        d <= MMMRRR ? (mmm[0] ? rfoAna : rfoDn) : rfob;
5548
                                else
5549
                                        s <= MMMRRR ? (mmm[0] ? rfoAna : rfoDn) : rfob;
5550
                                case(size_state)
5551
                                STORE_LWORD:
5552
                                        begin
5553
                                                Rt <= {mmm[0],rrr};
5554
                                                rfwrL <= 1'b1;
5555
                                        end
5556
                                STORE_WORD:
5557
                                        begin
5558
                                                Rt <= {mmm[0],rrr};
5559
                                                rfwrW <= 1'b1;
5560
                                        end
5561
                                STORE_BYTE:
5562
                                        begin
5563
                                                Rt <= {mmm[0],rrr};
5564
                                                rfwrB <= 1'b1;
5565
                                        end
5566
                                default:        ;
5567
                                endcase
5568
                                goto(RETSTATE);
5569
                        end     // Dn
5570
        3'd1:   begin
5571
                                if (dsi==D)
5572
                                        d <= rfob;
5573
                                else
5574
                                        s <= rfob;
5575
                                case(size_state)
5576
                                STORE_LWORD:
5577
                                        begin
5578
                                                Rt <= {mmm[0],rrr};
5579
                                                rfwrL <= 1'b1;
5580
                                        end
5581
                                STORE_WORD:
5582
                                        begin
5583
                                                Rt <= {mmm[0],rrr};
5584
                                                rfwrW <= 1'b1;
5585
                                        end
5586
                                STORE_BYTE:
5587
                                        begin
5588
                                                Rt <= {mmm[0],rrr};
5589
                                                rfwrB <= 1'b1;
5590
                                        end
5591
                                default:        ;
5592
                                endcase
5593
                                goto(RETSTATE);
5594
                                end     // An
5595
        3'd2:   begin   //(An)
5596
                                ea <= MMMRRR ? rfoAna : rfoAn;
5597
                                goto(size_state);
5598
                        end
5599
        3'd3:   begin   // (An)+
5600
                                ea <= (MMMRRR ? rfoAna : rfoAn);
5601
                                if (!lea) begin
5602
                                        Rt <= {1'b1,rrr};
5603
                                        rfwrL <= 1'b1;
5604
                                end
5605
                                case(size_state)
5606
                                LFETCH_BYTE,FETCH_BYTE,STORE_BYTE,USTORE_BYTE:  resL <= (MMMRRR ? rfoAna : rfoAn) + 4'd1;
5607
                                FETCH_WORD,STORE_WORD:  resL <= (MMMRRR ? rfoAna : rfoAn) + 4'd2;
5608
                                FETCH_LWORD,STORE_LWORD:        resL <= (MMMRRR ? rfoAna : rfoAn) + 4'd4;
5609
                                default:        ;
5610
                                endcase
5611
                                goto(size_state);
5612
                        end
5613
        3'd4:   begin   // -(An)
5614
                                if (!lea) begin
5615
                                        Rt <= {1'b1,rrr};
5616
                                        rfwrL <= 1'b1;
5617
                                end
5618
                                case(size_state)
5619
                                FETCH_NOP_BYTE,LFETCH_BYTE,FETCH_BYTE,STORE_BYTE,USTORE_BYTE:   ea <= (MMMRRR ? rfoAna : rfoAn) - 4'd1;
5620
                                FETCH_NOP_WORD,FETCH_WORD,STORE_WORD:   ea <= (MMMRRR ? rfoAna : rfoAn) - 4'd2;
5621
                                FETCH_NOP_LWORD,FETCH_LWORD,STORE_LWORD:        ea <= (MMMRRR ? rfoAna : rfoAn) - 4'd4;
5622
                                default:        ;
5623
                                endcase
5624
                                case(size_state)
5625
                                LFETCH_BYTE,FETCH_BYTE,STORE_BYTE,USTORE_BYTE:  resL <= (MMMRRR ? rfoAna : rfoAn) - 4'd1;
5626
                                FETCH_WORD,STORE_WORD:  resL <= (MMMRRR ? rfoAna : rfoAn) - 4'd2;
5627
                                FETCH_LWORD,STORE_LWORD:        resL <= (MMMRRR ? rfoAna : rfoAn) - 4'd4;
5628
                                default:        ;
5629
                                endcase
5630
                                goto(size_state);
5631
                        end
5632
        3'd5:   begin   // d16(An)
5633
                                ea <= (MMMRRR ? rfoAna : rfoAn);
5634
                                mmmx <= mmm;
5635
                                rrrx <= rrr;
5636
                                sz_state <= size_state;
5637
                                dsix <= dsi;
5638
                                goto (FSDATA2);
5639
                        end
5640
        3'd6:   begin   // d8(An,Xn)
5641
                                ea <= (MMMRRR ? rfoAna : rfoAn);
5642
                                mmmx <= mmm;
5643
                                rrrx <= rrr;
5644
                                sz_state <= size_state;
5645
                                dsix <= dsi;
5646
                                goto (FSDATA2);
5647
                        end
5648
        3'd7:   begin
5649
                                case(rrr)
5650
                                3'd0:   begin   // abs short
5651
                                                        ea <= 32'd0;
5652
                                                        mmmx <= mmm;
5653
                                                        rrrx <= rrr;
5654
                                                        sz_state <= size_state;
5655
                                                        dsix <= dsi;
5656
                                                        goto (FSDATA2);
5657
                                                end
5658
                                3'd1:   begin   // abs long
5659
                                                        ea <= 32'd0;
5660
                                                        mmmx <= mmm;
5661
                                                        rrrx <= rrr;
5662
                                                        sz_state <= size_state;
5663
                                                        dsix <= dsi;
5664
                                                        goto (FSDATA2);
5665
                                                end
5666
                                3'd2:   begin   // d16(PC)
5667
                                                        ea <= pc;
5668
                                                        mmmx <= mmm;
5669
                                                        rrrx <= rrr;
5670
                                                        sz_state <= size_state;
5671
                                                        dsix <= dsi;
5672
                                                        goto (FSDATA2);
5673
                                                end
5674
                                3'd3:   begin   // d8(PC,Xn)
5675
                                                        ea <= pc;
5676
                                                        mmmx <= mmm;
5677
                                                        rrrx <= rrr;
5678
                                                        sz_state <= size_state;
5679
                                                        dsix <= dsi;
5680
                                                        goto (FSDATA2);
5681
                                                end
5682
                                3'd4:   begin   // #i16
5683
                                                        goto((size_state==FETCH_LWORD||size_state==FETCH_NOP_LWORD)?FETCH_IMM32:FETCH_IMM16);
5684
                                                end
5685
                                3'd5:   begin   // #i32
5686
                                                        state <= FETCH_IMM32;
5687
                                                        goto (FETCH_IMM32);
5688
                                                end
5689
                                endcase
5690
                        end
5691
                endcase
5692
        end
5693
endtask
5694
 
5695
task fs_data2;
5696
input [2:0] mmm;
5697
input [2:0] rrr;
5698
input state_t size_state;
5699
input dsi;
5700
begin
5701
        ds <= dsi;
5702
        case(mmm)
5703
        3'd5:   begin   // d16(An)
5704
                                ea <= (MMMRRR ? rfoAna : rfoAn);
5705
                                call(FETCH_D16,size_state);
5706
                        end
5707
        3'd6:   begin   // d8(An,Xn)
5708
                                ea <= (MMMRRR ? rfoAna : rfoAn);
5709
                                call(FETCH_NDX,size_state);
5710
                        end
5711
        3'd7:   begin
5712
                                case(rrr)
5713
                                3'd0:   begin   // abs short
5714
                                                        ea <= 32'd0;
5715
                                                        call(FETCH_D16,size_state);
5716
                                                end
5717
                                3'd1:   begin   // abs long
5718
                                                        ea <= 32'd0;
5719
                                                        call(FETCH_D32,size_state);
5720
                                                end
5721
                                3'd2:   begin   // d16(PC)
5722
                                                        ea <= pc;
5723
                                                        call(FETCH_D16,size_state);
5724
                                                end
5725
                                3'd3:   begin   // d8(PC,Xn)
5726
                                                        ea <= pc;
5727
                                                        call(FETCH_NDX,size_state);
5728
                                                end
5729
                                3'd4:   begin   // #i16
5730
                                                        goto((size_state==FETCH_LWORD||size_state==FETCH_NOP_LWORD)?FETCH_IMM32:FETCH_IMM16);
5731
                                                        end
5732
                                3'd5:   begin   // #i32
5733
                                                        state <= FETCH_IMM32;
5734
                                                        goto (FETCH_IMM32);
5735
                                                end
5736
                                endcase
5737
                        end
5738
                endcase
5739
        end
5740
endtask
5741
 
5742
task goto;
5743
input state_t nst;
5744
begin
5745
        state <= nst;
5746
end
5747
endtask
5748
 
5749
task gosub;
5750
input state_t tgt;
5751
begin
5752
        state_stk1 <= state;
5753
        state_stk2 <= state_stk1;
5754
        state_stk3 <= state_stk2;
5755
        state_stk4 <= state_stk3;
5756
        state <= tgt;
5757
end
5758
endtask
5759
 
5760
task call;
5761
input state_t tgt;
5762
input state_t retst;
5763
begin
5764
        state_stk1 <= retst;
5765
        state_stk2 <= state_stk1;
5766
        state_stk3 <= state_stk2;
5767
        state_stk4 <= state_stk3;
5768
        state <= tgt;
5769
end
5770
endtask
5771
 
5772
task push;
5773
input state_t st;
5774
begin
5775
        state_stk1 <= st;
5776
        state_stk2 <= state_stk1;
5777
        state_stk3 <= state_stk2;
5778
        state_stk4 <= state_stk3;
5779
end
5780
endtask
5781
 
5782
task tIllegal;
5783
begin
5784
        is_illegal <= 1'b1;
5785
  vecno <= `ILLEGAL_VEC;
5786
  goto (TRAP);
5787
end
5788
endtask
5789
 
5790
task tPrivilegeViolation;
5791
begin
5792
        is_priv <= 1'b1;
5793
        vecno <= `PRIV_VEC;
5794
        goto (TRAP);
5795
end
5796
endtask
5797
 
5798
task tBadBranchDisp;
5799
begin
5800
        isr <= srx;
5801
        tf <= 1'b0;
5802
        sf <= 1'b1;
5803
        vecno <= `DISP_VEC;
5804
        goto (TRAP3);
5805
end
5806
endtask
5807
 
5808
// MMMRRR needs to be set already when the STORE_IN_DEST state is entered.
5809
// This state is entered after being popped off the state stack.
5810
// If about to fetch the next instruction and trace is enabled, then take the
5811
// trace trap.
5812
task ret;
5813
begin
5814
        if (state_stk1==STORE_IN_DEST ||
5815
                        state_stk1==ADDX2 ||
5816
                        state_stk1==SUBX2 ||
5817
                        state_stk1==BCD0 ||
5818
                        state_stk1==CMPM)
5819
                MMMRRR <= 1'b1;
5820
        if (state_stk1==IFETCH && tf) begin
5821
                is_trace <= 1'b1;
5822
                state <= TRAP;
5823
        end
5824
        else
5825
                state <= state_stk1;
5826
        state_stk1 <= state_stk2;
5827
        state_stk2 <= state_stk3;
5828
        state_stk3 <= state_stk4;
5829
end
5830
endtask
5831
 
5832
endmodule
5833
 

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