Subversion Repositories rf68000

`timescale 1ns / 1ps

// ============================================================================

//        __

//   \\__/ o\    (C) 2016-2022  Robert Finch, Waterloo

//    \  __ /    All rights reserved.

//     \/_//     robfinch@finitron.ca

//       ||

//

//      rf68000_mmu.sv

//

//

// BSD 3-Clause License

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// modification, are permitted provided that the following conditions are met:

//

// 1. Redistributions of source code must retain the above copyright notice, this

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//    this list of conditions and the following disclaimer in the documentation

//    and/or other materials provided with the distribution.

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// ============================================================================

//

`define LOW     1'b0

`define HIGH    1'b1

module rf68000_mmu(rst_i, clk_i, s_ex_i, s_cs_i, s_cyc_i, s_stb_i, s_ack_o, s_we_i,

                s_asid_i, s_adr_i, s_dat_i, s_dat_o,

    pea_o, cyc_o, stb_o, we_o, pdat_o,

    exv_o, rdv_o, wrv_o);

input rst_i;

input clk_i;

input s_ex_i;           // executable address

input s_cs_i;

input s_cyc_i;

input s_stb_i;

input s_we_i;           // write strobe

output s_ack_o;

input [7:0] s_asid_i;

input [31:0] s_adr_i;    // virtual address

input [31:0] s_dat_i;

output reg [31:0] s_dat_o;

output reg [31:0] pea_o;

output reg cyc_o;

output reg stb_o;

output reg we_o;

output reg [31:0] pdat_o;

output reg exv_o;       // execute violation

output reg rdv_o;       // read violation

output reg wrv_o;       // write violation

wire cs = s_cyc_i && s_stb_i && s_cs_i;

wire [5:0] okey = s_asid_i[5:0];

wire [5:0] akey = s_asid_i[5:0];

ack_gen #(

        .READ_STAGES(3),

        .WRITE_STAGES(0),

        .REGISTER_OUTPUT(1)

) uag1

(

        .rst_i(rst_i),

        .clk_i(clk_i),

        .ce_i(1'b1),

        .i(cs & ~s_we_i),

        .we_i(cs & s_we_i),

        .o(s_ack_o),

        .rid_i(0),

        .wid_i(0),

        .rid_o(),

        .wid_o()

);

reg cyc1,cyc2,stb1,stb2;

wire [17:0] douta;

wire [17:0] doutb;

wire [1:0] wx = doutb[17:16];

always @(posedge clk_i)

  exv_o <= s_ex_i & ~wx[0] & cyc2 & stb2;

always @(posedge clk_i)

  rdv_o <= 1'b0;

always @(posedge clk_i)

  wrv_o <= s_we_i & ~wx[1] & cyc2 & stb2;

wire [14:0] addra = {akey[5:0],s_adr_i[10: 2]};

wire [14:0] addrb = {okey[5:0],s_adr_i[24:16]};

wire clka = clk_i;

wire clkb = clk_i;

wire [17:0] dina = s_dat_i[17:0];

wire [17:0] dinb = 18'h0;

wire ena = cs;

wire enb = 1'b1;

wire wea = s_we_i;

wire web = 1'b0;

   // xpm_memory_tdpram: True Dual Port RAM

   // Xilinx Parameterized Macro, version 2022.2

   xpm_memory_tdpram #(

      .ADDR_WIDTH_A(15),               // DECIMAL

      .ADDR_WIDTH_B(15),               // DECIMAL

      .AUTO_SLEEP_TIME(0),            // DECIMAL

      .BYTE_WRITE_WIDTH_A(18),        // DECIMAL

      .BYTE_WRITE_WIDTH_B(18),        // DECIMAL

      .CASCADE_HEIGHT(0),             // DECIMAL

      .CLOCKING_MODE("common_clock"), // String

      .ECC_MODE("no_ecc"),            // String

      .MEMORY_INIT_FILE("none"),      // String

      .MEMORY_INIT_PARAM("0"),        // String

      .MEMORY_OPTIMIZATION("true"),   // String

      .MEMORY_PRIMITIVE("auto"),      // String

      .MEMORY_SIZE(589824),             // DECIMAL

      .MESSAGE_CONTROL(0),            // DECIMAL

      .READ_DATA_WIDTH_A(18),         // DECIMAL

      .READ_DATA_WIDTH_B(18),         // DECIMAL

      .READ_LATENCY_A(2),             // DECIMAL

      .READ_LATENCY_B(1),             // DECIMAL

      .READ_RESET_VALUE_A("0"),       // String

      .READ_RESET_VALUE_B("0"),       // String

      .RST_MODE_A("SYNC"),            // String

      .RST_MODE_B("SYNC"),            // String

      .SIM_ASSERT_CHK(0),             // DECIMAL; 0=disable simulation messages, 1=enable simulation messages

      .USE_EMBEDDED_CONSTRAINT(0),    // DECIMAL

      .USE_MEM_INIT(1),               // DECIMAL

      .USE_MEM_INIT_MMI(0),           // DECIMAL

      .WAKEUP_TIME("disable_sleep"),  // String

      .WRITE_DATA_WIDTH_A(18),        // DECIMAL

      .WRITE_DATA_WIDTH_B(18),        // DECIMAL

      .WRITE_MODE_A("no_change"),     // String

      .WRITE_MODE_B("no_change"),     // String

      .WRITE_PROTECT(1)               // DECIMAL

   )

   xpm_memory_tdpram_inst (

      .dbiterra(),             // 1-bit output: Status signal to indicate double bit error occurrence

                                       // on the data output of port A.

      .dbiterrb(),             // 1-bit output: Status signal to indicate double bit error occurrence

                                       // on the data output of port A.

      .douta(douta),                   // READ_DATA_WIDTH_A-bit output: Data output for port A read operations.

      .doutb(doutb),                   // READ_DATA_WIDTH_B-bit output: Data output for port B read operations.

      .sbiterra(),             // 1-bit output: Status signal to indicate single bit error occurrence

                                       // on the data output of port A.

      .sbiterrb(),             // 1-bit output: Status signal to indicate single bit error occurrence

                                       // on the data output of port B.

      .addra(addra),                   // ADDR_WIDTH_A-bit input: Address for port A write and read operations.

      .addrb(addrb),                   // ADDR_WIDTH_B-bit input: Address for port B write and read operations.

      .clka(clka),                     // 1-bit input: Clock signal for port A. Also clocks port B when

                                       // parameter CLOCKING_MODE is "common_clock".

      .clkb(clkb),                     // 1-bit input: Clock signal for port B when parameter CLOCKING_MODE is

                                       // "independent_clock". Unused when parameter CLOCKING_MODE is

                                       // "common_clock".

      .dina(dina),                     // WRITE_DATA_WIDTH_A-bit input: Data input for port A write operations.

      .dinb(dinb),                     // WRITE_DATA_WIDTH_B-bit input: Data input for port B write operations.

      .ena(ena),                       // 1-bit input: Memory enable signal for port A. Must be high on clock

                                       // cycles when read or write operations are initiated. Pipelined

                                       // internally.

      .enb(enb),                       // 1-bit input: Memory enable signal for port B. Must be high on clock

                                       // cycles when read or write operations are initiated. Pipelined

                                       // internally.

      .injectdbiterra(1'b0), // 1-bit input: Controls double bit error injection on input data when

                                       // ECC enabled (Error injection capability is not available in

                                       // "decode_only" mode).

      .injectdbiterrb(1'b0), // 1-bit input: Controls double bit error injection on input data when

                                       // ECC enabled (Error injection capability is not available in

                                       // "decode_only" mode).

      .injectsbiterra(1'b0), // 1-bit input: Controls single bit error injection on input data when

                                       // ECC enabled (Error injection capability is not available in

                                       // "decode_only" mode).

      .injectsbiterrb(1'b0), // 1-bit input: Controls single bit error injection on input data when

                                       // ECC enabled (Error injection capability is not available in

                                       // "decode_only" mode).

      .regcea(1'b1),                 // 1-bit input: Clock Enable for the last register stage on the output

                                       // data path.

      .regceb(1'b1),                 // 1-bit input: Clock Enable for the last register stage on the output

                                       // data path.

      .rsta(1'b0),                     // 1-bit input: Reset signal for the final port A output register stage.

                                       // Synchronously resets output port douta to the value specified by

                                       // parameter READ_RESET_VALUE_A.

      .rstb(1'b0),                     // 1-bit input: Reset signal for the final port B output register stage.

                                       // Synchronously resets output port doutb to the value specified by

                                       // parameter READ_RESET_VALUE_B.

      .sleep(1'b0),                   // 1-bit input: sleep signal to enable the dynamic power saving feature.

      .wea(wea),                       // WRITE_DATA_WIDTH_A/BYTE_WRITE_WIDTH_A-bit input: Write enable vector

                                       // for port A input data port dina. 1 bit wide when word-wide writes are

                                       // used. In byte-wide write configurations, each bit controls the

                                       // writing one byte of dina to address addra. For example, to

                                       // synchronously write only bits [15-8] of dina when WRITE_DATA_WIDTH_A

                                       // is 32, wea would be 4'b0010.

      .web(web)                        // WRITE_DATA_WIDTH_B/BYTE_WRITE_WIDTH_B-bit input: Write enable vector

                                       // for port B input data port dinb. 1 bit wide when word-wide writes are

                                       // used. In byte-wide write configurations, each bit controls the

                                       // writing one byte of dinb to address addrb. For example, to

                                       // synchronously write only bits [15-8] of dinb when WRITE_DATA_WIDTH_B

                                       // is 32, web would be 4'b0010.

   );

always_ff @(posedge clk_i)

if (s_cs_i)

        s_dat_o <= {14'h0,douta};

else

        s_dat_o <= 32'h0;

always @(posedge clk_i)

if (rst_i) begin

  cyc_o <= 1'b0;

  stb_o <= 1'b0;

  pea_o <= 32'h0;

  pdat_o <= 'd0;

end

else begin

        pea_o[15: 0] <= s_adr_i[15:0];

        pea_o[31:16] <= doutb[15:0];

        pdat_o <= s_dat_i;

        if (s_cs_i)

                pea_o <= 'd0;

        if (cs) begin

                cyc_o <= 1'b0;

                stb_o <= 1'b0;

        end

        else begin

        cyc_o <= s_cyc_i;

        stb_o <= s_stb_i;

        end

end

always_comb

  we_o <= wx[1] & s_we_i;

endmodule