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[/] [rf68000/] [trunk/] [software/] [vasm/] [cpus/] [rf68000/] [cpu.h] - Blame information for rev 2

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/*
2
** cpu.h Motorola M68k, CPU32 and ColdFire cpu-description header-file
3
** (c) in 2002,2006-2022 by Frank Wille
4
*/
5
 
6
#define BIGENDIAN 1
7
#define LITTLEENDIAN 0
8
#define VASM_CPU_M68K 1
9
#define MNEMOHTABSIZE 0x8000
10
 
11
/* maximum number of operands for one mnemonic */
12
#define MAX_OPERANDS 6
13
 
14
/* maximum number of mnemonic-qualifiers per mnemonic */
15
#define MAX_QUALIFIERS 1
16
 
17
/* maximum number of additional command-line-flags for this cpu */
18
 
19
/* data type to represent a target-address */
20
typedef int32_t taddr;
21
typedef uint32_t utaddr;
22
 
23
/* we support floating point constants */
24
#define FLOAT_PARSER 1
25
 
26
/* instruction extension */
27
#define HAVE_INSTRUCTION_EXTENSION 1
28
typedef struct {
29
  union {
30
    struct {
31
      unsigned char flags;
32
      signed char last_size;
33
      signed char orig_ext;
34
      char unused;
35
    } real;
36
    struct {
37
      struct instruction *next;
38
    } copy;
39
  } un;
40
} instruction_ext;
41
#define IFL_RETAINLASTSIZE    1   /* retain current last_size value */
42
#define IFL_UNSIZED           2   /* instruction had no size extension */
43
 
44
/* we use OPTS atoms for cpu-specific options */
45
#define HAVE_CPU_OPTS 1
46
typedef struct {
47
  int cmd;
48
  int arg;
49
} optcmd;
50
/* optcmd commands - warning: print_cpu_opts() depends on the order! */
51
enum {
52
  OCMD_NOP,
53
  OCMD_CPU,
54
  OCMD_FPU,
55
  OCMD_SDREG,
56
  OCMD_NOOPT,
57
  OCMD_OPTGEN,
58
  OCMD_OPTMOVEM,
59
  OCMD_OPTPEA,
60
  OCMD_OPTCLR,
61
  OCMD_OPTST,
62
  OCMD_OPTLSL,
63
  OCMD_OPTMUL,
64
  OCMD_OPTDIV,
65
  OCMD_OPTFCONST,
66
  OCMD_OPTBRAJMP,
67
  OCMD_OPTJBRA,
68
  OCMD_OPTPC,
69
  OCMD_OPTBRA,
70
  OCMD_OPTDISP,
71
  OCMD_OPTABS,
72
  OCMD_OPTMOVEQ,
73
  OCMD_OPTNMOVQ,
74
  OCMD_OPTQUICK,
75
  OCMD_OPTBRANOP,
76
  OCMD_OPTBDISP,
77
  OCMD_OPTODISP,
78
  OCMD_OPTLEA,
79
  OCMD_OPTLQUICK,
80
  OCMD_OPTIMMADDR,
81
  OCMD_OPTSPEED,
82
  OCMD_OPTSIZE,
83
  OCMD_SMALLCODE,
84
  OCMD_SMALLDATA,
85
  OCMD_OPTWARN,
86
  OCMD_CHKPIC,
87
  OCMD_CHKTYPE,
88
  OCMD_NOWARN
89
};
90
 
91
/* minimum instruction alignment */
92
#define INST_ALIGN 2
93
 
94
/* default alignment for n-bit data */
95
#define DATA_ALIGN(n) ((n<=8)?1:2)
96
 
97
/* operand class for n-bit data definitions */
98
#define DATA_OPERAND(n) m68k_data_operand(n)
99
 
100
/* returns true when instruction is valid for selected cpu */
101
#define MNEMONIC_VALID(n) m68k_available(n)
102
 
103
/* returns true when operand type is optional; may init default operand */
104
#define OPERAND_OPTIONAL(p,t) m68k_operand_optional(p,t)
105
 
106
/* parse cpu-specific directives with label */
107
#define PARSE_CPU_LABEL(l,s) parse_cpu_label(l,s)
108
 
109
/* we define one additional, but internal, unary operation, to count 1-bits */
110
int ext_unary_eval(int,taddr,taddr *,int);
111
int ext_find_base(symbol **,expr *,section *,taddr);
112
#define CNTONES (LAST_EXP_TYPE+1)
113
#define EXT_UNARY_EVAL(t,v,r,c) ext_unary_eval(t,v,r,c)
114
#define EXT_FIND_BASE(b,e,s,p) BASE_ILLEGAL
115
 
116
/* type to store each operand */
117
typedef struct {
118
  signed char mode;
119
  signed char reg;
120
  uint16_t format;            /* used for (d8,An/PC,Rn) and ext.addr.modes */
121
  unsigned char bf_offset;    /* bitfield offset, k-factor or MAC Upper Word */
122
  unsigned char bf_width;     /* bitfield width or MAC-MASK '&' */
123
  int8_t basetype[2];         /* BASE_OK=normal, BASE=PCREL=pc-relative base */
124
  uint32_t flags;
125
  expr *value[2];             /* immediate, abs. or displacem. expression */
126
  /* filled during instruction_size(): */
127
  taddr extval[2];            /* evaluated expression from value[0/1] */
128
  symbol *base[2];            /* symbol base for value[0/1], NULL otherwise */
129
} operand;
130
 
131
/* flags */
132
/* Note: FL_CheckMask bits are used together with optype.flags OTF-bits */
133
#define FL_ExtVal0          1   /* extval[0] is set */
134
#define FL_ExtVal1          2   /* extval[1] is set */
135
#define FL_UsesFormat       4   /* operand uses format word */
136
#define FL_020up            8   /* 020+ addressing mode */
137
#define FL_noCPU32       0x10   /* addressing mode not available for CPU32 */
138
#define FL_BFoffsetDyn   0x20   /* dynamic bitfield offset specified */
139
#define FL_BFwidthDyn    0x40   /* dynamic bitfield width specified */
140
#define FL_DoNotEval     0x80   /* do not evaluate, extval and base are ok */
141
/*#define FL_PossRegList   0x80    parser is not sure if operand is RegList */
142
#define FL_NoOptBase    0x100   /* never optimize base displacement */
143
#define FL_NoOptOuter   0x200   /* never optimize outer displacement */
144
#define FL_NoOpt        0x300   /* never optimize this whole operand */
145
#define FL_ZBase        0x400   /* ZAn base register specified */
146
#define FL_ZIndex       0x800   /* ZRn index register specified */
147
#define FL_BaseReg     0x1000   /* BASEREG expression in exp.value[0] */
148
#define FL_BnReg       0x4000   /* Apollo: Bn register instead of An */
149
#define FL_MAC         0x8000   /* ColdFire MAC specific extensions */
150
#define FL_Bitfield   0x10000   /* operand uses bf_offset/bf_width */
151
#define FL_DoubleReg  0x20000   /* Dm:Dn or (Rm):(Rn), where both registers
152
                                   are put into "reg": 0nnn0mmm */
153
#define FL_KFactor    0x40000   /* k-factor <ea>{#n} or <ea>{Dn}, which
154
                                   can be found in bf_offset */
155
#define FL_FPSpec     0x80000   /* special FPU reg. FPIAR/FPCR/FPSR only */
156
 
157
#define FL_CheckMask  0xfc000   /* bits to check, when comparing with
158
                                   flags from struct optype */
159
 
160
/* addressing modes */
161
#define MODE_Dn           0
162
#define MODE_An           1
163
#define MODE_AnIndir      2
164
#define MODE_AnPostInc    3
165
#define MODE_AnPreDec     4
166
#define MODE_An16Disp     5
167
#define MODE_An8Format    6   /* uses format word */
168
#define MODE_Extended     7   /* reg determines addressing mode */
169
#define MODE_FPn          8   /* FPU register */
170
#define MODE_SpecReg      9   /* reg determines index into SpecRegs */
171
/* reg encodings for MODE_Extended: */
172
#define REG_AbsShort      0
173
#define REG_AbsLong       1
174
#define REG_PC16Disp      2
175
#define REG_PC8Format     3   /* uses format word */
176
#define REG_Immediate     4
177
#define REG_RnList        5   /* An/Dn register list in value[0] */
178
#define REG_FPnList       6   /* FPn register list in value[0] */
179
 
180
/* format word */
181
#define FW_IndexAn        0x8000
182
#define FW_IndexReg_Shift 12
183
#define FW_IndexReg(n)    ((n)<<FW_IndexReg_Shift)
184
#define FW_LongIndex      0x0800
185
#define FW_Scale_Shift    9
186
#define FW_Scale(n)       ((n)<<FW_Scale_Shift)
187
#define FW_FullFormat     0x0100
188
#define FW_BaseSuppress   0x0080
189
#define FW_IndexSuppress  0x0040
190
#define FW_BDSize_Shift   4
191
#define FW_BDSize(n)      ((n)<<FW_BDSize_Shift)
192
#define FW_getBDSize(n)   (((n)>>FW_BDSize_Shift)&3)
193
#define FW_Postindexed    0x0004
194
#define FW_IndSize(n)     (n)
195
#define FW_getIndSize(n)  (n&3)
196
#define FW_None           0
197
#define FW_Null           1
198
#define FW_Word           2
199
#define FW_Long           3
200
#define FW_SizeMask       3
201
 
202
/* register macros */
203
#define REGAn             8
204
#define REGPC             0x10
205
#define REGBn             0x20          /* Apollo only */
206
#define REGZero           0x80
207
#define REGisAn(n)        ((n)&REGAn)
208
#define REGisDn(n)        (!((n)&REGAn))
209
#define REGisPC(n)        ((n)&REGPC)
210
#define REGisZero(n)      ((n)&REGZero)
211
#define REGisBn(n)        ((n)&REGBn)   /* Apollo only */
212
#define REGget(n)         ((n)&(REGAn-1))
213
#define REGgetA(n)        ((n)&(REGPC-1))
214
#define REGext_Shift      8
215
#define REGext(n)         (((n)&0x700)>>REGext_Shift)
216
#define REGscale_Shift    12
217
#define REGscale(n)       (((n)&0x3000)>>REGscale_Shift)
218
 
219
/* MAC scale-factor, stored as value[0] */
220
#define MACSF_None        0
221
#define MACSF_ShiftLeft   1
222
#define MACSF_ShiftRight  3
223
 
224
/* special CPU registers */
225
struct specreg {
226
  char *name;
227
  int code;                  /* -1 means no code, syntax-check only */
228
  uint32_t available;
229
};
230
 
231
 
232
/* extension codes */
233
#define EXT_BYTE          1
234
#define EXT_WORD          2
235
#define EXT_LONG          3
236
#define EXT_SINGLE        4
237
#define EXT_DOUBLE        5
238
#define EXT_EXTENDED      6
239
#define EXT_PACKED        7
240
#define EXT_UPPER         2  /* ColdFire MAC upper register word */
241
#define EXT_LOWER         3  /* ColdFire MAC lower register word */
242
#define EXT_MASK          7
243
 
244
 
245
struct addrmode {
246
  signed char mode;
247
  signed char reg;
248
};
249
 
250
#define AM_Dn 0
251
#define AM_An 1
252
#define AM_AnIndir 2
253
#define AM_AnPostInc 3
254
#define AM_AnPreDec 4
255
#define AM_An16Disp 5
256
#define AM_An8Format 6
257
#define AM_AbsShort 7
258
#define AM_AbsLong 8
259
#define AM_PC16Disp 9
260
#define AM_PC8Format 10
261
#define AM_Immediate 11
262
#define AM_RnList 12
263
#define AM_FPnList 13
264
#define AM_FPn 14
265
#define AM_SpecReg 15
266
 
267
 
268
/* operand types */
269
struct optype {
270
  uint16_t modes;         /* addressing modes allowed (0-15, see above) */
271
  uint32_t flags;
272
  unsigned char first;
273
  unsigned char last;
274
};
275
 
276
/* flags */
277
/* Note: Do not allocate bits from FL_CheckMask! */
278
#define OTF_NOSIZE      1 /* this addr. mode requires no additional bytes */
279
#define OTF_BRANCH      2 /* branch instruction */
280
#define OTF_DATA        4 /* data definition */
281
#define OTF_FLTIMM      8 /* base10 immediate values are floating point */
282
#define OTF_QUADIMM  0x10 /* immediate values are 64 bits */
283
#define OTF_SPECREG  0x20 /* check for special registers during parse */
284
#define OTF_SRRANGE  0x40 /* check range between first/last only */
285
#define OTF_REGLIST  0x80 /* register list required, even when single reg. */
286
#define OTF_MOVCREG 0x100 /* check for MOVEC control registers during parse */
287
#define OTF_CHKREG  0x200 /* compare op. register against first/last */
288
#define OTF_VXRNG2  0x400 /* Apollo AMMX Rn:Rn+1 vector register range */
289
#define OTF_VXRNG4  0x800 /* Apollo AMMX Rn-Rn+3 vector register range */
290
#define OTF_OPT    0x1000 /* optional operand */
291
#define OTF_DBRA   0x2000 /* DBcc branch is always 16 bits, ignores size */
292
 
293
 
294
/* additional mnemonic data */
295
typedef struct {
296
  uint16_t place[MAX_OPERANDS];
297
  uint16_t opcode[2];
298
  uint16_t size;
299
  uint32_t available;
300
} mnemonic_extension;
301
 
302
/* size qualifiers, lowest two bits specify opcode size in words! */
303
#define SIZE_UNSIZED 0
304
#define SIZE_BYTE 0x100
305
#define SIZE_WORD 0x200
306
#define SIZE_LONG 0x400
307
#define SIZE_SINGLE 0x800
308
#define SIZE_DOUBLE 0x1000
309
#define SIZE_EXTENDED 0x2000
310
#define SIZE_PACKED 0x4000
311
#define SIZE_MASK 0x7f00
312
#define SIZE_UNAMBIG 0x8000 /* only a single size allowed for this mnemonic */
313
#define S_CFCHECK 0x80      /* Coldfire: SIZE_LONG only, when mcf set */
314
#define S_QUADDEF 0x80      /* Apollo: prefer SIZE_DOUBLE, when apollo set */
315
#define S_NONE 4
316
#define S_STD S_NONE+4      /* 1st word, bits 6-7 */
317
#define S_STD1 S_STD+4      /* 1st word, bits 6-7, b=1,w=2,l=3  */
318
#define S_HI S_STD1+4       /* 1st word, bits 9-10 */
319
#define S_CAS S_HI+4        /* 1st word, bits 9-10, b=1,w=2,l=3 */
320
#define S_MOVE S_CAS+4      /* move instruction, 1st word bits 12-13 */
321
#define S_WL8 S_MOVE+4      /* w/l flag in 1st word bit 8 */
322
#define S_LW7 S_WL8+4       /* l/w flag in 1st word bit 7 */
323
#define S_WL6 S_LW7+4       /* w/l flag in 1st word bit 6 */
324
#define S_TRAP S_WL6+4      /* 1st word, bits 1-0, w=2, l=3 */
325
#define S_EXT S_TRAP+4      /* 2nd word, bits 6-7 */
326
#define S_FP S_EXT+4        /* 2nd word, bits 12-10 (l=0,s,x,p,w,d,b) */
327
#define S_MAC S_FP+4        /* w/l flag in 2nd word bit 11 */
328
#define S_AMMX S_MAC+4      /* q/w flag in 1st word bit 8 */
329
#define S_OPCODE_SIZE(n) (n&3)
330
#define S_SIZEMODE(n) (n&0x7c)
331
 
332
/* short cuts */
333
#define UNS SIZE_UNSIZED
334
#define B SIZE_BYTE
335
#define W SIZE_WORD
336
#define L SIZE_LONG
337
#define Q SIZE_DOUBLE
338
#define SBW (SIZE_BYTE|SIZE_WORD|SIZE_SINGLE)  /* .s = .b for branches */
339
#define SBWL (SIZE_BYTE|SIZE_WORD|SIZE_LONG|SIZE_SINGLE)
340
#define BW (SIZE_BYTE|SIZE_WORD)
341
#define WL (SIZE_WORD|SIZE_LONG)
342
#define BWL (SIZE_BYTE|SIZE_WORD|SIZE_LONG)
343
#define WQ (SIZE_WORD|SIZE_DOUBLE)
344
#define QW (SIZE_WORD|SIZE_DOUBLE|S_QUADDEF)
345
#define CFWL (SIZE_WORD|SIZE_LONG|S_CFCHECK)
346
#define CFBWL (SIZE_BYTE|SIZE_WORD|SIZE_LONG|S_CFCHECK)
347
#define ANY (SIZE_BYTE|SIZE_WORD|SIZE_LONG|SIZE_SINGLE|SIZE_DOUBLE| \
348
             SIZE_EXTENDED|SIZE_PACKED)
349
#define CFANY (SIZE_BYTE|SIZE_WORD|SIZE_LONG|SIZE_SINGLE|SIZE_DOUBLE)
350
#define FX SIZE_EXTENDED
351
#define FD SIZE_DOUBLE
352
 
353
 
354
/* operand insertion info */
355
struct oper_insert {
356
  unsigned char mode;         /* insert mode (see below) */
357
  unsigned char size;         /* number of bits to insert */
358
  unsigned char pos;          /* bit position for inserted value in stream */
359
  unsigned char flags;
360
  void (*insert)(unsigned char *,struct oper_insert *,operand *);
361
};
362
 
363
/* insert modes */
364
#define M_nop         0       /* do nothing for this operand */
365
#define M_noea        1       /* don't store ea, only extension words */
366
#define M_ea          2       /* insert mode/reg in lowest 6 bits */
367
#define M_high_ea     3       /* insert reg/mode in bits 11-6 (MOVE) */
368
#define M_bfea        4       /* insert std. ea and bitfield offset/width */
369
#define M_kfea        5       /* insert std. ea and k-factor/dest.format */
370
#define M_func        6       /* use insert() function */
371
#define M_branch      7       /* extval0 contains branch label */
372
#define M_val0        8       /* extval0 at specified position */
373
#define M_reg         9       /* insert reg at specified position */
374
/* flags */
375
#define IIF_MASK      1       /* value 2^size is represented by a 0 (M_val0)
376
                                 recognize MASK-flag for MAC instr. (M_ea) */
377
#define IIF_BCC       2       /* Bcc branch, opcode is modified */
378
#define IIF_REVERSE   4       /* store bits in reverse order (M_val0) */
379
#define IIF_NOMODE    8       /* don't store ea mode specifier in opcode */
380
#define IIF_SIGNED   16       /* value is signed (M_val0) */
381
#define IIF_3Q       64       /* MOV3Q: -1 is written as 0 (M_val0) */
382
#define IIF_ABSVAL  128       /* make sure first expr. is absolute (M_func) */
383
/* redefinition for AMMX special registers (M_func) */
384
#define IIF_A         8       /* RegBit 4 to A-bit (bit-position 8) */
385
#define IIF_B         7       /* RegBit 4 to B-bit (bit-position 7) */
386
#define IIF_D         6       /* RegBit 4 to D-bit (bit-position 6) */
387
 
388
 
389
/* CPU models and their type-flags */
390
struct cpu_models {
391
  char name[8];
392
  uint32_t type;
393
};
394
 
395
/* cpu types for availability check - warning: order is important */
396
#define CPUMASK  0x00ffffff
397
#define m68000   0x00000001
398
#define m68010   0x00000002
399
#define m68020   0x00000004
400
#define m68030   0x00000008
401
#define m68040   0x00000010
402
#define m68060   0x00000020
403
#define m68881   0x00000040
404
#define m68882   m68881
405
#define m68851   0x00000080
406
#define cpu32    0x00000100
407
#define mcfa     0x00000200
408
#define mcfaplus 0x00000400
409
#define mcfb     0x00000800
410
#define mcfc     0x00001000
411
#define mcfhwdiv 0x00002000
412
#define mcfmac   0x00004000
413
#define mcfemac  0x00008000
414
#define mcfusp   0x00010000
415
#define mcffpu   0x00020000
416
#define mcfmmu   0x00040000
417
#define ac68080  0x00100000
418
#define mbanked  0x10000000 /* Apollo 68080 Bank Prefix */
419
#define mgas     0x20000000 /* a GNU-as specific mnemonic */
420
#define malias   0x40000000 /* a bad alias which we should warn about */
421
#define mfpu     0x80000000 /* just to check if CP-ID needs to be inserted */
422
 
423
/* handy aliases */
424
#define m68k      (m68000|m68010|m68020|m68030|m68040|m68060)
425
#define apollo    (ac68080)
426
#define mcf       (mcfa|mcfaplus|mcfb|mcfc)
427
#define mcf_all   (mcfa|mcfaplus|mcfb|mcfc|mcfhwdiv|mcfmac|mcfemac|mcfusp|mcffpu|mcfmmu)
428
#define mfloat    (mfpu|m68881|m68882|m68040|m68060|ac68080)
429
#define mmmu      (m68851|m68030|m68040|m68060)
430
#define m68040up  (m68040|m68060|apollo)
431
#define m68030up  (m68030|m68040up)
432
#define m68020up  (m68020|m68030up)
433
#define m68010up  (m68010|cpu32|m68020up)
434
#define m68000up  (m68000|m68010up)
435
 
436
 
437
/* register symbols */
438
#define HAVE_REGSYMS
439
#define REGSYMHTSIZE 256
440
 
441
#define RSTYPE_Dn   0
442
#define RSTYPE_An   1
443
#define RSTYPE_FPn  2
444
#define RSTYPE_Bn   3  /* Apollo only */
445
#define RSTYPE_En   4  /* Apollo only */
446
 
447
 
448
/* MID for a.out format */
449
extern int m68k_mid;
450
#define MID m68k_mid
451
 
452
/* exported functions */
453
int m68k_available(int);
454
int m68k_data_operand(int);
455
int m68k_operand_optional(operand *,int);
456
int parse_cpu_label(char *,char **);

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