| 1 |
2 |
robfinch |
struct addrmode addrmodes[] = {
|
| 2 |
|
|
MODE_Dn,-1, /* 0 */
|
| 3 |
|
|
MODE_An,-1,
|
| 4 |
|
|
MODE_AnIndir,-1,
|
| 5 |
|
|
MODE_AnPostInc,-1,
|
| 6 |
|
|
MODE_AnPreDec,-1,
|
| 7 |
|
|
MODE_An16Disp,-1,
|
| 8 |
|
|
MODE_An8Format,-1, /* 6 */
|
| 9 |
|
|
MODE_Extended,REG_AbsShort, /* 7 */
|
| 10 |
|
|
MODE_Extended,REG_AbsLong,
|
| 11 |
|
|
MODE_Extended,REG_PC16Disp,
|
| 12 |
|
|
MODE_Extended,REG_PC8Format,
|
| 13 |
|
|
MODE_Extended,REG_Immediate,
|
| 14 |
|
|
MODE_Extended,REG_RnList,
|
| 15 |
|
|
MODE_Extended,REG_FPnList, /* 13 */
|
| 16 |
|
|
MODE_FPn,-1,
|
| 17 |
|
|
MODE_SpecReg,-1 /* 15 */
|
| 18 |
|
|
};
|
| 19 |
|
|
|
| 20 |
|
|
|
| 21 |
|
|
/* specregs.h */
|
| 22 |
|
|
enum {
|
| 23 |
|
|
REG_CCR=0,REG_SR,REG_USP,REG_NC,REG_DC,REG_IC,REG_BC,
|
| 24 |
|
|
|
| 25 |
|
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REG_ACC,REG_ACC0,REG_ACC1,REG_ACC2,REG_ACC3,REG_ACCX01,REG_ACCX23,
|
| 26 |
|
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REG_MACSR,REG_MASK,REG_SFLEFT,REG_SFRIGHT,
|
| 27 |
|
|
|
| 28 |
|
|
REG_VX00,REG_VX01,REG_VX02,REG_VX03,REG_VX04,REG_VX05,REG_VX06,REG_VX07,
|
| 29 |
|
|
REG_VX08,REG_VX09,REG_VX10,REG_VX11,REG_VX12,REG_VX13,REG_VX14,REG_VX15,
|
| 30 |
|
|
REG_VX16,REG_VX17,REG_VX18,REG_VX19,REG_VX20,REG_VX21,REG_VX22,REG_VX23,
|
| 31 |
|
|
|
| 32 |
|
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REG_TC,REG_SRP,REG_CRP,REG_DRP,REG_CAL,REG_VAL,REG_SCC,REG_AC,
|
| 33 |
|
|
REG_BAC0,REG_BAC1,REG_BAC2,REG_BAC3,REG_BAC4,REG_BAC5,REG_BAC6,REG_BAC7,
|
| 34 |
|
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REG_BAD0,REG_BAD1,REG_BAD2,REG_BAD3,REG_BAD4,REG_BAD5,REG_BAD6,REG_BAD7,
|
| 35 |
|
|
REG_MMUSR,REG_PSR,REG_PCSR,REG_TT0,REG_TT1,
|
| 36 |
|
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#if 0
|
| 37 |
|
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REG_ACUSR,REG_AC0,REG_AC1,
|
| 38 |
|
|
#endif
|
| 39 |
|
|
|
| 40 |
|
|
/* MOVEC control registers _CTRL */
|
| 41 |
|
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REG_SFC,REG_DFC,REG_CACR,REG_ASID,REG_TC_,
|
| 42 |
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REG_ITT0,REG_ITT1,REG_DTT0,REG_DTT1,
|
| 43 |
|
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REG_IACR0,REG_IACR1,REG_DACR0,REG_DACR1,
|
| 44 |
|
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REG_ACR0,REG_ACR1,REG_ACR2,REG_ACR3,
|
| 45 |
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REG_BUSCR,REG_MMUBAR,
|
| 46 |
|
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REG_STR,REG_STC,REG_STH,REG_STB,REG_MWR,
|
| 47 |
|
|
REG_APC,REG_CPL,REG_TR,REG_TCBA,
|
| 48 |
|
|
REG_MMUS,REG_IOS,RES_IOPS,
|
| 49 |
|
|
REG_USP_,REG_VBR,REG_CAAR,REG_MSP,
|
| 50 |
|
|
REG_ISP,REG_MMUSR_,REG_URP,REG_SRP_,REG_PCR,
|
| 51 |
|
|
REG_CCC,REG_IEP1,REG_IEP2,REG_BPC,REG_BPW,REG_DCH,REG_DCM,
|
| 52 |
|
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REG_ROMBAR,REG_ROMBAR0,REG_ROMBAR1,
|
| 53 |
|
|
REG_RAMBAR,REG_RAMBAR0,REG_RAMBAR1,
|
| 54 |
|
|
REG_MPCR,REG_EDRAMBAR,REG_SECMBAR,REG_MBAR,
|
| 55 |
|
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REG_PCR1U0,REG_PCR1L0,REG_PCR2U0,REG_PCR2L0,REG_PCR3U0,REG_PCR3L0,
|
| 56 |
|
|
REG_PCR1U1,REG_PCR1L1,REG_PCR2U1,REG_PCR2L1,REG_PCR3U1,REG_PCR3L1,
|
| 57 |
|
|
REG_CORENO,REG_SRX,REG_TICK,REG_ICNT
|
| 58 |
|
|
};
|
| 59 |
|
|
#define FIRST_CTRLREG REG_SFC
|
| 60 |
|
|
#define LAST_CTRLREG REG_ICNT
|
| 61 |
|
|
|
| 62 |
|
|
|
| 63 |
|
|
#define _(a,b,c,d,e,f,g,h,i,j,k,l,m,n,o,p) \
|
| 64 |
|
|
((a)|((b)<<1)|((c)<<2)|((d)<<3)|((e)<<4)|((f)<<5)|((g)<<6)|((h)<<7)| \
|
| 65 |
|
|
((i)<<8)|((j)<<9)|((k)<<10)|((l)<<11)|((m)<<12)|((n)<<13)| \
|
| 66 |
|
|
((o)<<14)|((p)<<15))
|
| 67 |
|
|
|
| 68 |
|
|
enum {
|
| 69 |
|
|
OP_D8=1,OP_D16,OP_D32,OP_D64,OP_F32,OP_F64,OP_F96,OP_FPD,
|
| 70 |
|
|
D_,A_,B_,AI,IB,R_,RM,DD,CS,VR2,VB2,VDR2,VDR4,PA,AP,DP,
|
| 71 |
|
|
F_,FF,FR,FPIAR,IM,IQ,QI,IR,BR,DB,AB,VA,M6,RL,FL,FS,
|
| 72 |
|
|
AY,AM,MA,MI,FA,CF,MAQ,CFAM,CM,AL,DA,DN,DI,CFDA,CT,AC,AD,CFAD,
|
| 73 |
|
|
BD,BS,AK,MS,MR,CFMM,CFMN,ND,NI,NJ,NK,BY,BI,BJ,OF_,
|
| 74 |
|
|
_CCR,_SR,_USP,_CACHES,_ACC,_MACSR,_MASK,_CTRL,_ACCX,_AEXT,
|
| 75 |
|
|
_VAL,_FC,_RP_030,_RP_851,_TC,_AC,_M1_B,_BAC,_BAD,_PSR,_PCSR,
|
| 76 |
|
|
_TT,SH,VX,VXR2,VXR4,OVX
|
| 77 |
|
|
};
|
| 78 |
|
|
|
| 79 |
|
|
struct optype optypes[] = {
|
| 80 |
|
|
0,0,0,0,
|
| 81 |
|
|
|
| 82 |
|
|
/* OP_D8 8-bit data */
|
| 83 |
|
|
_(0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0),OTF_DATA,0,0,
|
| 84 |
|
|
|
| 85 |
|
|
/* OP_D16 16-bit data */
|
| 86 |
|
|
_(0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0),OTF_DATA,0,0,
|
| 87 |
|
|
|
| 88 |
|
|
/* OP_D32 32-bit data */
|
| 89 |
|
|
_(0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0),OTF_DATA,0,0,
|
| 90 |
|
|
|
| 91 |
|
|
/* OP_D64 64-bit data */
|
| 92 |
|
|
_(0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0),OTF_DATA|OTF_QUADIMM,0,0,
|
| 93 |
|
|
|
| 94 |
|
|
/* OP_F32 32-bit data */
|
| 95 |
|
|
_(0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0),OTF_DATA|OTF_FLTIMM,0,0,
|
| 96 |
|
|
|
| 97 |
|
|
/* OP_F64 64-bit data */
|
| 98 |
|
|
_(0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0),OTF_DATA|OTF_FLTIMM,0,0,
|
| 99 |
|
|
|
| 100 |
|
|
/* OP_F96 96-bit data */
|
| 101 |
|
|
_(0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0),OTF_DATA|OTF_FLTIMM,0,0,
|
| 102 |
|
|
|
| 103 |
|
|
/* OP_FPD 96-bit data (Packed Decimal) */
|
| 104 |
|
|
_(0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0),OTF_DATA|OTF_FLTIMM,0,0,
|
| 105 |
|
|
|
| 106 |
|
|
/* D_ data register */
|
| 107 |
|
|
_(1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0),0,0,0,
|
| 108 |
|
|
|
| 109 |
|
|
/* A_ address register */
|
| 110 |
|
|
_(0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0),0,0,0,
|
| 111 |
|
|
|
| 112 |
|
|
/* B_ (Apollo) base register */
|
| 113 |
|
|
_(0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0),FL_BnReg,0,0,
|
| 114 |
|
|
|
| 115 |
|
|
/* AI address register indirect */
|
| 116 |
|
|
_(0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0),0,0,0,
|
| 117 |
|
|
|
| 118 |
|
|
/* IB (Apollo) base register indirect */
|
| 119 |
|
|
_(0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0),FL_BnReg,0,0,
|
| 120 |
|
|
|
| 121 |
|
|
/* R_ any data or address register */
|
| 122 |
|
|
_(1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0),0,0,0,
|
| 123 |
|
|
|
| 124 |
|
|
/* RM any data or address register with optional U/L extension (MAC) */
|
| 125 |
|
|
_(1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0),FL_MAC,0,0,
|
| 126 |
|
|
|
| 127 |
|
|
/* DD double data register */
|
| 128 |
|
|
_(1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0),FL_DoubleReg,0,0,
|
| 129 |
|
|
|
| 130 |
|
|
/* CS any double data or address register indirect (cas2) */
|
| 131 |
|
|
_(0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0),FL_DoubleReg,0,0,
|
| 132 |
|
|
|
| 133 |
|
|
/* VR2 (Apollo) Rn:Rn+1 */
|
| 134 |
|
|
_(1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0),OTF_VXRNG2|FL_DoubleReg,0,0,
|
| 135 |
|
|
|
| 136 |
|
|
/* VB2 (Apollo) Bn:Bn+1 */
|
| 137 |
|
|
_(0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0),OTF_VXRNG2|FL_BnReg|FL_DoubleReg,0,0,
|
| 138 |
|
|
|
| 139 |
|
|
/* VDR2 (Apollo) Dn:Dn+1 */
|
| 140 |
|
|
_(1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0),OTF_VXRNG2|FL_DoubleReg,0,0,
|
| 141 |
|
|
|
| 142 |
|
|
/* VDR4 (Apollo) Dn-Dn+3 */
|
| 143 |
|
|
_(1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0),OTF_VXRNG4,0,0,
|
| 144 |
|
|
|
| 145 |
|
|
/* PA address register indirect with predecrement */
|
| 146 |
|
|
_(0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0),0,0,0,
|
| 147 |
|
|
|
| 148 |
|
|
/* AP address register indirect with postincrement */
|
| 149 |
|
|
_(0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0),0,0,0,
|
| 150 |
|
|
|
| 151 |
|
|
/* DP address register indirect with displacement (movep) */
|
| 152 |
|
|
_(0,0,1,0,0,1,0,0,0,0,0,0,0,0,0,0),0,0,0,
|
| 153 |
|
|
|
| 154 |
|
|
/* F_ FPU register FPn */
|
| 155 |
|
|
_(0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0),0,0,0,
|
| 156 |
|
|
|
| 157 |
|
|
/* FF double FPU register */
|
| 158 |
|
|
_(0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0),FL_DoubleReg,0,0,
|
| 159 |
|
|
|
| 160 |
|
|
/* FR FPU special register FPCR/FPSR/FPIAR */
|
| 161 |
|
|
_(0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0),FL_FPSpec,0,0,
|
| 162 |
|
|
|
| 163 |
|
|
/* FPIAR FPU special register FPIAR */
|
| 164 |
|
|
_(0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0),OTF_CHKREG|FL_FPSpec,1,1,
|
| 165 |
|
|
|
| 166 |
|
|
/* IM immediate data */
|
| 167 |
|
|
_(0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0),0,0,0,
|
| 168 |
|
|
|
| 169 |
|
|
/* IQ immediate quad data */
|
| 170 |
|
|
_(0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0),OTF_QUADIMM,0,0,
|
| 171 |
|
|
|
| 172 |
|
|
/* QI quick immediate data (moveq, addq, subq) */
|
| 173 |
|
|
_(0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0),OTF_NOSIZE,0,0,
|
| 174 |
|
|
|
| 175 |
|
|
/* IR immediate register list value (movem) */
|
| 176 |
|
|
_(0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0),OTF_NOSIZE,0,0,
|
| 177 |
|
|
|
| 178 |
|
|
/* BR branch destination */
|
| 179 |
|
|
_(0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0),OTF_BRANCH,0,0,
|
| 180 |
|
|
|
| 181 |
|
|
/* DB DBcc branch destination (always 16 bits) */
|
| 182 |
|
|
_(0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0),OTF_DBRA,0,0,
|
| 183 |
|
|
|
| 184 |
|
|
/* AB absolute long destination */
|
| 185 |
|
|
_(0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0),0,0,0,
|
| 186 |
|
|
|
| 187 |
|
|
/* VA absolute value */
|
| 188 |
|
|
_(0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0),OTF_NOSIZE,0,0,
|
| 189 |
|
|
|
| 190 |
|
|
/* M6 mode 6 - addr. reg. indirect with index and displacement */
|
| 191 |
|
|
_(0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0),0,0,0,
|
| 192 |
|
|
|
| 193 |
|
|
/* RL An/Dn register list */
|
| 194 |
|
|
_(0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0),OTF_REGLIST,0,0,
|
| 195 |
|
|
|
| 196 |
|
|
/* FL FPn register list */
|
| 197 |
|
|
_(0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0),OTF_REGLIST,0,0,
|
| 198 |
|
|
|
| 199 |
|
|
/* FS FPIAR/FPSR/FPCR register list */
|
| 200 |
|
|
_(0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0),OTF_REGLIST|FL_FPSpec,0,0,
|
| 201 |
|
|
|
| 202 |
|
|
/* ea addressing modes */
|
| 203 |
|
|
/* AY all addressing modes 0-6,7.0-4 */
|
| 204 |
|
|
_(1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0),0,0,0,
|
| 205 |
|
|
|
| 206 |
|
|
/* AM alterable memory 2-6,7.0-1 */
|
| 207 |
|
|
_(0,0,1,1,1,1,1,1,1,0,0,0,0,0,0,0),0,0,0,
|
| 208 |
|
|
|
| 209 |
|
|
/* MA memory addressing modes 2-6,7.0-4 */
|
| 210 |
|
|
_(0,0,1,1,1,1,1,1,1,1,1,1,0,0,0,0),0,0,0,
|
| 211 |
|
|
|
| 212 |
|
|
/* MI memory addressing modes 2-6,7.0-3 without immediate */
|
| 213 |
|
|
_(0,0,1,1,1,1,1,1,1,1,1,0,0,0,0,0),0,0,0,
|
| 214 |
|
|
|
| 215 |
|
|
/* FA memory addressing modes 2-6,7.0-4 with float immediate */
|
| 216 |
|
|
_(0,0,1,1,1,1,1,1,1,1,1,1,0,0,0,0),OTF_FLTIMM,0,0,
|
| 217 |
|
|
|
| 218 |
|
|
/* CF (ColdFire) float addressing modes 2-5 and 7.2 */
|
| 219 |
|
|
_(0,0,1,1,1,1,0,0,0,1,0,0,0,0,0,0),0,0,0,
|
| 220 |
|
|
|
| 221 |
|
|
/* MAQ memory addressing modes 2-6,7.0-4 with 64-bit immediate */
|
| 222 |
|
|
_(0,0,1,1,1,1,1,1,1,1,1,1,0,0,0,0),OTF_QUADIMM,0,0,
|
| 223 |
|
|
|
| 224 |
|
|
/* CFAM (ColdFire) alterable memory 2-5 */
|
| 225 |
|
|
_(0,0,1,1,1,1,0,0,0,0,0,0,0,0,0,0),0,0,0,
|
| 226 |
|
|
|
| 227 |
|
|
/* CM (ColdFire) alterable memory 2-5 with MASK-flag (MAC) */
|
| 228 |
|
|
_(0,0,1,1,1,1,0,0,0,0,0,0,0,0,0,0),FL_MAC,0,0,
|
| 229 |
|
|
|
| 230 |
|
|
/* AL alterable 0-6,7.0-1 */
|
| 231 |
|
|
_(1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0),0,0,0,
|
| 232 |
|
|
|
| 233 |
|
|
/* DA data 0,2-6,7.0-4 */
|
| 234 |
|
|
_(1,0,1,1,1,1,1,1,1,1,1,1,0,0,0,0),0,0,0,
|
| 235 |
|
|
|
| 236 |
|
|
/* DN data, but not immediate 0,2-6,7.0-3 */
|
| 237 |
|
|
_(1,0,1,1,1,1,1,1,1,1,1,0,0,0,0,0),0,0,0,
|
| 238 |
|
|
|
| 239 |
|
|
/* DI data registers and immediate */
|
| 240 |
|
|
_(1,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0),0,0,0,
|
| 241 |
|
|
|
| 242 |
|
|
/* CFDA (ColdFire) float data 0,2-6,7.0-4 (=CF + mode 0) */
|
| 243 |
|
|
_(1,0,1,1,1,1,0,0,0,1,0,0,0,0,0,0),0,0,0,
|
| 244 |
|
|
|
| 245 |
|
|
/* CT control, 2,5-6,7.0-3 */
|
| 246 |
|
|
_(0,0,1,0,0,1,1,1,1,1,1,0,0,0,0,0),0,0,0,
|
| 247 |
|
|
|
| 248 |
|
|
/* AC alterable control, 2,5-6,7.0-1 */
|
| 249 |
|
|
_(0,0,1,0,0,1,1,1,1,0,0,0,0,0,0,0),0,0,0,
|
| 250 |
|
|
|
| 251 |
|
|
/* AD alterable data, 0,2-6,7.0-1 */
|
| 252 |
|
|
_(1,0,1,1,1,1,1,1,1,0,0,0,0,0,0,0),0,0,0,
|
| 253 |
|
|
|
| 254 |
|
|
/* CFAD (ColdFire) alterable data, 0,2-5 */
|
| 255 |
|
|
_(1,0,1,1,1,1,0,0,0,0,0,0,0,0,0,0),0,0,0,
|
| 256 |
|
|
|
| 257 |
|
|
/* BD alterable control or data (bitfield), 0,2,5-6,7.0-1 */
|
| 258 |
|
|
_(1,0,1,0,0,1,1,1,1,0,0,0,0,0,0,0),FL_Bitfield,0,0,
|
| 259 |
|
|
|
| 260 |
|
|
/* BS control or data register (bitfield), 0,2,5-6,7.0-3 */
|
| 261 |
|
|
_(1,0,1,0,0,1,1,1,1,1,1,0,0,0,0,0),FL_Bitfield,0,0,
|
| 262 |
|
|
|
| 263 |
|
|
/* AK alterable memory (incl. k-factor) 2-6,7.0-1 */
|
| 264 |
|
|
_(0,0,1,1,1,1,1,1,1,0,0,0,0,0,0,0),FL_KFactor,0,0,
|
| 265 |
|
|
|
| 266 |
|
|
/* MS save operands, 2,4-6,7.0-1 */
|
| 267 |
|
|
_(0,0,1,0,1,1,1,1,1,0,0,0,0,0,0,0),0,0,0,
|
| 268 |
|
|
|
| 269 |
|
|
/* MR restore operands, 2-3,5-6,7.0-3 */
|
| 270 |
|
|
_(0,0,1,1,0,1,1,1,1,1,1,0,0,0,0,0),0,0,0,
|
| 271 |
|
|
|
| 272 |
|
|
/* CFMM (ColdFire) MOVEM, 2,5 */
|
| 273 |
|
|
_(0,0,1,0,0,1,0,0,0,0,0,0,0,0,0,0),0,0,0,
|
| 274 |
|
|
|
| 275 |
|
|
/* CFMN (ColdFire) FMOVEM src-ea, 2,5,7.2 */
|
| 276 |
|
|
_(0,0,1,0,0,1,0,0,0,1,0,0,0,0,0,0),0,0,0,
|
| 277 |
|
|
|
| 278 |
|
|
/* ND (Apollo) all except Dn, 1-6,7.0-4 */
|
| 279 |
|
|
_(0,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0),0,0,0,
|
| 280 |
|
|
|
| 281 |
|
|
/* NI (Apollo) all except immediate, 0-6,7.0-3 */
|
| 282 |
|
|
_(1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0),0,0,0,
|
| 283 |
|
|
|
| 284 |
|
|
/* NJ (Apollo) all except Dn and immediate, 1-6,7.0-3 */
|
| 285 |
|
|
_(0,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0),0,0,0,
|
| 286 |
|
|
|
| 287 |
|
|
/* NK (Apollo) all except An and immediate, 0,2-6,7.0-3 */
|
| 288 |
|
|
_(1,0,1,1,1,1,1,1,1,1,1,0,0,0,0,0),0,0,0,
|
| 289 |
|
|
|
| 290 |
|
|
/* BY (Apollo) all addressing modes 0-6,7.0-4 with An replaced by Bn */
|
| 291 |
|
|
_(1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0),FL_BnReg,0,0,
|
| 292 |
|
|
|
| 293 |
|
|
/* BI (Apollo) all except immediate, 0-6,7.0-3 with An repl. by Bn */
|
| 294 |
|
|
_(1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0),FL_BnReg,0,0,
|
| 295 |
|
|
|
| 296 |
|
|
/* BJ (Apollo) all except Dn/An & immediate, 0-6,7.0-3, An -> Bn */
|
| 297 |
|
|
_(0,0,1,1,1,1,1,1,1,1,1,0,0,0,0,0),FL_BnReg,0,0,
|
| 298 |
|
|
|
| 299 |
|
|
/* OF_ (Apollo) optional FPU register FPn */
|
| 300 |
|
|
_(0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0),OTF_OPT,0,0,
|
| 301 |
|
|
|
| 302 |
|
|
/* special registers */
|
| 303 |
|
|
/* _CCR */
|
| 304 |
|
|
_(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1),OTF_SPECREG|OTF_CHKREG,REG_CCR,REG_CCR,
|
| 305 |
|
|
/* _SR */
|
| 306 |
|
|
_(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1),OTF_SPECREG|OTF_CHKREG,REG_SR,REG_SR,
|
| 307 |
|
|
/* _USP */
|
| 308 |
|
|
_(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1),OTF_SPECREG|OTF_CHKREG,REG_USP,REG_USP,
|
| 309 |
|
|
/* _CACHES */
|
| 310 |
|
|
_(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1),OTF_SPECREG|OTF_CHKREG,REG_NC,REG_BC,
|
| 311 |
|
|
/* _ACC */
|
| 312 |
|
|
_(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1),OTF_SPECREG|OTF_CHKREG,REG_ACC,REG_ACC,
|
| 313 |
|
|
/* _MACSR */
|
| 314 |
|
|
_(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1),OTF_SPECREG|OTF_CHKREG,REG_MACSR,REG_MACSR,
|
| 315 |
|
|
/* _MASK */
|
| 316 |
|
|
_(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1),OTF_SPECREG|OTF_CHKREG,REG_MASK,REG_MASK,
|
| 317 |
|
|
/* _CTRL */
|
| 318 |
|
|
_(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1),OTF_MOVCREG,FIRST_CTRLREG,LAST_CTRLREG,
|
| 319 |
|
|
/* _ACCX */
|
| 320 |
|
|
_(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1),OTF_SPECREG|OTF_SRRANGE|OTF_CHKREG,
|
| 321 |
|
|
REG_ACC0,REG_ACC3,
|
| 322 |
|
|
/* _AEXT */
|
| 323 |
|
|
_(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1),OTF_SPECREG|OTF_SRRANGE|OTF_CHKREG,
|
| 324 |
|
|
REG_ACCX01,REG_ACCX23,
|
| 325 |
|
|
/* _VAL */
|
| 326 |
|
|
_(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1),OTF_SPECREG|OTF_CHKREG,REG_VAL,REG_VAL,
|
| 327 |
|
|
/* _FC */
|
| 328 |
|
|
_(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1),OTF_MOVCREG|OTF_SRRANGE|OTF_CHKREG,
|
| 329 |
|
|
REG_SFC,REG_DFC,
|
| 330 |
|
|
/* _RP_030 */
|
| 331 |
|
|
_(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1),OTF_SPECREG|OTF_CHKREG,REG_SRP,REG_CRP,
|
| 332 |
|
|
/* _RP_851 */
|
| 333 |
|
|
_(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1),OTF_SPECREG|OTF_CHKREG,REG_SRP,REG_DRP,
|
| 334 |
|
|
/* _TC */
|
| 335 |
|
|
_(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1),OTF_SPECREG|OTF_CHKREG,REG_TC,REG_TC,
|
| 336 |
|
|
/* _AC */
|
| 337 |
|
|
_(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1),OTF_SPECREG|OTF_CHKREG,REG_AC,REG_AC,
|
| 338 |
|
|
/* _M1_B */
|
| 339 |
|
|
_(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1),OTF_SPECREG|OTF_CHKREG,REG_CAL,REG_SCC,
|
| 340 |
|
|
/* _BAC */
|
| 341 |
|
|
_(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1),OTF_SPECREG|OTF_CHKREG,REG_BAC0,REG_BAC7,
|
| 342 |
|
|
/* _BAD */
|
| 343 |
|
|
_(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1),OTF_SPECREG|OTF_CHKREG,REG_BAD0,REG_BAD7,
|
| 344 |
|
|
/* _PSR */
|
| 345 |
|
|
_(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1),OTF_SPECREG|OTF_CHKREG,REG_MMUSR,REG_PSR,
|
| 346 |
|
|
/* _PCSR */
|
| 347 |
|
|
_(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1),OTF_SPECREG|OTF_CHKREG,REG_MMUSR,REG_PCSR,
|
| 348 |
|
|
/* _TT */
|
| 349 |
|
|
_(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1),OTF_SPECREG|OTF_CHKREG,REG_TT0,REG_TT1,
|
| 350 |
|
|
/* SH */
|
| 351 |
|
|
_(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1),OTF_SPECREG|OTF_CHKREG,REG_SFLEFT,REG_SFRIGHT,
|
| 352 |
|
|
/* VX (Apollo) */
|
| 353 |
|
|
_(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1),OTF_SPECREG|OTF_SRRANGE|OTF_CHKREG,REG_VX00,REG_VX23,
|
| 354 |
|
|
/* VXR2 (Apollo) En:En+1 */
|
| 355 |
|
|
_(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1),OTF_SPECREG|OTF_VXRNG2|OTF_SRRANGE|OTF_CHKREG|FL_DoubleReg,REG_VX00,REG_VX23,
|
| 356 |
|
|
/* VXR4 (Apollo) En-En+3 */
|
| 357 |
|
|
_(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1),OTF_SPECREG|OTF_VXRNG4|OTF_SRRANGE|OTF_CHKREG,REG_VX00,REG_VX23,
|
| 358 |
|
|
/* OVX (Apollo) optional En register */
|
| 359 |
|
|
_(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1),OTF_OPT|OTF_SPECREG|OTF_SRRANGE|OTF_CHKREG,REG_VX00,REG_VX23,
|
| 360 |
|
|
};
|
| 361 |
|
|
|
| 362 |
|
|
#undef _
|
| 363 |
|
|
|
| 364 |
|
|
|
| 365 |
|
|
/* special operand insertion functions */
|
| 366 |
|
|
|
| 367 |
|
|
static void write_val(unsigned char *,int,int,taddr,int);
|
| 368 |
|
|
|
| 369 |
|
|
static void insert_cas2(unsigned char *d,struct oper_insert *i,operand *o)
|
| 370 |
|
|
{
|
| 371 |
|
|
uint16_t w1 = (((uint16_t)*(d+2))<<8) | *(d+3);
|
| 372 |
|
|
uint16_t w2 = (((uint16_t)*(d+4))<<8) | *(d+5);
|
| 373 |
|
|
|
| 374 |
|
|
w1 |= (i->size==4 ? o->reg&15 : o->reg&7) << (16-((i->pos-16)+i->size));
|
| 375 |
|
|
w2 |= (o->reg>>4) << (16-((i->pos-16)+i->size));
|
| 376 |
|
|
*(d+2) = w1>>8;
|
| 377 |
|
|
*(d+3) = w1&0xff;
|
| 378 |
|
|
*(d+4) = w2>>8;
|
| 379 |
|
|
*(d+5) = w2&0xff;
|
| 380 |
|
|
}
|
| 381 |
|
|
|
| 382 |
|
|
static void insert_macreg(unsigned char *d,struct oper_insert *i,operand *o)
|
| 383 |
|
|
{
|
| 384 |
|
|
if (i->pos == 4) {
|
| 385 |
|
|
/* special case: MSB is at bit-position 9 */
|
| 386 |
|
|
write_val(d,4,3,o->reg,0);
|
| 387 |
|
|
*(d+1) |= o->mode << 6;
|
| 388 |
|
|
}
|
| 389 |
|
|
else
|
| 390 |
|
|
write_val(d,i->pos,4,(o->mode<<3)+o->reg,0);
|
| 391 |
|
|
if (o->bf_offset) /* .u extension selects upper word, else lower */
|
| 392 |
|
|
*(d+3) |= i->size; /* size holds the U/L mask for this register */
|
| 393 |
|
|
}
|
| 394 |
|
|
|
| 395 |
|
|
static void insert_muldivl(unsigned char *d,struct oper_insert *i,operand *o)
|
| 396 |
|
|
{
|
| 397 |
|
|
unsigned char r = o->reg & 7;
|
| 398 |
|
|
|
| 399 |
|
|
if (o->mode == MODE_An)
|
| 400 |
|
|
r |= REGAn;
|
| 401 |
|
|
*(d+2) |= r << 4;
|
| 402 |
|
|
*(d+3) |= r;
|
| 403 |
|
|
}
|
| 404 |
|
|
|
| 405 |
|
|
static void insert_divl(unsigned char *d,struct oper_insert *i,operand *o)
|
| 406 |
|
|
{
|
| 407 |
|
|
if (o->flags & FL_DoubleReg) {
|
| 408 |
|
|
*(d+2) |= o->reg & 0xf0;
|
| 409 |
|
|
*(d+3) |= o->reg & 0xf;
|
| 410 |
|
|
}
|
| 411 |
|
|
else insert_muldivl(d,i,o);
|
| 412 |
|
|
}
|
| 413 |
|
|
|
| 414 |
|
|
static void insert_tbl(unsigned char *d,struct oper_insert *i,operand *o)
|
| 415 |
|
|
{
|
| 416 |
|
|
*(d+1) |= o->reg & 7;
|
| 417 |
|
|
*(d+3) |= (o->reg & 0x70) >> 4;
|
| 418 |
|
|
}
|
| 419 |
|
|
|
| 420 |
|
|
static void insert_fp(unsigned char *d,struct oper_insert *i,operand *o)
|
| 421 |
|
|
{
|
| 422 |
|
|
*(d+2) |= ((o->reg&7) << 2) | ((o->reg&7) >> 1);
|
| 423 |
|
|
*(d+3) |= (o->reg&1) << 7;
|
| 424 |
|
|
}
|
| 425 |
|
|
|
| 426 |
|
|
static void insert_fpcs(unsigned char *d,struct oper_insert *i,operand *o)
|
| 427 |
|
|
{
|
| 428 |
|
|
*(d+2) |= (o->reg&0x60) >> 5;
|
| 429 |
|
|
*(d+3) |= ((o->reg&0x10) << 3) | (o->reg & 7);
|
| 430 |
|
|
}
|
| 431 |
|
|
|
| 432 |
|
|
static void insert_accx(unsigned char *d,struct oper_insert *i,operand *o)
|
| 433 |
|
|
{
|
| 434 |
|
|
unsigned char v = o->extval[0];
|
| 435 |
|
|
|
| 436 |
|
|
*(d+1) |= (v&1) << 7;
|
| 437 |
|
|
*(d+3) |= (v&2) << 3;
|
| 438 |
|
|
}
|
| 439 |
|
|
|
| 440 |
|
|
static void insert_accx_rev(unsigned char *d,struct oper_insert *i,operand *o)
|
| 441 |
|
|
{
|
| 442 |
|
|
unsigned char v = o->extval[0];
|
| 443 |
|
|
|
| 444 |
|
|
*(d+1) |= ((v&1) ^ 1) << 7;
|
| 445 |
|
|
*(d+3) |= (v&2) << 3;
|
| 446 |
|
|
}
|
| 447 |
|
|
|
| 448 |
|
|
static void insert_ammx(unsigned char *d,struct oper_insert *i,operand *o)
|
| 449 |
|
|
{
|
| 450 |
|
|
unsigned char v = o->extval[0];
|
| 451 |
|
|
|
| 452 |
|
|
write_val(d,i->pos,i->size,v&15,0);
|
| 453 |
|
|
write_val(d,15-(i->flags&15),1,(v&16)!=0,0);
|
| 454 |
|
|
}
|
| 455 |
|
|
|
| 456 |
|
|
/* place to put an operand */
|
| 457 |
|
|
enum {
|
| 458 |
|
|
NOP=0,NEA,SEA,MEA,BEA,KEA,REA,EAM,BRA,DBR,RHI,RLO,RL4,R2H,R2M,R2L,R2P,
|
| 459 |
|
|
FPN,FPM,FMD,C2H,A2M,A2L,AXA,AXB,AXD,AX0,CS1,CS2,CS3,MDL,DVL,TBL,FPS,FPC,
|
| 460 |
|
|
RMM,RMW,RMY,RMX,ACX,ACR,DL8,DL4,D3Q,DL3,CAC,D16,S16,D2R,ELC,EL8,E8R,
|
| 461 |
|
|
EL3,EL4,EM3,EM4,EH3,BAX,FCR,F13,M3Q,MSF,ACW,AHI,ALO,LIN
|
| 462 |
|
|
};
|
| 463 |
|
|
|
| 464 |
|
|
struct oper_insert insert_info[] = {
|
| 465 |
|
|
/* NOP do nothing for this operand (usually a special reg.) */
|
| 466 |
|
|
M_nop,0,0,0,0,
|
| 467 |
|
|
|
| 468 |
|
|
/* NEA don't store effective address, but extension words */
|
| 469 |
|
|
M_noea,0,0,0,0,
|
| 470 |
|
|
|
| 471 |
|
|
/* SEA standard effective address */
|
| 472 |
|
|
M_ea,0,0,0,0,
|
| 473 |
|
|
|
| 474 |
|
|
/* MEA high effective address for MOVE */
|
| 475 |
|
|
M_high_ea,0,0,0,0,
|
| 476 |
|
|
|
| 477 |
|
|
/* BEA std. EA including bitfield offset/width */
|
| 478 |
|
|
M_bfea,0,0,0,0,
|
| 479 |
|
|
|
| 480 |
|
|
/* KEA std. EA including K-factor */
|
| 481 |
|
|
M_kfea,0,0,0,0,
|
| 482 |
|
|
|
| 483 |
|
|
/* REA store only register-part of effective address */
|
| 484 |
|
|
M_ea,0,0,IIF_NOMODE,0,
|
| 485 |
|
|
|
| 486 |
|
|
/* EAM standard effective address with MAC MASK-flag in bit 5 of 2nd word */
|
| 487 |
|
|
M_ea,0,5,IIF_MASK,0,
|
| 488 |
|
|
|
| 489 |
|
|
/* BRA pc-relative branch to label */
|
| 490 |
|
|
M_branch,0,0,IIF_BCC,0,
|
| 491 |
|
|
|
| 492 |
|
|
/* DBR DBcc, FBcc or PBcc branch to label */
|
| 493 |
|
|
M_branch,0,0,0,0,
|
| 494 |
|
|
|
| 495 |
|
|
/* RHI register 3 bits in bits 11-9 */
|
| 496 |
|
|
M_reg,3,4,0,0,
|
| 497 |
|
|
|
| 498 |
|
|
/* RLO register 3 bits in bits 2-0 */
|
| 499 |
|
|
M_reg,3,13,0,0,
|
| 500 |
|
|
|
| 501 |
|
|
/* RL4 register 4 bits in bits 3-0 */
|
| 502 |
|
|
M_reg,4,12,0,0,
|
| 503 |
|
|
|
| 504 |
|
|
/* R2H register 3 bits in 2nd word bits 14-12 */
|
| 505 |
|
|
M_reg,3,17,0,0,
|
| 506 |
|
|
|
| 507 |
|
|
/* R2M register 3 bits in 2nd word bits 8-6 */
|
| 508 |
|
|
M_reg,3,23,0,0,
|
| 509 |
|
|
|
| 510 |
|
|
/* R2L register 3 bits in 2nd word bits 2-0 */
|
| 511 |
|
|
M_reg,3,29,0,0,
|
| 512 |
|
|
|
| 513 |
|
|
/* R2P register 3 bits in 2nd word bits 7-5 */
|
| 514 |
|
|
M_reg,3,24,0,0,
|
| 515 |
|
|
|
| 516 |
|
|
/* FPN register 3 bits in 2nd word bits 9-7 (FPn) */
|
| 517 |
|
|
M_reg,3,22,0,0,
|
| 518 |
|
|
|
| 519 |
|
|
/* FPM register 3 bits in 2nd word bits 12-10 (FPm) */
|
| 520 |
|
|
M_reg,3,19,0,0,
|
| 521 |
|
|
|
| 522 |
|
|
/* FMD register 3 bits in 2nd word bits 6-4 (FMOVE dynamic) */
|
| 523 |
|
|
M_reg,3,25,0,0,
|
| 524 |
|
|
|
| 525 |
|
|
/* C2H register 4 bits in 2nd word bits 15-12 (cmp2,chk2,moves) */
|
| 526 |
|
|
M_reg,4,16,0,0,
|
| 527 |
|
|
|
| 528 |
|
|
/* A2M register 4 bits in 2nd word bits 11-8 (Apollo AMMX) */
|
| 529 |
|
|
M_reg,4,20,0,0,
|
| 530 |
|
|
|
| 531 |
|
|
/* A2L register 4 bits in 2nd word bits 3-0 (Apollo AMMX) */
|
| 532 |
|
|
M_reg,4,28,0,0,
|
| 533 |
|
|
|
| 534 |
|
|
/* AXA vector register field A (Apollo AMMX) */
|
| 535 |
|
|
M_func,4,28,IIF_A|IIF_ABSVAL,insert_ammx,
|
| 536 |
|
|
|
| 537 |
|
|
/* AXB vector register field B (Apollo AMMX) */
|
| 538 |
|
|
M_func,4,16,IIF_B|IIF_ABSVAL,insert_ammx,
|
| 539 |
|
|
|
| 540 |
|
|
/* AXD vector register field D (Apollo AMMX) */
|
| 541 |
|
|
M_func,4,20,IIF_D|IIF_ABSVAL,insert_ammx,
|
| 542 |
|
|
|
| 543 |
|
|
/* AX0 vector register field A in first word (Apollo AMMX) */
|
| 544 |
|
|
M_func,4,12,IIF_A|IIF_ABSVAL,insert_ammx,
|
| 545 |
|
|
|
| 546 |
|
|
/* CS1 register 3 bits for CAS2 bits 2-0 */
|
| 547 |
|
|
M_func,3,29,0,insert_cas2,
|
| 548 |
|
|
|
| 549 |
|
|
/* CS2 register 3 bits for CAS2 bits 8-6 */
|
| 550 |
|
|
M_func,3,23,0,insert_cas2,
|
| 551 |
|
|
|
| 552 |
|
|
/* CS3 register 4 bits for CAS2 (CAS2) bits 15-12 */
|
| 553 |
|
|
M_func,4,16,0,insert_cas2,
|
| 554 |
|
|
|
| 555 |
|
|
/* MDL insert 4 bit reg. Dq/Dl into 2nd word bits 15-12/3-0 */
|
| 556 |
|
|
M_func,0,0,0,insert_muldivl,
|
| 557 |
|
|
|
| 558 |
|
|
/* DVL 4 bit Dq to 2nd word bits 15-12, Dr to bits 3-0 */
|
| 559 |
|
|
M_func,0,0,0,insert_divl,
|
| 560 |
|
|
|
| 561 |
|
|
/* TBL 3 bit Dym to 1st w. bits 2-0, Dyn to 2nd w. 2-0 */
|
| 562 |
|
|
M_func,0,0,0,insert_tbl,
|
| 563 |
|
|
|
| 564 |
|
|
/* FPS 3 bit FPn to 2nd word bits 12-10 (FPm) and 9-7 (FPn) */
|
| 565 |
|
|
M_func,0,0,0,insert_fp,
|
| 566 |
|
|
|
| 567 |
|
|
/* FPC 3 bit FPc to 2nd word bits 2-0, FPs to bits 9-7 */
|
| 568 |
|
|
M_func,0,0,0,insert_fpcs,
|
| 569 |
|
|
|
| 570 |
|
|
/* RMM register 4 bits in bits 3-0, MAC U/L flag in bit 6 of 2nd word */
|
| 571 |
|
|
M_func,0x40,12,0,insert_macreg,
|
| 572 |
|
|
|
| 573 |
|
|
/* RMW register 4 bits in bits 6,11-9, MAC U/L flag in bit 7 of 2nd word */
|
| 574 |
|
|
M_func,0x80,4,0,insert_macreg,
|
| 575 |
|
|
|
| 576 |
|
|
/* RMY register 4 bits in 2nd word bits 3-0, MAC U/L flag in bit 6 */
|
| 577 |
|
|
M_func,0x40,28,0,insert_macreg,
|
| 578 |
|
|
|
| 579 |
|
|
/* RMX register 4 bits in 2nd word bits 15-12, MAC U/L flag in bit 7 */
|
| 580 |
|
|
M_func,0x80,16,0,insert_macreg,
|
| 581 |
|
|
|
| 582 |
|
|
/* ACX 2 bits ACC: MSB in bit 4 of 2nd word, LSB in bit 7 of first word */
|
| 583 |
|
|
M_func,0,0,IIF_ABSVAL,insert_accx,
|
| 584 |
|
|
|
| 585 |
|
|
/* ACR 2 bits ACC: MSB in bit 4 of 2nd word, reversed LSB in bit 7 of first */
|
| 586 |
|
|
M_func,0,0,IIF_ABSVAL,insert_accx_rev,
|
| 587 |
|
|
|
| 588 |
|
|
/* DL8 8-bit data in lo-byte */
|
| 589 |
|
|
M_val0,8,8,IIF_SIGNED,0,
|
| 590 |
|
|
|
| 591 |
|
|
/* DL4 4-bit value in bits 3-0 */
|
| 592 |
|
|
M_val0,4,12,0,0,
|
| 593 |
|
|
|
| 594 |
|
|
/* D3Q addq/subq 3-bit quick data in bits 11-9 */
|
| 595 |
|
|
M_val0,3,4,IIF_MASK,0,
|
| 596 |
|
|
|
| 597 |
|
|
/* DL3 3-bit value in bits 2-0 */
|
| 598 |
|
|
M_val0,3,13,0,0,
|
| 599 |
|
|
|
| 600 |
|
|
/* CAC 2-bit cache field in bits 7-6 */
|
| 601 |
|
|
M_val0,2,8,0,0,
|
| 602 |
|
|
|
| 603 |
|
|
/* D16 16-bit data in 2nd word */
|
| 604 |
|
|
M_val0,16,16,0,0,
|
| 605 |
|
|
|
| 606 |
|
|
/* S16 signed 16-bit data in 2nd word */
|
| 607 |
|
|
M_val0,16,16,IIF_SIGNED,0,
|
| 608 |
|
|
|
| 609 |
|
|
/* D2R 16-bit reversed data in 2nd word (movem predec.) */
|
| 610 |
|
|
M_val0,16,16,IIF_REVERSE,0,
|
| 611 |
|
|
|
| 612 |
|
|
/* ELC 12-bit value in bits 11-0 of 2nd word */
|
| 613 |
|
|
M_val0,12,20,0,0,
|
| 614 |
|
|
|
| 615 |
|
|
/* EL8 8-bit data in lo-byte of extension word (2nd word) */
|
| 616 |
|
|
M_val0,8,24,0,0,
|
| 617 |
|
|
|
| 618 |
|
|
/* E8R 8-bit reversed data in lo-byte of 2nd word (fmovem) */
|
| 619 |
|
|
M_val0,8,24,IIF_REVERSE,0,
|
| 620 |
|
|
|
| 621 |
|
|
/* EL3 3-bit value in bits 2-0 of 2nd word */
|
| 622 |
|
|
M_val0,3,29,0,0,
|
| 623 |
|
|
|
| 624 |
|
|
/* EL4 4-bit value in bits 3-0 of 2nd word */
|
| 625 |
|
|
M_val0,4,28,0,0,
|
| 626 |
|
|
|
| 627 |
|
|
/* EM3 3-bit value in bits 7-5 of 2nd word */
|
| 628 |
|
|
M_val0,3,24,0,0,
|
| 629 |
|
|
|
| 630 |
|
|
/* EM4 4-bit value in bits 8-5 of 2nd word */
|
| 631 |
|
|
M_val0,4,23,0,0,
|
| 632 |
|
|
|
| 633 |
|
|
/* EH3 3-bit value in bits 12-10 of 2nd word */
|
| 634 |
|
|
M_val0,3,19,0,0,
|
| 635 |
|
|
|
| 636 |
|
|
/* BAX 3-bit number of BAC/BAD reg. in bits 4-2 of 2nd word */
|
| 637 |
|
|
M_val0,3,27,0,0,
|
| 638 |
|
|
|
| 639 |
|
|
/* FCR 7-bit ROM offset in bits 6-0 of 2nd word (FMOVECR) */
|
| 640 |
|
|
M_val0,7,25,0,0,
|
| 641 |
|
|
|
| 642 |
|
|
/* F13 13-bit special register mask in bits 12-0 of 2nd word (FMOVEM) */
|
| 643 |
|
|
M_val0,13,19,0,0,
|
| 644 |
|
|
|
| 645 |
|
|
/* M3Q mov3q 3-bit quick data in bits 11-9, -1 is written as 0 */
|
| 646 |
|
|
M_val0,3,4,IIF_3Q,0,
|
| 647 |
|
|
|
| 648 |
|
|
/* MSF 2-bit MAC scale factor in bits 10-9 of 2nd word */
|
| 649 |
|
|
M_val0,2,21,0,0,
|
| 650 |
|
|
|
| 651 |
|
|
/* ACW 2-bit ACC in bits 3-2 of 2nd word */
|
| 652 |
|
|
M_val0,2,28,0,0,
|
| 653 |
|
|
|
| 654 |
|
|
/* AHI 2-bit ACC in bits 10-9 */
|
| 655 |
|
|
M_val0,2,5,0,0,
|
| 656 |
|
|
|
| 657 |
|
|
/* ALO 2-bit ACC in bits 1-0 */
|
| 658 |
|
|
M_val0,2,14,0,0,
|
| 659 |
|
|
|
| 660 |
|
|
/* LIN 12-bit value in bits 0-11 (LINE-A, LINE-F) */
|
| 661 |
|
|
M_val0,12,4,0,0,
|
| 662 |
|
|
};
|
