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[/] [rf6809/] [trunk/] [rtl/] [CmodA7/] [cs02memInterface.sv] - Blame information for rev 18

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1 16 robfinch
// ============================================================================
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//        __
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//   \\__/ o\    (C) 2019-2022  Robert Finch, Waterloo
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//    \  __ /    All rights reserved.
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//     \/_//     robfinch@finitron.ca
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//       ||
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//
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//
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// BSD 3-Clause License
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// 1. Redistributions of source code must retain the above copyright notice, this
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//    list of conditions and the following disclaimer.
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//
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// 2. Redistributions in binary form must reproduce the above copyright notice,
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//    this list of conditions and the following disclaimer in the documentation
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//    and/or other materials provided with the distribution.
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//
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// 3. Neither the name of the copyright holder nor the names of its
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//    contributors may be used to endorse or promote products derived from
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//    this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// ============================================================================
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//
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module cs02memInterface(rst_i, clk_i, cpuclk_i,
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        cs_i, cyc_i, stb_i, ack_o, we_i, adr_i, dat_i, dat_o,
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        RamCEn, RamWEn, RamOEn, MemAdr, MemDBo, MemDBi);
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input rst_i;
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input clk_i;          // 100 MHz
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input cpuclk_i;
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input cs_i;
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input cyc_i;
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input stb_i;
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output ack_o;
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input we_i;
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input [23:0] adr_i;
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input [11:0] dat_i;
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output reg [11:0] dat_o;
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output reg RamCEn;
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output reg RamWEn;
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output reg RamOEn;
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output reg [18:0] MemAdr;
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output reg [7:0] MemDBo;
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input [7:0] MemDBi;
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parameter HIGH = 1'b1;
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parameter LOW = 1'b0;
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reg [3:0] state;
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parameter IDLE = 4'd0;
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parameter WRF1 = 4'd1;
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parameter WRF2 = 4'd2;
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parameter WRF3 = 4'd3;
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parameter WRF4 = 4'd4;
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parameter WRF5 = 4'd5;
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parameter WRF6 = 4'd6;
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parameter WRF7 = 4'd7;
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parameter WRF8 = 4'd8;
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parameter RRF1 = 4'd9;
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parameter RRF2 = 4'd10;
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parameter RRF3 = 4'd11;
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parameter RRF4 = 4'd12;
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wire cs = cs_i & stb_i & cyc_i;
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reg ack;
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wire hit;
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ack_gen #(
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        .READ_STAGES(2),
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        .WRITE_STAGES(1),
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        .REGISTER_OUTPUT(1)
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) uag1
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(
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        .rst_i(rst_i),
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        .clk_i(cpuclk_i),
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        .ce_i(1'b1),
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        .i(cs & hit & ~we_i),
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        .we_i(cs & ack),
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        .o(ack_o),
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        .rid_i(0),
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        .wid_i(0),
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        .rid_o(),
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        .wid_o()
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);
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reg wrc, inv;
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wire [11:0] rdat;
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A709_ReadCache urc1
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(
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        .rst(rst_i),
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        .wclk(clk_i),
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        .wr(wrc),
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        .wa({5'h0,MemAdr[18:0]}),
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        .wd(MemDBi[5:0]),
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        .rclk(cpuclk_i),
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        .ra(adr_i),
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        .rd(rdat),
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        .hit(hit),
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        .inv(inv),
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        .ia(adr_i)
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);
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always_ff @(posedge cpuclk_i)
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if (cs)
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        dat_o <= rdat;
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else
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        dat_o <= 12'h0;
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reg [31:0] ctr; // ring counter
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always_ff @(posedge clk_i)
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if (rst_i) begin
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        state <= IDLE;
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        RamWEn <= HIGH;
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        RamOEn <= HIGH;
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        RamCEn <= HIGH;
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        wrc <= 1'b0;
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        ack <= 1'b0;
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        inv <= 1'b0;
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        ctr <= 33'h1;
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end
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else begin
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wrc <= 1'b0;
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inv <= 1'b0;
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case(state)
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IDLE:
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        begin
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                RamWEn <= HIGH;
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                RamCEn <= HIGH;
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                RamOEn <= HIGH;
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                MemAdr[18:0] <= {adr_i[17:0],1'b0};
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                MemDBo <= {2'b0,dat_i[5:0]};
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                if (cs & we_i) begin
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                        inv <= 1'b1;
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                        RamCEn <= LOW;
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                        state <= WRF1;
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                end
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                // Initiate a read, it might take several cycles before hit goes high,
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                // so test for a hit at each stage.
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                else if (cs & !hit) begin
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                        RamCEn <= LOW;
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                        RamOEn <= LOW;
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                        MemAdr[4:0] <= 5'h0;
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                        ctr <= 33'h1;
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                        state <= RRF1;
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                end
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        end
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WRF1:
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        begin
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                RamWEn <= LOW;
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                state <= WRF2;
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        end
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WRF2:
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        begin
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                state <= WRF3;
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        end
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WRF3:
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        begin
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                RamWEn <= HIGH;
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                state <= WRF4;
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        end
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WRF4:
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        begin
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                MemAdr[0] <= 1'b1;
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                MemDBo <= {2'b0,dat_i[11:6]};
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                state <= WRF5;
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        end
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WRF5:
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        begin
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                RamWEn <= LOW;
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                state <= WRF6;
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        end
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WRF6:
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        begin
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                state <= WRF7;
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        end
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WRF7:
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        begin
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                RamWEn <= HIGH;
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                ack <= 1'b1;
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                state <= WRF8;
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        end
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WRF8:
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        if (!cs) begin
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                ack <= 1'b0;
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                state <= IDLE;
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        end
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RRF1:
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        begin
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                if (hit)
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                        state <= IDLE;
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                else
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                        state <= RRF2;
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        end
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RRF2:
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        begin
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                wrc <= 1'b1;
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                if (hit)
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                        state <= IDLE;
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                else if (ctr[31])
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                        state <= RRF4;
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                else
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                        state <= RRF3;
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        end
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RRF3:
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        begin
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                MemAdr[4:0] <= MemAdr[4:0] + 2'd1;
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                ctr <= {ctr[30:0],ctr[31]};
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                if (hit)
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                        state <= IDLE;
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                else
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                        state <= RRF1;
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        end
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RRF4:
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        begin
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                wrc <= 1'b1;
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                state <= IDLE;
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        end
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default:
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        state <= IDLE;
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endcase
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end
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endmodule
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module A709_ReadCache(rst, wclk, wr, wa, wd, rclk, ra, rd, hit, inv, ia);
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input rst;
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input wclk;
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input wr;
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input [24:0] wa;
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input [5:0] wd;
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input rclk;
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input [23:0] ra;
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output reg [11:0] rd;
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output reg hit;
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input inv;
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input [23:0] ia;
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reg [11:0] mem [0:2047];
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reg [10:0] rra;
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always_ff @(posedge rclk)
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        rra <= ra[10:0];
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always_ff @(posedge rclk)
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        rd <= mem[rra];
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always_ff @(posedge wclk)
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        if (wr & ~wa[0]) mem[wa[11:1]][5:0] <= wd;
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always_ff @(posedge wclk)
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        if (wr &  wa[0]) mem[wa[11:1]][11:6] <= wd;
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reg [19:0] tagmem [127:0];
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reg [127:0] valid;
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reg [23:0] iar;
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reg invr;
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// register onto wclk domain
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always_ff @(posedge wclk)
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        iar <= ia;
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always_ff @(posedge wclk)
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        invr <= inv;
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always_ff @(posedge wclk)
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        if (wr && wa[4:0]==5'h1F)
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                tagmem[wa[11:5]] <= wa[24:5];
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always_ff @(posedge wclk)
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if (rst)
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        valid <= 128'd0;
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else begin
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if (invr)
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        valid[iar[10:4]] <= tagmem[iar[10:4]]!=iar[23:4];
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else if (wr && wa[4:0]==5'h1F)
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        valid[wa[11:5]] <= 1'b1;
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end
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always_ff @(posedge rclk)
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        hit <= valid[ra[10:4]] && tagmem[ra[10:4]]==ra[23:4];
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endmodule

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