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robfinch |
`timescale 1ns / 1ps
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// ============================================================================
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// __
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// \\__/ o\ (C) 2005-2022 Robert Finch, Waterloo
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// \ __ / All rights reserved.
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// \/_// robfinch@finitron.ca
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// ||
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//
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// PS2kbd.v - PS2 compatible keyboard interface
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//
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see .
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//
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//
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// PS2 compatible keyboard / mouse interface
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//
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// This core provides a raw interface to the a PS2
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// keyboard or mouse. The interface is raw in the sense
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// that it doesn't do any scan code processing, it
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// just supplies it to the system. The core uses a
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// WISHBONE compatible bus interface.
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// Both transmit and recieve are
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// supported. It is possible to build the core without
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// the transmitter to reduce the size of the core; however
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// then it would not be possible to control the leds on
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// the keyboard. (The transmitter is required for a mouse
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// interface).
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// There is a 5us debounce circuit on the incoming
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// clock.
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// The transmitter does not have a watchdog timer, so
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// it may cause the keyboard to stop responding if there
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// was a problem with the transmit. It relys on the system
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// to reset the transmitter after 30ms or so of no
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// reponse. Resetting the transmitter should allow the
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// keyboard to respond again.
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// Note: keyboard clock must be at least three times slower
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// than the clk_i input to work reliably.
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// A typical keyboard clock is <30kHz so this should be ok
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// for most systems.
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// * There must be pullup resistors on the keyboard clock
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// and data lines, and the keyboard clock and data lines
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// are assumed to be open collector.
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// To read the keyboard, wait for bit 7 of the status
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// register to be set, then read the transmit / recieve
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// register. Reading the transmit / recieve register clears
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// the keyboard reciever, and allows the next character to
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// be recieved.
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//
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// Reg
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// 0 keyboard transmit/receive register
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// 1 status reg. itk xxxx p
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// i = interrupt status
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// t = transmit complete
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// k = transmit acknowledge receipt (from keyboard)
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// p = parity error
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// A write to the status register clears the transmitter
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// state
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//
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//
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//
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// Webpack 9.1i xc3s1000-4ft256
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// LUTs / slices / MHz
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// block rams
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// multiplier
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//
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// ============================================================================
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// A good source of info:
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// http://panda.stb_i.ndsu.nodak.edu/~achapwes/PICmicro/PS2/ps2.htm
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// http://www.beyondlogic.org/keyboard/keybrd.htm
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//
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// From the keyboard
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// 1 start bit
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// 8 data bits
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// 1 parity bit
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// 1 stop bit
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//
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// +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// |WISHBONE Datasheet
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// |WISHBONE SoC Architecture Specification, Revision B.3
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// |
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// |Description: Specifications:
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// +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// |General Description: PS2 keyboard / mouse interface
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// +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// |Supported Cycles: SLAVE,READ/WRITE
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// | SLAVE,BLOCK READ/WRITE
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// | SLAVE,RMW
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// +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// |Data port, size: 8 bit
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// |Data port, granularity: 8 bit
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// |Data port, maximum operand size: 8 bit
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// |Data transfer ordering: Undefined
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// |Data transfer sequencing: Undefined
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// +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// |Clock frequency constraints: none
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// +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// |Supported signal list and Signal Name WISHBONE equiv.
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// |cross reference to equivalent ack_o ACK_O
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// |WISHBONE signals adr_i ADR_I()
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// | clk_i CLK_I
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// | cyc_i CYC_I
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// | dat_i(7:0) DAT_I()
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// | dat_o(7:0) DAT_O()
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// | stb_i STB_I
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// | we_i WE_I
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// |
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// +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// |Special requirements:
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// +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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//
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//==================================================================
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`define KBD_TX 1 // include transmitter
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`define S_KBDRX_WAIT_CLK 0
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`define S_KBDRX_CHK_CLK_LOW 1
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`define S_KBDRX_CAPTURE_BIT 2
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module PS2kbd(
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// WISHBONE/SoC bus interface
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input rst_i,
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input clk_i, // system clock
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input cs_i,
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input cyc_i,
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input stb_i, // core select (active high)
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output reg ack_o, // bus transfer acknowledged
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input we_i, // I/O write taking place (active high)
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input [3:0] adr_i, // address
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input [11:0] dat_i, // data in
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output reg [11:0] dat_o, // data out
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inout tri [11:0] db,
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//-------------
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output irq, // interrupt request (active high)
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input kclk_i, // keyboard clock from keyboard
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output kclk_en, // 1 = drive clock low
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input kdat_i, // keyboard data
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output kdat_en // 1 = drive data low
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);
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parameter pClkFreq = 40000000;
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parameter pAckStyle = 1'b0;
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parameter p5us = pClkFreq / 200000; // number of clocks for 5us
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parameter p100us = pClkFreq / 10000; // number of clocks for 100us
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reg [13:0] os; // one shot
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wire os_5us_done = os==p5us;
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wire os_100us_done = os==p100us;
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reg [10:0] q; // receive register
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reg tc; // transmit complete indicator
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reg [1:0] s_rx; // keyboard receive state
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reg [7:0] kq;
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reg [15:0] kqc;
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// Use majority logic for bit capture
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// 4 or more bits high = 1, otherwise 0
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wire [2:0] kqs = {2'b0,kq[0]}+
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{2'b0,kq[1]}+
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{2'b0,kq[2]}+
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{2'b0,kq[3]}+
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{2'b0,kq[4]}+
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{2'b0,kq[5]}+
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{2'b0,kq[6]};
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wire kqcne; // negative edge on kqc
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wire kqcpe; // positive edge on kqc
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assign irq = ~q[0];
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reg kack; // keyboard acknowledge bit
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`ifdef KBD_TX
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reg [16:0] tx_state; // transmitter states
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reg klow; // force clock line low
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reg [10:0] t; // transmit register
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wire rx_inh = ~tc; // inhibit receive while transmit occuring
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reg [3:0] bitcnt;
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wire shift_done = bitcnt==0;
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reg tx_oe; // transmitter output enable / shift enable
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`else
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wire rx_inh = 0;
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`endif
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wire cs = cyc_i & stb_i & cs_i;
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//reg ack,ack1;
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//always @(posedge clk_i) begin ack <= cs; ack1 <= ack & cs; end
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always_ff @(posedge clk_i)
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ack_o <= cs ? 1'b1 : pAckStyle;// ? (we_i ? 1'b1 : ack) : 1'b0;
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wire pe_cs;
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edge_det ed1 (.rst(rst_i), .clk(clk_i), .ce(1'b1), .i(cs), .pe(pe_cs), .ne(), .ee() );
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// register read path
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// Latches data on positive edge of the circuit select, as reading the keyboard
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// register triggers a clear of it.
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always_ff @(posedge clk_i)
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if (cs_i)
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case(adr_i[1:0])
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2'd0: dat_o <= {4'h0,q[8:1]};
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2'd1: dat_o <= {4'h0,~q[0],tc,~kack,4'b0,~^q[9:1]};
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2'd2: dat_o <= {4'h0,q[8:1]};
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2'd3: dat_o <= {4'h0,~q[0],tc,~kack,4'b0,~^q[9:1]};
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endcase
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else
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dat_o <= 12'h00;
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assign db = (cs & ~we_i) ? dat_o : {12{1'bz}};
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// Prohibit keyboard device from further transmits until
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// this character has been processed.
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// Holding the clock line low does this.
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//assign kclk = irq ? 1'b0 : 1'bz;
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`ifdef KBD_TX
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// Force clock and data low during transmits
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assign kclk_en = klow | irq;
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assign kdat_en = tx_oe & ~t[0];// ? 1'b0 : 1'bz;
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`else
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assign kclk_en = irq;
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`endif
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// stabilize clock and data
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always_ff @(posedge clk_i) begin
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kq <= {kq[6:0],kdat_i};
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kqc <= {kqc[14:0],kclk_i};
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end
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edge_det ed0 (.rst(rst_i), .clk(clk_i), .ce(1'b1), .i(kqc[10]), .pe(kqcpe), .ne(kqcne), .ee() );
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// The debounce one-shot and 100us timer
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always @(posedge clk_i)
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if (rst_i)
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os <= 0;
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else begin
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if ((s_rx==`S_KBDRX_WAIT_CLK && kqcne && ~rx_inh)||
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(s_rx==`S_KBDRX_CHK_CLK_LOW && rx_inh)
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`ifdef KBD_TX
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||tx_state[0]||tx_state[2]||tx_state[5]||tx_state[7]||tx_state[9]||tx_state[11]||tx_state[14]
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`endif
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)
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os <= 0;
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else
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os <= os + 1;
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end
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// Receive state machine
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always_ff @(posedge clk_i) begin
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if (rst_i) begin
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q <= 11'h7FF;
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s_rx <= `S_KBDRX_WAIT_CLK;
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end
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else begin
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// clear rx on write to status reg
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if (cs && we_i && adr_i[1:0]==2'd1 && dat_i[7:0]==8'h00)
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q <= 11'h7FF;
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// Receive state machine
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case (s_rx) // synopsys full_case parallel_case
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// negedge on kclk ?
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// then set debounce one-shot
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`S_KBDRX_WAIT_CLK:
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if (kqcne && ~rx_inh)
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s_rx <= `S_KBDRX_CHK_CLK_LOW;
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// wait 5us
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// check if clock low
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`S_KBDRX_CHK_CLK_LOW:
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if (rx_inh)
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s_rx <= `S_KBDRX_WAIT_CLK;
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else if (os_5us_done) begin
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// clock low ?
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if (~kqc[10])
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s_rx <= `S_KBDRX_CAPTURE_BIT;
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else
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s_rx <= `S_KBDRX_WAIT_CLK; // no - spurious
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end
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// capture keyboard bit
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// keyboard transmits LSB first
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`S_KBDRX_CAPTURE_BIT:
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begin
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q <= {kq[2],q[10:1]};
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s_rx <= `S_KBDRX_WAIT_CLK;
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end
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default:
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s_rx <= `S_KBDRX_WAIT_CLK;
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endcase
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end
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end
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`ifdef KBD_TX
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// Transmit state machine
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// a shift register / ring counter is used
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reg adv_tx_state; // advance transmitter state
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reg start_tx; // start the transmitter
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reg clear_tx; // clear the transmit state
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always_ff @(posedge clk_i)
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if (rst_i)
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tx_state <= 0;
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else begin
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if (clear_tx)
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tx_state <= 0;
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else if (start_tx)
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tx_state[0] <= 1;
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else if (adv_tx_state) begin
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tx_state[6:0] <= {tx_state[5:0],1'b0};
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tx_state[7] <= (tx_state[8] && !shift_done) || tx_state[6];
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tx_state[8] <= tx_state[7];
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| 318 |
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|
tx_state[9] <= tx_state[8] && shift_done;
|
| 319 |
|
|
tx_state[16:10] <= tx_state[15:9];
|
| 320 |
|
|
end
|
| 321 |
|
|
end
|
| 322 |
|
|
|
| 323 |
|
|
|
| 324 |
|
|
// detect when to advance the transmit state
|
| 325 |
|
|
always_comb
|
| 326 |
|
|
case (1'b1) // synopsys parallel_case
|
| 327 |
|
|
tx_state[0]: adv_tx_state <= 1;
|
| 328 |
|
|
tx_state[1]: adv_tx_state <= os_100us_done;
|
| 329 |
|
|
tx_state[2]: adv_tx_state <= 1;
|
| 330 |
|
|
tx_state[3]: adv_tx_state <= os_5us_done;
|
| 331 |
|
|
tx_state[4]: adv_tx_state <= 1;
|
| 332 |
|
|
tx_state[5]: adv_tx_state <= kqcne;
|
| 333 |
|
|
tx_state[6]: adv_tx_state <= os_5us_done;
|
| 334 |
|
|
tx_state[7]: adv_tx_state <= kqcpe;
|
| 335 |
|
|
tx_state[8]: adv_tx_state <= os_5us_done;
|
| 336 |
|
|
tx_state[9]: adv_tx_state <= kqcpe;
|
| 337 |
|
|
tx_state[10]: adv_tx_state <= os_5us_done;
|
| 338 |
|
|
tx_state[11]: adv_tx_state <= kqcne;
|
| 339 |
|
|
tx_state[12]: adv_tx_state <= os_5us_done;
|
| 340 |
|
|
tx_state[13]: adv_tx_state <= 1;
|
| 341 |
|
|
tx_state[14]: adv_tx_state <= kqcpe;
|
| 342 |
|
|
tx_state[15]: adv_tx_state <= os_5us_done;
|
| 343 |
|
|
default: adv_tx_state <= 0;
|
| 344 |
|
|
endcase
|
| 345 |
|
|
|
| 346 |
|
|
wire load_tx = cs && we_i && adr_i[1:0]==2'b0;
|
| 347 |
|
|
wire shift_tx = (tx_state[7] & kqcpe)|tx_state[4];
|
| 348 |
|
|
|
| 349 |
|
|
// It can take up to 20ms for the keyboard to accept data
|
| 350 |
|
|
// from the host.
|
| 351 |
|
|
always_ff @(posedge clk_i) begin
|
| 352 |
|
|
if (rst_i) begin
|
| 353 |
|
|
klow <= 0;
|
| 354 |
|
|
tc <= 1;
|
| 355 |
|
|
start_tx <= 0;
|
| 356 |
|
|
tx_oe <= 0;
|
| 357 |
|
|
end
|
| 358 |
|
|
else begin
|
| 359 |
|
|
|
| 360 |
|
|
clear_tx <= 0;
|
| 361 |
|
|
start_tx <= 0;
|
| 362 |
|
|
|
| 363 |
|
|
// write to keyboard register triggers whole thing
|
| 364 |
|
|
if (load_tx) begin
|
| 365 |
|
|
start_tx <= 1;
|
| 366 |
|
|
tc <= 0;
|
| 367 |
|
|
end
|
| 368 |
|
|
// write to status register clears transmit state
|
| 369 |
|
|
else if (cs && we_i && adr_i[1:0]==2'd1 && dat_i[7:0]==8'hFF) begin
|
| 370 |
|
|
tc <= 1;
|
| 371 |
|
|
tx_oe <= 0;
|
| 372 |
|
|
klow <= 1'b0;
|
| 373 |
|
|
clear_tx <= 1;
|
| 374 |
|
|
end
|
| 375 |
|
|
else begin
|
| 376 |
|
|
|
| 377 |
|
|
case (1'b1) // synopsys parallel_case
|
| 378 |
|
|
|
| 379 |
|
|
tx_state[0]: klow <= 1'b1; // First step: pull the clock low
|
| 380 |
|
|
tx_state[1]: ; // wait 100 us (hold clock low)
|
| 381 |
|
|
tx_state[2]: tx_oe <= 1; // bring data low / enable shift
|
| 382 |
|
|
tx_state[3]: ; // wait 5us
|
| 383 |
|
|
// at this point the clock should go high
|
| 384 |
|
|
// and shift out the start bit
|
| 385 |
|
|
tx_state[4]: klow <= 0; // release clock line
|
| 386 |
|
|
tx_state[5]: ; // wait for clock to go low
|
| 387 |
|
|
tx_state[6]: ; // wait 5us
|
| 388 |
|
|
// state7, 8 shift the data out
|
| 389 |
|
|
tx_state[7]: ; // wait for clock to go high
|
| 390 |
|
|
tx_state[8]: ; // wait 5us, go back to state 7
|
| 391 |
|
|
tx_state[9]: tx_oe <= 0; // wait for clock to go high // disable transmit output / shift
|
| 392 |
|
|
tx_state[10]: ; // wait 5us
|
| 393 |
|
|
tx_state[11]: ; // wait for clock to go low
|
| 394 |
|
|
tx_state[12]: ; // wait 5us
|
| 395 |
|
|
tx_state[13]: kack <= kq[1]; // capture the ack_o bit from the keyboard
|
| 396 |
|
|
tx_state[14]: ; // wait for clock to go high
|
| 397 |
|
|
tx_state[15]: ; // wait 5us
|
| 398 |
|
|
tx_state[16]:
|
| 399 |
|
|
begin
|
| 400 |
|
|
tc <= 1; // transmit is now complete
|
| 401 |
|
|
clear_tx <= 1;
|
| 402 |
|
|
end
|
| 403 |
|
|
|
| 404 |
|
|
default: ;
|
| 405 |
|
|
|
| 406 |
|
|
endcase
|
| 407 |
|
|
end
|
| 408 |
|
|
end
|
| 409 |
|
|
end
|
| 410 |
|
|
|
| 411 |
|
|
|
| 412 |
|
|
// transmitter shift register
|
| 413 |
|
|
always_ff @(posedge clk_i)
|
| 414 |
|
|
if (rst_i)
|
| 415 |
|
|
t <= 11'd0;
|
| 416 |
|
|
else begin
|
| 417 |
|
|
if (load_tx)
|
| 418 |
|
|
t <= {~(^dat_i[7:0]),dat_i[7:0],2'b0};
|
| 419 |
|
|
else if (shift_tx)
|
| 420 |
|
|
t <= {1'b1,t[10:1]};
|
| 421 |
|
|
end
|
| 422 |
|
|
|
| 423 |
|
|
|
| 424 |
|
|
// transmitter bit counter
|
| 425 |
|
|
always_ff @(posedge clk_i)
|
| 426 |
|
|
if (rst_i)
|
| 427 |
|
|
bitcnt <= 4'd0;
|
| 428 |
|
|
else begin
|
| 429 |
|
|
if (load_tx)
|
| 430 |
|
|
bitcnt <= 4'd11;
|
| 431 |
|
|
else if (shift_tx)
|
| 432 |
|
|
bitcnt <= bitcnt - 4'd1;
|
| 433 |
|
|
end
|
| 434 |
|
|
|
| 435 |
|
|
`endif
|
| 436 |
|
|
|
| 437 |
|
|
endmodule
|
