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1 19 robfinch
// ============================================================================
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//        __
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//   \\__/ o\    (C) 2011-2022  Robert Finch, Waterloo
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//    \  __ /    All rights reserved.
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//     \/_//     robfinch@finitron.ca
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//       ||
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//
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// random.v
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//     Multi-stream random number generator.
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//
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program.  If not, see .
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//
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//      Reg no.
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//      0                        read: random output bits [31:0], write: gen next number
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//  1           random stream number
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//  2           m_z seed setting bits [31:0]
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//  3           m_w seed setting bits [31:0]
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//
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//  +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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//      |WISHBONE Datasheet
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//      |WISHBONE SoC Architecture Specification, Revision B.3
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//      |
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//      |Description:                                           Specifications:
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//      +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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//      |General Description:                           random number generator
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//      +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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//      |Supported Cycles:                                      SLAVE,READ/WRITE
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//      |                                                                       SLAVE,BLOCK READ/WRITE
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//      |                                                                       SLAVE,RMW
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//      +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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//      |Data port, size:                                       16 bit
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//      |Data port, granularity:                        16 bit
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//      |Data port, maximum operand size:       16 bit
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//      |Data transfer ordering:                        Undefined
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//      |Data transfer sequencing:                      Undefined
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//      +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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//      |Clock frequency constraints:           none
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//      +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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//      |Supported signal list and                      Signal Name             WISHBONE equiv.
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//      |cross reference to equivalent          ack_o                   ACK_O
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//      |WISHBONE signals                                       adr_i[43:0]             ADR_I()
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//      |                                                                       clk_i                   CLK_I
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//      |                                   rst_i           RST_I()
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//      |                                                                       dat_i(15:0)             DAT_I()
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//      |                                                                       dat_o(15:0)             DAT_O()
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//      |                                                                       cyc_i                   CYC_I
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//      |                                                                       stb_i                   STB_I
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//      |                                                                       we_i                    WE_I
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//      |
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//      +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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//      |Special requirements:
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//      +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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//
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// ============================================================================
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//
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// Uses George Marsaglia's multiply method
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//
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// m_w = ;    /* must not be zero */
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// m_z = ;    /* must not be zero */
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//
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// uint get_random()
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// {
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//     m_z = 36969 * (m_z & 65535) + (m_z >> 16);
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//     m_w = 18000 * (m_w & 65535) + (m_w >> 16);
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//     return (m_z << 16) + m_w;  /* 32-bit result */
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// }
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//
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`define TRUE    1'b1
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`define FALSE   1'b0
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module random(rst_i, clk_i, cs_i, cyc_i, stb_i, ack_o, we_i, adr_i, dat_i, dat_o);
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input rst_i;
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input clk_i;
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input cs_i;
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input cyc_i;
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input stb_i;
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output reg ack_o;
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input we_i;
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input [3:0] adr_i;
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input [11:0] dat_i;
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output reg [11:0] dat_o;
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parameter pAckStyle = 1'b0;
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reg ack;
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reg cs;
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reg we;
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reg [3:0] adr;
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reg [11:0] dat;
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always_ff @(posedge clk_i)
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        cs <= cs_i && cyc_i && stb_i;
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always_ff @(posedge clk_i)
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        we <= we_i;
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always_ff @(posedge clk_i)
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        adr <= adr_i;
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always_ff @(posedge clk_i)
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        dat <= dat_i;
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always_ff @(posedge clk_i)
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        ack_o <= cs & cs_i & cyc_i & stb_i;
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//always @*
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//      ack_o <= cs ? ack : pAckStyle;
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reg [9:0] stream;
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reg [35:0] next_m_z;
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reg [35:0] next_m_w;
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reg [35:0] out;
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reg wrw, wrz;
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reg [35:0] w=32'd3,z=32'd17;
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wire [35:0] m_zs;
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wire [35:0] m_ws;
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wire pe_we;
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edge_det ued1 (.rst(rst_i), .clk(clk_i), .ce(1'b1), .i(we), .pe(pe_we), .ne(), .ee());
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rand_ram u1 (clk_i, wrw, stream, w, m_ws);
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rand_ram u2 (clk_i, wrz, stream, z, m_zs);
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always_comb
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begin
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        next_m_z = (18'h36969 * m_zs[17:0]) + m_zs[35:18];
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        next_m_w = (18'h18000 * m_ws[17:0]) + m_ws[35:18];
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end
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reg [35:0] m_zsws;
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always_comb
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        m_zsws <= {m_zs[17:0],18'd0} + m_ws;
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// Register read path
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//
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always_ff @(posedge clk_i)
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if (cs_i)
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        case(adr[3:0])
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        4'd0:   dat_o <= 12'h0;
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        4'd1: dat_o <= m_zsws[35:24];
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        4'd2: dat_o <= m_zsws[23:12];
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        4'd3:   dat_o <= m_zsws[11: 0];
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        4'd5:   dat_o <= {2'h0,stream};
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// Uncomment these for register read-back
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//              3'd4:   dat_o <= m_z[31:16];
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//              3'd5:   dat_o <= m_z[15: 0];
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//              3'd6:   dat_o <= m_w[31:16];
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//              3'd7:   dat_o <= m_w[15: 0];
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        default:        dat_o <= 12'h000;
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        endcase
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else
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        dat_o <= 12'h0;
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// Register write path
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//
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always_ff @(posedge clk_i)
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begin
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        wrw <= `FALSE;
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        wrz <= `FALSE;
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        if (cs) begin
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                if (pe_we)
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                        case(adr[3:0])
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                        4'd3:
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                                begin
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                                        z <= next_m_z;
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                                        w <= next_m_w;
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                                        wrw <= `TRUE;
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                                        wrz <= `TRUE;
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                                end
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                        4'd5:   stream <= dat[9:0];
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                        4'd8:   ;
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                        4'd9:   z[35:24] <= dat;
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                        4'd10:  z[23:12] <= dat;
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                        4'd11:  begin z[11: 0] <= dat; wrz <= `TRUE; end
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                        4'd12:  ;
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                        4'd13:  w[35:24] <= dat;
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                        4'd14:  w[23:12] <= dat;
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                        4'd15:  begin w[11:0] <= dat; wrw <= `TRUE; end
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                        endcase
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        end
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end
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endmodule
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// Tools were inferring a massive distributed ram so we help them out a bit by
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// creating an explicit ram definition.
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module rand_ram(clk, wr, ad, i, o);
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input clk;
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input wr;
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input [9:0] ad;
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input [35:0] i;
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output [35:0] o;
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reg [35:0] ri;
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reg [9:0] regadr;
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reg regwr;
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(* RAM_STYLE="BLOCK" *)
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reg [35:0] mem [0:1023];
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always_ff @(posedge clk)
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        regadr <= ad;
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always_ff @(posedge clk)
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        regwr <= wr;
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always_ff @(posedge clk)
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        ri <= i;
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always_ff @(posedge clk)
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        if (regwr)
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                mem[regadr] <= ri;
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assign o = mem[regadr];
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endmodule

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