Subversion Repositories rf6809

// ============================================================================

//        __

//   \\__/ o\    (C) 2012-2022  Robert Finch, Waterloo

//    \  __ /    All rights reserved.

//     \/_//     robfinch@finitron.ca

//       ||

//

//

// BSD 3-Clause License

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// modification, are permitted provided that the following conditions are met:

//

// 1. Redistributions of source code must retain the above copyright notice, this

//    list of conditions and the following disclaimer.

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// 2. Redistributions in binary form must reproduce the above copyright notice,

//    this list of conditions and the following disclaimer in the documentation

//    and/or other materials provided with the distribution.

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// 3. Neither the name of the copyright holder nor the names of its

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//    this software without specific prior written permission.

//

// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"

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//

// ============================================================================

//

module scratchmem(rst_i, clk_i, cti_i, bok_o, cs_i, cyc_i, stb_i, ack_o, we_i, adr_i, dat_i, dat_o, sp);

input rst_i;

input clk_i;

input [2:0] cti_i;

output bok_o;

input cs_i;

input cyc_i;

input stb_i;

output ack_o;

input we_i;

input [13:0] adr_i;

input [11:0] dat_i;

output reg [11:0] dat_o;

input [23:0] sp;

integer n;

reg [11:0] rommem [16383:0];

reg [13:0] radr;

initial begin

        for (n = 0; n < 16384; n = n + 1)

                rommem[n] <= 'h00;

`include "d:/cores2022/rf6809/software/a09/a09/debug/boot_rom.ver";

end

wire cs = cs_i && cyc_i && stb_i;

assign bok_o = cs_i;

reg csd = 1'b0;

reg wed = 1'b0;

reg [13:0] adrd = 16'h00;

reg [11:0] datid = 8'h00;

reg [11:0] datod = 'h00;

reg [2:0] cnt;

ack_gen #(

        .READ_STAGES(2),

        .WRITE_STAGES(1),

        .REGISTER_OUTPUT(1)

) ag1

(

        .clk_i(clk_i),

        .ce_i(1'b1),

        .i(cs && cnt != 3'b101),

        .we_i(we_i && cs && cnt != 3'b101),

        .o(ack_o),

        .rid_i(0),

        .wid_i(0),

        .rid_o(),

        .wid_o()

);

always @(posedge clk_i)

        csd <= cs;

always @(posedge clk_i)

        wed <= we_i;

always @(posedge clk_i)

        adrd <= adr_i;

always @(posedge clk_i)

        datid <= dat_i;

always @(posedge clk_i)

        if (cs & we_i) begin

                $display ("wrote to scratchmem: %h=%h", adr_i, dat_i);

                /*

                if (adr_i[14:3]==15'h3e9 && dat_i==64'h00) begin

                  $display("3e9=00");

                  $finish;

                end

                */

        end

genvar g;

generate begin : gRom

for (g = 0; g < 1; g = g + 1)

always @(posedge clk_i)

        if (csd && wed)

                rommem[adrd[13:0]][g*12+11:g*12] <= datid[11:0];

end

endgenerate

wire pe_cs;

edge_det u1(.rst(rst_i), .clk(clk_i), .ce(1'b1), .i(cs), .pe(pe_cs), .ne(), .ee() );

reg [13:0] ctr;

always @(posedge clk_i)

if (rst_i) begin

        cnt <= 3'd0;

        ctr <= 14'd0;

end

else begin

        if (pe_cs) begin

                if (cti_i==3'b000)

                        ctr <= adr_i[13:0];

                else

                        ctr <= adr_i[13:0] + 12'd1;

                cnt <= 3'b000;

        end

        else if (cs && cnt[2:0]!=3'b100 && cti_i!=3'b000) begin

                ctr <= ctr + 2'd1;

                cnt <= cnt + 3'd1;

        end

end

always @(posedge clk_i)

        radr <= pe_cs ? adr_i[13:0] : ctr;

reg [13:0] spr;

always @(posedge clk_i)

        spr <= sp[13:0];

always @(posedge clk_i)

if (rst_i)

        datod <= 12'h00;

else begin

        datod <= rommem[radr[13:0]];

        if (!we_i & cs)

                $display("read from scratchmem: %h=%h", radr, rommem[radr[13:0]]);

//      $display("-------------- Stack --------------");

//      for (n = -6; n < 8; n = n + 1) begin

//              $display("%c%c %h %h", n==0 ? "-": " ", n==0 ?">" : " ",spr + n, rommem[spr+n]);

//      end

end

always @(posedge clk_i)

if (rst_i)

        dat_o <= 'h00;

else begin

        if (cs_i)

                dat_o <= datod;

        else

                dat_o <= 'd0;

end

endmodule