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[/] [rf6809/] [trunk/] [rtl/] [noc/] [video/] [rfFrameBuffer_x12.sv] - Blame information for rev 19

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1 19 robfinch
// ============================================================================
2
//  Bitmap Controller (Frame Buffer Display)
3
//  - Displays a bitmap from memory.
4
//
5
//
6
//        __
7
//   \\__/ o\    (C) 2008-2022  Robert Finch, Waterloo
8
//    \  __ /    All rights reserved.
9
//     \/_//     robfinch@finitron.ca
10
//       ||
11
//
12
//
13
// BSD 3-Clause License
14
// Redistribution and use in source and binary forms, with or without
15
// modification, are permitted provided that the following conditions are met:
16
//
17
// 1. Redistributions of source code must retain the above copyright notice, this
18
//    list of conditions and the following disclaimer.
19
//
20
// 2. Redistributions in binary form must reproduce the above copyright notice,
21
//    this list of conditions and the following disclaimer in the documentation
22
//    and/or other materials provided with the distribution.
23
//
24
// 3. Neither the name of the copyright holder nor the names of its
25
//    contributors may be used to endorse or promote products derived from
26
//    this software without specific prior written permission.
27
//
28
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
29
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
30
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
31
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
32
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
34
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
35
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
36
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38
//
39
//
40
//  The default base screen address is:
41
//              $0200000 - the third meg of RAM
42
//
43
//
44
//      Verilog 1995
45
//
46
// ============================================================================
47
 
48
//`define USE_CLOCK_GATE        1'b1
49
`define INTERNAL_SYNC_GEN       1'b1
50
 
51
`define ABITS   31:0
52
`define HIGH    1'b1
53
`define LOW             1'b0
54
`define TRUE    1'b1
55
`define FALSE   1'b0
56
 
57
module rfFrameBuffer_x12 (
58
        rst_i, irq_o,
59
        s_clk_i, s_cs_i, s_cyc_i, s_stb_i, s_ack_o, s_we_i, s_adr_i, s_dat_i, s_dat_o,
60
        m_clk_i, m_cyc_o, m_stb_o, m_ack_i, m_we_o, m_sel_o, m_adr_o, m_dat_i, m_dat_o,
61
        dot_clk_i, zrgb_o, xonoff_i, xal_o,
62
`ifdef INTERNAL_SYNC_GEN
63
        , hsync_o, vsync_o, blank_o, border_o, hctr_o, vctr_o, fctr_o, vblank_o
64
`else
65
        , hsync_i, vsync_i, blank_i
66
`endif
67
);
68
parameter MDW = 96;             // Bus master data width
69
parameter MAP = 12'd0;
70
parameter BM_BASE_ADDR1 = 32'h0020_0000;
71
parameter BM_BASE_ADDR2 = 32'h0028_0000;
72
parameter REG_CTRL = 11'd0;
73
parameter REG_REFDELAY = 11'd1;
74
parameter REG_PAGE1ADDR = 11'd2;
75
parameter REG_PAGE2ADDR = 11'd3;
76
parameter REG_PXYZ = 11'd4;
77
parameter REG_PCOLCMD = 11'd5;
78
parameter REG_TOTAL = 11'd8;
79
parameter REG_SYNC_ONOFF = 11'd9;
80
parameter REG_BLANK_ONOFF = 11'd10;
81
parameter REG_BORDER_ONOFF = 11'd11;
82
parameter REG_RASTCMP = 11'd12;
83
parameter REG_BMPSIZE = 11'd13;
84
parameter REG_OOB_COLOR = 11'd14;
85
parameter REG_WINDOW = 11'd15;
86
 
87
parameter BPP6 = 4'd1;
88
parameter BPP8 = 4'd2;
89
parameter BPP12 = 4'd3;
90
parameter BPP16 = 4'd4;
91
parameter BPP18 = 4'd5;
92
parameter BPP21 = 4'd6;
93
parameter BPP24 = 4'd7;
94
parameter BPP27 = 4'd8;
95
parameter BPP32 = 4'd9;
96
parameter BPP33 = 4'd10;
97
 
98
parameter OPBLACK = 4'd0;
99
parameter OPCOPY = 4'd1;
100
parameter OPINV = 4'd2;
101
parameter OPAND = 4'd4;
102
parameter OPOR = 4'd5;
103
parameter OPXOR = 4'd6;
104
parameter OPANDN = 4'd7;
105
parameter OPNAND = 4'd8;
106
parameter OPNOR = 4'd9;
107
parameter OPXNOR = 4'd10;
108
parameter OPORN = 4'd11;
109
parameter OPWHITE = 4'd15;
110
 
111
// Sync Generator defaults: 800x600 60Hz
112
parameter phSyncOn  = 40;               //   40 front porch
113
parameter phSyncOff = 168;              //  128 sync
114
parameter phBlankOff = 252;     //256   //   88 back porch
115
//parameter phBorderOff = 336;  //   80 border
116
parameter phBorderOff = 256;    //   80 border
117
//parameter phBorderOn = 976;           //  640 display
118
parameter phBorderOn = 1056;            //  800 display
119
parameter phBlankOn = 1052;             //   4 border
120
parameter phTotal = 1056;               // 1056 total clocks
121
parameter pvSyncOn  = 1;                //    1 front porch
122
parameter pvSyncOff = 5;                //    4 vertical sync
123
parameter pvBlankOff = 28;              //   23 back porch
124
parameter pvBorderOff = 28;             //   44 border  0
125
//parameter pvBorderOff = 72;           //   44 border  0
126
parameter pvBorderOn = 628;             //  600 display
127
//parameter pvBorderOn = 584;           //  512 display
128
parameter pvBlankOn = 628;      //   44 border  0
129
parameter pvTotal = 628;                //  628 total scan lines
130
 
131
 
132
// SYSCON
133
input rst_i;                            // system reset
134
output irq_o;
135
 
136
// Peripheral IO slave port
137
input s_clk_i;
138
input s_cs_i;
139
input s_cyc_i;
140
input s_stb_i;
141
output s_ack_o;
142
input s_we_i;
143
input [13:0] s_adr_i;
144
input [11:0] s_dat_i;
145
output [11:0] s_dat_o;
146
reg [11:0] s_dat_o;
147
 
148
// Video Memory Master Port
149
// Used to read memory via burst access
150
input m_clk_i;                          // system bus interface clock
151
output reg m_cyc_o;             // video burst request
152
output reg m_stb_o;
153
output reg m_we_o;
154
output reg [MDW/12-1:0] m_sel_o;
155
input  m_ack_i;                 // vid_acknowledge from memory
156
output reg [`ABITS] m_adr_o;    // address for memory access
157
input  [MDW-1:0] m_dat_i;       // memory data input
158
output reg [MDW-1:0] m_dat_o;
159
 
160
// Video
161
input dot_clk_i;                // Video clock 80 MHz
162
`ifdef INTERNAL_SYNC_GEN
163
output hsync_o;
164
output vsync_o;
165
output blank_o;
166
output vblank_o;
167
output border_o;
168
output [11:0] hctr_o;
169
output [11:0] vctr_o;
170
output [5:0] fctr_o;
171
`else
172
input hsync_i;                  // start/end of scan line
173
input vsync_i;                  // start/end of frame
174
input blank_i;                  // blank the output
175
`endif
176
output [31:0] zrgb_o;           // 24-bit RGB output + z-order
177
reg [31:0] zrgb_o;
178
 
179
input xonoff_i;
180
output reg xal_o;               // external access line (sprite access)
181
 
182
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
183
// IO registers
184
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
185
reg irq_o;
186
 
187
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
188
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
189
wire vclk;
190
reg cs;
191
reg we;
192
reg [13:0] adri;
193
reg [11:0] dat;
194
 
195
always @(posedge s_clk_i)
196
        cs <= s_cyc_i & s_stb_i & s_cs_i;
197
always @(posedge s_clk_i)
198
        we <= s_we_i;
199
always @(posedge s_clk_i)
200
        adri <= s_adr_i;
201
always @(posedge s_clk_i)
202
        dat <= s_dat_i;
203
 
204
ack_gen #(
205
        .READ_STAGES(2),
206
        .WRITE_STAGES(0),
207
        .REGISTER_OUTPUT(1)
208
) uag1
209
(
210
        .rst_i(rst_i),
211
        .clk_i(s_clk_i),
212
        .ce_i(1'b1),
213
        .i(cs),
214
        .we_i(s_cyc_i & s_stb_i & s_cs_i & s_we_i),
215
        .o(s_ack_o),
216
        .rid_i(0),
217
        .wid_i(0),
218
        .rid_o(),
219
        .wid_o()
220
);
221
 
222
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
223
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
224
integer n;
225
reg [11:0] rastcmp;
226
reg [`ABITS] bm_base_addr1,bm_base_addr2;
227
reg [3:0] color_depth;
228
wire [7:0] fifo_cnt;
229
reg onoff;
230
reg [2:0] hres,vres;
231
reg greyscale;
232
reg page;
233
reg [3:0] pals;                         // palette select
234
reg [15:0] hrefdelay;
235
reg [15:0] vrefdelay;
236
reg [15:0] windowLeft;
237
reg [15:0] windowTop;
238
reg [11:0] windowWidth,windowHeight;
239
reg [11:0] map;     // memory access period
240
reg [11:0] mapctr;
241
reg [15:0] bmpWidth;            // scan line increment (pixels)
242
reg [15:0] bmpHeight;
243
reg [`ABITS] baseAddr;  // base address register
244
wire [MDW-1:0] rgbo1, rgbo1e, rgbo1o, rgbo1m;
245
reg [31:0] rgbo2,rgbo4;
246
reg [MDW-1:0] rgbo3;
247
reg [15:0] pixelRow;
248
reg [15:0] pixelCol;
249
wire [11:0] pal_wo;
250
wire [47:0] pal_o;
251
reg [15:0] px;
252
reg [15:0] py;
253
reg [11:0] pz;
254
reg [1:0] pcmd,pcmd_o;
255
reg [3:0] raster_op;
256
reg [32:0] oob_color;
257
reg [31:0] color;
258
reg [31:0] color_o;
259
reg rstcmd,rstcmd1;
260
reg [11:0] hTotal = phTotal;
261
reg [11:0] vTotal = pvTotal;
262
reg [11:0] hSyncOn = phSyncOn, hSyncOff = phSyncOff;
263
reg [11:0] vSyncOn = pvSyncOn, vSyncOff = pvSyncOff;
264
reg [11:0] hBlankOn = phBlankOn, hBlankOff = phBlankOff;
265
reg [11:0] vBlankOn = pvBlankOn, vBlankOff = pvBlankOff;
266
reg [11:0] hBorderOn = phBorderOn, hBorderOff = phBorderOff;
267
reg [11:0] vBorderOn = pvBorderOn, vBorderOff = pvBorderOff;
268
reg sgLock;
269
wire pe_hsync, pe_hsync2;
270
wire pe_vsync;
271
 
272
`ifdef INTERNAL_SYNC_GEN
273
wire hsync_i, vsync_i, blank_i;
274
 
275
VGASyncGen usg1
276
(
277
        .rst(rst_i),
278
        .clk(vclk),
279
        .eol(),
280
        .eof(),
281
        .hSync(hsync_o),
282
        .vSync(vsync_o),
283
        .hCtr(hctr_o),
284
        .vCtr(vctr_o),
285
  .blank(blank_o),
286
  .vblank(vblank),
287
  .vbl_int(),
288
  .border(border_o),
289
  .hTotal_i(hTotal),
290
  .vTotal_i(vTotal),
291
  .hSyncOn_i(hSyncOn),
292
  .hSyncOff_i(hSyncOff),
293
  .vSyncOn_i(vSyncOn),
294
  .vSyncOff_i(vSyncOff),
295
  .hBlankOn_i(hBlankOn),
296
  .hBlankOff_i(hBlankOff),
297
  .vBlankOn_i(vBlankOn),
298
  .vBlankOff_i(vBlankOff),
299
  .hBorderOn_i(hBorderOn),
300
  .hBorderOff_i(hBorderOff),
301
  .vBorderOn_i(vBorderOn),
302
  .vBorderOff_i(vBorderOff)
303
);
304
assign hsync_i = hsync_o;
305
assign vsync_i = vsync_o;
306
assign blank_i = blank_o;
307
assign vblank_o = vblank;
308
`endif
309
 
310
edge_det edcs1
311
(
312
        .rst(rst_i),
313
        .clk(s_clk_i),
314
        .ce(1'b1),
315
        .i(cs),
316
        .pe(cs_edge),
317
        .ne(),
318
        .ee()
319
);
320
 
321
// Frame counter
322
//
323
VT163 #(6) ub1
324
(
325
        .clk(vclk),
326
        .clr_n(!rst_i),
327
        .ent(pe_vsync),
328
        .enp(1'b1),
329
        .ld_n(1'b1),
330
        .d(6'd0),
331
        .q(fctr_o),
332
        .rco()
333
);
334
 
335
reg rst_irq;
336
always_ff @(posedge vclk)
337
if (rst_i)
338
        irq_o <= `LOW;
339
else begin
340
        if (hctr_o==12'd02 && rastcmp==vctr_o)
341
                irq_o <= `HIGH;
342
        else if (rst_irq)
343
                irq_o <= `LOW;
344
end
345
 
346
always @(page or bm_base_addr1 or bm_base_addr2)
347
        baseAddr = page ? bm_base_addr2 : bm_base_addr1;
348
 
349
// Color palette RAM for 8bpp modes
350
syncRam512x48_1rw1r upal1       // Actually 1024x48
351
(
352
  .clka(s_clk_i),    // input wire clka
353
  .ena(cs & adri[13]),      // input wire ena
354
  .wea(we),      // input wire [3 : 0] wea
355
  .addra(adri[11:0]),  // input wire [8 : 0] addra
356
  .dina(dat),                           // input wire [31 : 0] dina
357
  .douta(pal_wo),  // output wire [31 : 0] douta
358
  .clkb(vclk),    // input wire clkb
359
  .enb(1'b1),      // input wire enb
360
  .web(1'b0),      // input wire [3 : 0] web
361
  .addrb({pals[2:0],rgbo4[5:0]}),  // input wire [8 : 0] addrb
362
  .dinb(48'h0),    // input wire [31 : 0] dinb
363
  .doutb(pal_o)  // output wire [31 : 0] doutb
364
);
365
 
366
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
367
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
368
always_ff @(posedge s_clk_i)
369
if (rst_i) begin
370
        page <= 1'b0;
371
        pals <= 4'h0;
372
        hres <= 3'd2;
373
        vres <= 3'd2;
374
        windowWidth <= 12'd400;
375
        windowHeight <= 12'd300;
376
        onoff <= 1'b0;
377
        color_depth <= BPP16;
378
        greyscale <= 1'b0;
379
        bm_base_addr1 <= BM_BASE_ADDR1;
380
        bm_base_addr2 <= BM_BASE_ADDR2;
381
        hrefdelay = 16'hFF99;//12'd103;
382
        vrefdelay = 16'hFFF3;//12'd13;
383
        windowLeft <= 16'h0;
384
        windowTop <= 16'h0;
385
        windowWidth <= 16'd400;
386
        windowHeight <= 16'd300;
387
        bmpWidth <= 16'd400;
388
        bmpHeight <= 16'd300;
389
        map <= MAP;
390
        pcmd <= 2'b00;
391
        rstcmd1 <= 1'b0;
392
        rst_irq <= 1'b0;
393
        rastcmp <= 12'hFFF;
394
        oob_color <= 32'h00003C00;
395
end
396
else begin
397
        rstcmd1 <= rstcmd;
398
        rst_irq <= 1'b0;
399
  if (rstcmd & ~rstcmd1)
400
    pcmd <= 2'b00;
401
        if (cs_edge) begin
402
                if (we) begin
403
                        casez(adri[13:3])
404
                        REG_CTRL:
405
                                case(adri[2:0])
406
                                3'd0:   onoff <= dat[0];
407
                                3'd1:
408
                                        begin
409
                                                color_depth <= dat[3:0];
410
                                                greyscale <= dat[4];
411
                                        end
412
                                3'd2:
413
                                        begin
414
                                                hres <= dat[2:0];
415
                                                vres <= dat[6:4];
416
                                        end
417
                                3'd3:
418
                                        begin
419
                                                page <= dat[0];
420
                                                pals <= dat[3:1];
421
                                        end
422
                                3'd6: ;
423
                                3'd7:   map[11:0] <= dat;
424
                                default:        ;
425
                                endcase
426
                        REG_REFDELAY:
427
                                case(adri[2:0])
428
                                3'd0:   hrefdelay[15:12] <= dat[3:0];
429
                                3'd1:   hrefdelay[11: 0] <= dat;
430
                                3'd2:   vrefdelay[15:12] <= dat[3:0];
431
                                3'd3:   vrefdelay[11: 0] <= dat;
432
                                default:        ;
433
                                endcase
434
                        REG_PAGE1ADDR:
435
                                case(adri[2:0])
436
                                3'd1:   bm_base_addr1[31:24] <= dat[7:0];
437
                                3'd2: bm_base_addr1[23:12] <= dat;
438
                                3'd3:   bm_base_addr1[11: 0] <= dat;
439
                                default:        ;
440
                                endcase
441
                        REG_PAGE2ADDR:
442
                                case(adri[2:0])
443
                                3'd1:   bm_base_addr2[31:24] <= dat[7:0];
444
                                3'd2: bm_base_addr2[23:12] <= dat;
445
                                3'd3:   bm_base_addr2[11: 0] <= dat;
446
                                default:        ;
447
                                endcase
448
                        REG_PXYZ:
449
                                case(adri[2:0])
450
                                3'd0:   px[15:12] <= dat[3:0];
451
                                3'd1:   px[11: 0] <= dat;
452
                                3'd2:   py[15:12] <= dat[3:0];
453
                                3'd3:   py[11: 0] <= dat;
454
                                3'd5:   pz[11: 0] <= dat;
455
                                default:        ;
456
                                endcase
457
                        REG_PCOLCMD:
458
                                case(adri[2:0])
459
                                3'd0:   pcmd <= dat[1:0];
460
                                3'd2:   raster_op <= dat[3:0];
461
                                3'd4:   ;
462
                                3'd5:   color[31:24] <= dat[7:0];
463
                                3'd6:   color[23:12] <= dat;
464
                                3'd7:   color[11: 0] <= dat;
465
                                default:        ;
466
                                endcase
467
                        REG_RASTCMP:
468
                                case(adri[2:0])
469
                                3'd0:   ;
470
                                3'd1:   rastcmp[11: 0] <= dat;
471
                                3'd7:   rst_irq <= dat[11];
472
                                default:        ;
473
                                endcase
474
                        REG_BMPSIZE:
475
                                case(adri[2:0])
476
                                3'd2: bmpWidth[15:12] <= dat[3:0];
477
                                3'd3:   bmpWidth[11:0] <= dat;
478
                                3'd6: bmpHeight[15:12] <= dat[3:0];
479
                                3'd7: bmpHeight[11:0] <= dat;
480
                                default:        ;
481
                                endcase
482
                        REG_OOB_COLOR:
483
                                case(adri[2:0])
484
                                3'd1:   oob_color[31:24] <= dat[7:0];
485
                                3'd2:   oob_color[23:12] <= dat;
486
                                3'd3:   oob_color[11: 0] <= dat;
487
                                default:        ;
488
                                endcase
489
                        REG_WINDOW:
490
                                case(adri[2:0])
491
                                3'd0:   windowWidth <= dat;
492
                                3'd1:   windowHeight <= dat;
493
                                3'd4:   windowLeft[15:12] <= dat[3:0];
494
                                3'd5:   windowLeft[11: 0] <= dat;
495
                                3'd6:   windowTop[15:12] <= dat[3:0];
496
                                3'd7:   windowTop[11: 0] <= dat;
497
                                endcase
498
 
499
`ifdef INTERNAL_SYNC_GEN
500
                        REG_TOTAL:
501
                                case(adri[2:0])
502
                                3'd0:   if (!sgLock) hTotal <= dat;
503
                                3'd1: if (!sgLock) vTotal <= dat;
504
                                3'd7:   if (dat==12'hA12)
505
                                                                sgLock <= 1'b1;
506
                                                        else if (dat==12'h21A)
507
                                                                sgLock <= 1'b0;
508
                                default:        ;
509
                                endcase
510
                        REG_SYNC_ONOFF:
511
                                case(adri[2:0])
512
                                3'd0:   if (!sgLock) hSyncOff <= dat;
513
                                3'd1:   if (!sgLock) hSyncOn <= dat;
514
                                3'd2: if (!sgLock) vSyncOff <= dat;
515
                                3'd3: if (!sgLock) vSyncOn <= dat;
516
                                default:        ;
517
                                endcase
518
                        REG_BLANK_ONOFF:
519
                                case(adri[2:0])
520
                                3'd0:   if (!sgLock) hBlankOff <= dat;
521
                                3'd1:   if (!sgLock) hBlankOn <= dat;
522
                                3'd2: if (!sgLock) vBlankOff <= dat;
523
                                3'd3: if (!sgLock) vBlankOn <= dat;
524
                                default:        ;
525
                                endcase
526
                        REG_BORDER_ONOFF:
527
                                case(adri[2:0])
528
                                3'd0:   if (!sgLock) hBorderOff <= dat;
529
                                3'd1:   if (!sgLock) hBorderOn <= dat;
530
                                3'd2: if (!sgLock) vBorderOff <= dat;
531
                                3'd3: if (!sgLock) vBorderOn <= dat;
532
                                default:        ;
533
                                endcase
534
`endif
535
      default:  ;
536
                        endcase
537
                end
538
        end
539
        if (s_cs_i)
540
          casez(adri[13:3])
541
          REG_CTRL:     ;
542
          /*
543
              begin
544
                  s_dat_o[0] <= onoff;
545
                  s_dat_o[10:8] <= color_depth;
546
                  s_dat_o[12] <= greyscale;
547
                  s_dat_o[18:16] <= hres;
548
                  s_dat_o[22:20] <= vres;
549
                  s_dat_o[24] <= page;
550
                  s_dat_o[28:25] <= pals;
551
                  s_dat_o[47:32] <= bmpWidth;
552
                  s_dat_o[59:48] <= map;
553
              end
554
          */
555
          REG_REFDELAY:
556
                        case(adri[2:0])
557
                        3'd0:   s_dat_o <= {8'h00,hrefdelay[15:12]};
558
                        3'd1:   s_dat_o <= hrefdelay[11: 0];
559
                        3'd2:   s_dat_o <= {8'h00,vrefdelay[15:12]};
560
                        3'd3:   s_dat_o <= vrefdelay[11: 0];
561
                        default:        s_dat_o <= 12'h0;
562
                        endcase
563
          REG_PAGE1ADDR:
564
                        case(adri[2:0])
565
                        3'd1:   s_dat_o <= {4'h0,bm_base_addr1[31:24]};
566
                        3'd2: s_dat_o <= bm_base_addr1[23:12];
567
                        3'd3:   s_dat_o <= bm_base_addr1[11: 0];
568
                        default:        s_dat_o <= 12'h0;
569
                        endcase
570
          REG_PAGE2ADDR:
571
                        case(adri[2:0])
572
                        3'd1:   s_dat_o <= {4'h0,bm_base_addr2[31:24]};
573
                        3'd2: s_dat_o <= bm_base_addr2[23:12];
574
                        3'd3:   s_dat_o <= bm_base_addr2[11: 0];
575
                        default:        s_dat_o <= 12'h0;
576
                        endcase
577
          REG_PXYZ:
578
                        case(adri[2:0])
579
                        3'd0:   s_dat_o <= {8'h00,px[15:12]};
580
                        3'd1:   s_dat_o <= px[11: 0];
581
                        3'd2:   s_dat_o <= {8'h00,py[15:12]};
582
                        3'd3:   s_dat_o <= py[11: 0];
583
                        3'd5:   s_dat_o <= pz[11: 0];
584
                        default:        s_dat_o <= 12'h0;
585
                        endcase
586
          REG_PCOLCMD:
587
                        case(adri[2:0])
588
                        3'd0:   s_dat_o <= {10'h0,pcmd};
589
                        3'd2:   s_dat_o <= {8'h0,raster_op};
590
                        3'd5:   s_dat_o <= {4'h0,color[31:24]};
591
                        3'd6:   s_dat_o <= color[23:12];
592
                        3'd7:   s_dat_o <= color[11: 0];
593
                        default:        s_dat_o <= 12'h0;
594
                        endcase
595
          REG_OOB_COLOR:
596
                        case(adri[2:0])
597
                        3'd1:   s_dat_o <= {4'h0,oob_color[31:24]};
598
                        3'd2:   s_dat_o <= oob_color[23:12];
599
                        3'd3:   s_dat_o <= oob_color[11: 0];
600
                        default:        s_dat_o <= 12'h0;
601
                        endcase
602
          REG_WINDOW:
603
                        case(adri[2:0])
604
                        3'd0:   s_dat_o <= windowWidth <= dat;
605
                        3'd1:   s_dat_o <= windowHeight <= dat;
606
                        3'd4:   s_dat_o <= {8'h00,windowLeft[15:12]};
607
                        3'd5:   s_dat_o <= windowLeft[11: 0];
608
                        3'd6:   s_dat_o <= {8'h00,windowTop[15:12]};
609
                        3'd7:   s_dat_o <= windowTop[11: 0];
610
                        default:        s_dat_o <= 12'h0;
611
                        endcase
612
          11'b1?_????_????_?:   s_dat_o <= pal_wo;
613
          default:        s_dat_o <= 12'd0;
614
          endcase
615
        else
616
                s_dat_o <= 12'h0;
617
end
618
 
619
//`ifdef USE_CLOCK_GATE
620
//BUFHCE ucb1
621
//(
622
//      .I(dot_clk_i),
623
//      .CE(onoff),
624
//      .O(vclk)
625
//);
626
//`else
627
assign vclk = dot_clk_i;
628
//`endif
629
 
630
 
631
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
632
// Horizontal and Vertical timing reference counters
633
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
634
 
635
reg lef;        // load even fifo
636
reg lof;        // load odd fifo
637
 
638
edge_det edh1
639
(
640
        .rst(rst_i),
641
        .clk(vclk),
642
        .ce(1'b1),
643
        .i(hsync_i),
644
        .pe(pe_hsync),
645
        .ne(),
646
        .ee()
647
);
648
 
649
edge_det edh2
650
(
651
        .rst(1'b0),
652
        .clk(m_clk_i),
653
        .ce(1'b1),
654
        .i(hsync_i),
655
        .pe(pe_hsync2),
656
        .ne(),
657
        .ee()
658
);
659
 
660
edge_det edv1
661
(
662
        .rst(rst_i),
663
        .clk(vclk),
664
        .ce(1'b1),
665
        .i(vsync_i),
666
        .pe(pe_vsync),
667
        .ne(),
668
        .ee()
669
);
670
 
671
reg [3:0] hc = 4'd1;
672
always_ff @(posedge vclk)
673
if (pe_hsync) begin
674
        hc <= 4'd1;
675
        pixelCol <= hrefdelay;
676
end
677
else begin
678
        if (hc==hres) begin
679
                hc <= 4'd1;
680
                pixelCol <= pixelCol + 16'd1;
681
        end
682
        else
683
                hc <= hc + 4'd1;
684
end
685
 
686
reg [3:0] vc = 4'd1;
687
always_ff @(posedge vclk)
688
if (pe_vsync) begin
689
        vc <= 4'd1;
690
        pixelRow <= vrefdelay;
691
end
692
else begin
693
        if (pe_hsync) begin
694
                vc <= vc + 4'd1;
695
                if (vc==vres) begin
696
                        vc <= 4'd1;
697
                        pixelRow <= pixelRow + 16'd1;
698
                end
699
        end
700
end
701
always_comb
702
        lef = ~pixelRow[0];
703
always_comb
704
        lof =  pixelRow[0];
705
 
706
always_ff @(posedge vclk)
707
        xal_o <= vc != 4'd1;
708
 
709
// Bits per pixel minus one.
710
reg [4:0] bpp;
711
always_comb
712
case(color_depth)
713
BPP6: bpp = 5;
714
BPP8:   bpp = 7;
715
BPP12: bpp = 11;
716
BPP16:  bpp = 15;
717
BPP18:  bpp = 17;
718
BPP21:  bpp = 20;
719
BPP24:  bpp = 23;
720
BPP27:  bpp = 26;
721
BPP32:  bpp = 31;
722
BPP33:  bpp = 32;
723
default:        bpp = 15;
724
endcase
725
 
726
reg [5:0] shifts;
727
always_comb
728
case(MDW)
729
96:
730
        case(color_depth)
731
        BPP6:   shifts = 6'd16;
732
        BPP8:   shifts = 6'd12;
733
        BPP12:  shifts = 6'd8;
734
        BPP16:  shifts = 6'd6;
735
        BPP18:  shifts = 6'd5;
736
        BPP21:  shifts = 6'd4;
737
        BPP24:  shifts = 6'd4;
738
        BPP27:  shifts = 6'd3;
739
        BPP32:  shifts = 6'd3;
740
        BPP33:  shifts = 6'd2;
741
        default:  shifts = 6'd8;
742
        endcase
743
default:
744
        begin
745
        $display("rfFrameBuffer_x12: Bad master bus width");
746
        $finish;
747
        end
748
endcase
749
 
750
wire vFetch = !vblank;//pixelRow < windowHeight;
751
reg fifo_rrst;
752
reg fifo_wrst;
753
always_comb fifo_rrst = pixelCol==16'hFFFF;
754
always_comb fifo_wrst = pe_hsync2 && vc==4'd1;
755
 
756
wire[31:0] grAddr,xyAddr;
757
reg [11:0] fetchCol;
758
localparam CMS = MDW==128 ? 6 : MDW==64 ? 5 : 4;
759
wire [CMS:0] mb,me,ce;
760
reg [MDW-1:0] mem_strip;
761
wire [MDW-1:0] mem_strip_o;
762
wire [31:0] mem_color;
763
 
764
// Compute fetch address
765
gfx_calc_address #(MDW) u1
766
(
767
  .clk(m_clk_i),
768
        .base_address_i(baseAddr),
769
        .color_depth_i(color_depth),
770
        .bmp_width_i(bmpWidth),
771
        .x_coord_i(windowLeft),
772
        .y_coord_i(windowTop + pixelRow),
773
        .address_o(grAddr),
774
        .mb_o(),
775
        .me_o(),
776
        .ce_o()
777
);
778
 
779
// Compute address for get/set pixel
780
gfx_calc_address  #(MDW) u2
781
(
782
  .clk(m_clk_i),
783
        .base_address_i(baseAddr),
784
        .color_depth_i(color_depth),
785
        .bmp_width_i(bmpWidth),
786
        .x_coord_i(px),
787
        .y_coord_i(py),
788
        .address_o(xyAddr),
789
        .mb_o(mb),
790
        .me_o(me),
791
        .ce_o(ce)
792
);
793
 
794
always_ff @(posedge m_clk_i)
795
if (pe_hsync2)
796
  mapctr <= 12'hFFE;
797
else begin
798
  if (mapctr == map)
799
    mapctr <= 12'd0;
800
  else
801
    mapctr <= mapctr + 12'd1;
802
end
803
wire memreq = mapctr==12'd0 && vc==4'd1;
804
 
805
// The following bypasses loading the fifo when all the pixels from a scanline
806
// are buffered in the fifo and the pixel row doesn't change. Since the fifo
807
// pointers are reset at the beginning of a scanline, the fifo can be used like
808
// a cache.
809
wire blankEdge;
810
edge_det ed2(.rst(rst_i), .clk(m_clk_i), .ce(1'b1), .i(blank_i), .pe(blankEdge), .ne(), .ee() );
811
reg do_loads;
812
reg load_fifo = 1'b0;
813
always_ff @(posedge m_clk_i)
814
        //load_fifo <= fifo_cnt < 10'd1000 && vFetch && onoff && xonoff && !m_cyc_o && do_loads;
815
        load_fifo <= /*fifo_cnt < 8'd224 &&*/ vFetch && onoff && xonoff_i && (fetchCol < windowWidth) && memreq;
816
// The following table indicates the number of pixel that will fit into the
817
// video fifo.
818
reg [11:0] hCmp;
819
always_comb
820
case(color_depth)
821
BPP6: hCmp = 128 * $floor(MDW/6);    // must fit in 12 bits
822
BPP8:   hCmp = 128 * $floor(MDW/8);
823
BPP12: hCmp = 128 * $floor(MDW/12);
824
BPP16:  hCmp = 128 * $floor(MDW/16);
825
BPP18:  hCmp = 128 * $floor(MDW/18);
826
BPP21:  hCmp = 128 * $floor(MDW/21);
827
BPP24:  hCmp = 128 * $floor(MDW/24);
828
BPP27:  hCmp = 128 * $floor(MDW/27);
829
BPP32:  hCmp = 128 * $floor(MDW/32);
830
BPP33:  hCmp = 128 * $floor(MDW/33);
831
default:        hCmp = 128 * $floor(MDW/16);
832
endcase
833
/*
834
always @(posedge m_clk_i)
835
        // if windowWidth > hCmp we always load because the fifo isn't large enough to act as a cache.
836
        if (!(windowWidth < hCmp))
837
                do_loads <= 1'b1;
838
        // otherwise load the fifo only when the row changes to conserve memory bandwidth
839
        else if (vc==4'd1)//pixelRow != opixelRow)
840
                do_loads <= 1'b1;
841
        else if (blankEdge)
842
                do_loads <= 1'b0;
843
*/
844
always_comb m_stb_o = m_cyc_o;
845
always_comb m_sel_o = MDW==128 ? 16'hFFFF : MDW==64 ? 8'hFF : 4'hF;
846
 
847
reg [31:0] adr;
848
reg [3:0] state;
849
reg [127:0] icolor1;
850
parameter IDLE = 4'd0;
851
parameter LOADCOLOR = 4'd2;
852
parameter LOADSTRIP = 4'd3;
853
parameter STORESTRIP = 4'd4;
854
parameter ACKSTRIP = 4'd5;
855
parameter WAITLOAD = 4'd6;
856
parameter WAITRST = 4'd7;
857
parameter ICOLOR1 = 4'd8;
858
parameter ICOLOR2 = 4'd9;
859
parameter ICOLOR3 = 4'd10;
860
parameter ICOLOR4 = 4'd11;
861
parameter WAIT_NACK = 4'd12;
862
parameter LOAD_OOB = 4'd13;
863
 
864
function rastop;
865
input [3:0] op;
866
input a;
867
input b;
868
case(op)
869
OPBLACK: rastop = 1'b0;
870
OPCOPY:  rastop = b;
871
OPINV:   rastop = ~a;
872
OPAND:   rastop = a & b;
873
OPOR:    rastop = a | b;
874
OPXOR:   rastop = a ^ b;
875
OPANDN:  rastop = a & ~b;
876
OPNAND:  rastop = ~(a & b);
877
OPNOR:   rastop = ~(a | b);
878
OPXNOR:  rastop = ~(a ^ b);
879
OPORN:   rastop = a | ~b;
880
OPWHITE: rastop = 1'b1;
881
default:        rastop = 1'b0;
882
endcase
883
endfunction
884
 
885
always_ff @(posedge m_clk_i)
886
        if (fifo_wrst)
887
                adr <= grAddr;
888
  else begin
889
    if ((state==WAITLOAD && m_ack_i) || state==LOAD_OOB)
890
        case(MDW)
891
        32:             adr <= adr + 32'd4;
892
        64:             adr <= adr + 32'd8;
893
        default:        adr <= adr + 32'd16;
894
        endcase
895
  end
896
 
897
always_ff @(posedge m_clk_i)
898
        if (fifo_wrst)
899
                fetchCol <= 12'd0;
900
  else begin
901
    if ((state==WAITLOAD && m_ack_i) || state==LOAD_OOB)
902
      fetchCol <= fetchCol + shifts;
903
  end
904
 
905
// Check for legal (positive) coordinates
906
// Illegal coordinates result in a red display
907
wire [15:0] xcol = fetchCol;
908
reg legal_x, legal_y;
909
always_comb legal_x = ~&xcol[15:12] && xcol < bmpWidth;
910
always_comb legal_y = ~&pixelRow[15:12] && pixelRow < bmpHeight;
911
 
912
reg modd;
913
always_comb
914
        case(MDW)
915
        32:     modd <= m_adr_o[5:2]==4'hF;
916
        64:     modd <= m_adr_o[5:3]==3'h7;
917
        default:        modd <= m_adr_o[5:4]==2'h3;
918
        endcase
919
 
920
always @(posedge m_clk_i)
921
if (rst_i) begin
922
        wb_nack();
923
  rstcmd <= 1'b0;
924
  state <= IDLE;
925
end
926
else begin
927
        case(state)
928
  WAITRST:
929
    if (pcmd==2'b00 && ~m_ack_i) begin
930
      rstcmd <= 1'b0;
931
      state <= IDLE;
932
    end
933
    else
934
      rstcmd <= 1'b1;
935
  IDLE:
936
        if (load_fifo && !(legal_x && legal_y))
937
                        state <= LOAD_OOB;
938
    else if (load_fifo & ~m_ack_i) begin
939
      m_cyc_o <= `HIGH;
940
      m_we_o <= `LOW;
941
      m_adr_o <= adr;
942
      state <= WAITLOAD;
943
    end
944
    // The adr_o[5:3]==3'b111 causes the controller to wait until all eight
945
    // 64 bit strips from the memory controller have been processed. Otherwise
946
    // there would be cache thrashing in the memory controller and the memory
947
    // bandwidth available would be greatly reduced. However fetches are also
948
    // allowed when loads are not active or all strips for the current scan-
949
    // line have been fetched.
950
    else if (pcmd!=2'b00 && (modd || !(vFetch && onoff && xonoff_i && fetchCol < windowWidth))) begin
951
      m_cyc_o <= `HIGH;
952
      m_we_o <= `LOW;
953
      m_adr_o <= xyAddr;
954
      state <= LOADSTRIP;
955
    end
956
  LOADSTRIP:
957
    if (m_ack_i) begin
958
      wb_nack();
959
      mem_strip <= m_dat_i;
960
      icolor1 <= {96'b0,color} << mb;
961
      rstcmd <= 1'b1;
962
      if (pcmd==2'b01)
963
        state <= ICOLOR3;
964
      else if (pcmd==2'b10)
965
        state <= ICOLOR2;
966
      else begin
967
        state <= WAITRST;
968
      end
969
    end
970
  // Registered inline mem2color
971
  ICOLOR3:
972
    begin
973
      color_o <= mem_strip >> mb;
974
      state <= ICOLOR4;
975
    end
976
  ICOLOR4:
977
    begin
978
      for (n = 0; n < 32; n = n + 1)
979
        color_o[n] <= (n <= bpp) ? color_o[n] : 1'b0;
980
      state <= pcmd == 2'b0 ? (~m_ack_i ? IDLE : WAITRST) : WAITRST;
981
      if (pcmd==2'b00)
982
        rstcmd <= 1'b0;
983
    end
984
  // Registered inline color2mem
985
  ICOLOR2:
986
    begin
987
      for (n = 0; n < MDW; n = n + 1)
988
        m_dat_o[n] <= (n >= mb && n <= me)
989
                ? ((n <= ce) ?  rastop(raster_op, mem_strip[n], icolor1[n]) : icolor1[n])
990
                : mem_strip[n];
991
      state <= STORESTRIP;
992
    end
993
  STORESTRIP:
994
    if (~m_ack_i) begin
995
      m_cyc_o <= `HIGH;
996
      m_we_o <= `HIGH;
997
      state <= ACKSTRIP;
998
    end
999
  ACKSTRIP:
1000
    if (m_ack_i) begin
1001
      wb_nack();
1002
      state <= pcmd == 2'b0 ? IDLE : WAITRST;
1003
      if (pcmd==2'b00)
1004
        rstcmd <= 1'b0;
1005
    end
1006
  WAITLOAD:
1007
    if (m_ack_i) begin
1008
      wb_nack();
1009
      state <= IDLE;
1010
    end
1011
  LOAD_OOB:
1012
        state <= IDLE;
1013
  WAIT_NACK:
1014
        if (~m_ack_i)
1015
                state <= IDLE;
1016
  default:      state <= IDLE;
1017
  endcase
1018
end
1019
 
1020
task wb_nack;
1021
begin
1022
        m_cyc_o <= `LOW;
1023
        m_we_o <= `LOW;
1024
end
1025
endtask
1026
 
1027
always_ff @(posedge vclk)
1028
case(color_depth)
1029
BPP6:   rgbo4 <= {rgbo3[5:3],5'h00,21'd0,rgbo3[2:0]};   // feeds into palette
1030
BPP8:   rgbo4 <= {rgbo3[7:5],6'h00,18'h0,rgbo3[4:0]};           // feeds into palette
1031
BPP12:  rgbo4 <= {rgbo3[11:9],5'd0,rgbo3[8:6],5'd0,rgbo3[5:3],5'd0,rgbo3[2:0],5'd0};
1032
BPP16:  rgbo4 <= {rgbo3[15:13],5'b0,rgbo3[11:8],4'b0,rgbo3[7:4],4'b0,rgbo3[3:0],4'b0};
1033
BPP18:  rgbo4 <= {rgbo3[17:15],5'b0,rgbo3[14:10],3'b0,rgbo3[9:5],3'b0,rgbo3[4:0],3'b0};
1034
BPP21:  rgbo4 <= {rgbo3[20:18],5'b0,rgbo3[17:12],2'b0,rgbo3[11:6],2'b0,rgbo3[5:0],2'b0};
1035
BPP24:  rgbo4 <= {rgbo3[23:21],5'b0,rgbo3[20:14],1'b0,rgbo3[13:7],1'b0,rgbo3[6:0],1'b0};
1036
BPP27:  rgbo4 <= {rgbo3[26:24],5'b0,rgbo3[23:16],rgbo3[15:8],rgbo3[7:0]};
1037
BPP32:  rgbo4 <= {rgbo3[31:29],2'b0,rgbo3[26:18],rgbo3[17:9],rgbo3[8:0]};
1038
default:        rgbo4 <= {rgbo3[15:13],5'b0,rgbo3[11:8],4'b0,rgbo3[7:4],4'b0,rgbo3[3:0],4'b0};
1039
endcase
1040
 
1041
reg rd_fifo,rd_fifo1,rd_fifo2;
1042
reg de;
1043
always_ff @(posedge vclk)
1044
        if (rd_fifo1)
1045
                de <= ~blank_i;
1046
 
1047
always_ff @(posedge vclk)
1048
        if (onoff && xonoff_i && !blank_i) begin
1049
                if (color_depth[2:1]==2'b00) begin
1050
                        if (!greyscale)
1051
                                zrgb_o <= pal_o[31:0];
1052
                        else
1053
                                zrgb_o <= {pal_o[31:24],{3{pal_o[7:0]}}};
1054
                end
1055
                else
1056
                        zrgb_o <= rgbo4;
1057
        end
1058
        else
1059
                zrgb_o <= 32'h00000000;
1060
 
1061
// Before the hrefdelay expires, pixelCol will be negative, which is greater
1062
// than windowWidth as the value is unsigned. That means that fifo reading is
1063
// active only during the display area 0 to windowWidth.
1064
reg shift1;
1065
always_comb shift1 = hc==hres;
1066
reg [5:0] shift_cnt;
1067
always_ff @(posedge vclk)
1068
if (pe_hsync)
1069
        shift_cnt <= 5'd1;
1070
else begin
1071
        if (shift1) begin
1072
                if (pixelCol==16'hFFFF)
1073
                        shift_cnt <= shifts;
1074
                else if (!pixelCol[15]) begin
1075
                        shift_cnt <= shift_cnt + 5'd1;
1076
                        if (shift_cnt==shifts)
1077
                                shift_cnt <= 5'd1;
1078
                end
1079
                else
1080
                        shift_cnt <= 5'd1;
1081
        end
1082
end
1083
 
1084
reg next_strip;
1085
always_comb next_strip = (shift_cnt==shifts) && (hc==hres);
1086
 
1087
wire vrd;
1088
reg shift,shift2;
1089
always_ff @(posedge vclk) shift2 <= shift1;
1090
always_ff @(posedge vclk) shift <= shift2;
1091
always_ff @(posedge vclk) rd_fifo2 <= next_strip;
1092
always_ff @(posedge vclk) rd_fifo <= rd_fifo2;
1093
always_ff @(posedge vclk)
1094
        if (rd_fifo)
1095
                rgbo3 <= lef ? rgbo1o : rgbo1e;
1096
        else if (shift) begin
1097
                case(color_depth)
1098
                BPP6:   rgbo3 <= {4'h0,rgbo3[MDW-1:6]};
1099
                BPP8:   rgbo3 <= {8'h0,rgbo3[MDW-1:8]};
1100
                BPP12: rgbo3 <= {12'h0,rgbo3[MDW-1:12]};
1101
                BPP16:  rgbo3 <= {16'h0,rgbo3[MDW-1:16]};
1102
                BPP18:  rgbo3 <= {18'h0,rgbo3[MDW-1:18]};
1103
                BPP21:  rgbo3 <= {21'h0,rgbo3[MDW-1:21]};
1104
                BPP24:  rgbo3 <= {24'h0,rgbo3[MDW-1:24]};
1105
                BPP27:  rgbo3 <= {27'h0,rgbo3[MDW-1:27]};
1106
                BPP32:  rgbo3 <= {32'h0,rgbo3[MDW-1:32]};
1107
                BPP32:  rgbo3 <= {33'h0,rgbo3[MDW-1:33]};
1108
                default: rgbo3 <= {16'h0,rgbo3[MDW-1:16]};
1109
                endcase
1110
        end
1111
 
1112
 
1113
/* Debugging
1114
wire [127:0] dat;
1115
assign dat[11:0] = pixelRow[0] ? 12'hEA4 : 12'h000;
1116
assign dat[23:12] = pixelRow[1] ? 12'hEA4 : 12'h000;
1117
assign dat[35:24] = pixelRow[2] ? 12'hEA4 : 12'h000;
1118
assign dat[47:36] = pixelRow[3] ? 12'hEA4 : 12'h000;
1119
assign dat[59:48] = pixelRow[4] ? 12'hEA4 : 12'h000;
1120
assign dat[71:60] = pixelRow[5] ? 12'hEA4 : 12'h000;
1121
assign dat[83:72] = pixelRow[6] ? 12'hEA4 : 12'h000;
1122
assign dat[95:84] = pixelRow[7] ? 12'hEA4 : 12'h000;
1123
assign dat[107:96] = pixelRow[8] ? 12'hEA4 : 12'h000;
1124
assign dat[119:108] = pixelRow[9] ? 12'hEA4 : 12'h000;
1125
*/
1126
 
1127
reg [MDW-1:0] oob_dat;
1128
always_comb
1129
case(color_depth)
1130
BPP6:   oob_dat <= {MDW/6{oob_color[5:0]}};
1131
BPP8:   oob_dat <= {MDW/8{oob_color[7:0]}};
1132
BPP12:  oob_dat <= {MDW/12{oob_color[11:0]}};
1133
BPP16:  oob_dat <= {MDW/16{oob_color[15:0]}};
1134
BPP18:  oob_dat <= {MDW/18{oob_color[17:0]}};
1135
BPP21:  oob_dat <= {MDW/21{oob_color[20:0]}};
1136
BPP24:  oob_dat <= {MDW/24{oob_color[23:0]}};
1137
BPP27:  oob_dat <= {MDW/27{oob_color[26:0]}};
1138
BPP32:  oob_dat <= {MDW/32{oob_color[31:0]}};
1139
BPP33:  oob_dat <= {MDW/33{oob_color[32:0]}};
1140
default:        oob_dat <= {MDW/16{oob_color[15:0]}};
1141
endcase
1142
 
1143
rfVideoFifo #(MDW) uf1
1144
(
1145
        .wrst(fifo_wrst),
1146
        .wclk(m_clk_i),
1147
        .wr(((m_ack_i && state==WAITLOAD) || state==LOAD_OOB) && lef),
1148
        .di((state==LOAD_OOB) ? oob_dat : m_dat_i),
1149
        .rrst(fifo_rrst),
1150
        .rclk(vclk),
1151
        .rd(rd_fifo & lof),
1152
        .dout(rgbo1e),
1153
        .cnt()
1154
);
1155
 
1156
rfVideoFifo #(MDW) uf2
1157
(
1158
        .wrst(fifo_wrst),
1159
        .wclk(m_clk_i),
1160
        .wr(((m_ack_i && state==WAITLOAD) || state==LOAD_OOB) && lof),
1161
        .di((state==LOAD_OOB) ? oob_dat : m_dat_i),
1162
        .rrst(fifo_rrst),
1163
        .rclk(vclk),
1164
        .rd(rd_fifo & lef),
1165
        .dout(rgbo1o),
1166
        .cnt()
1167
);
1168
 
1169
endmodule

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