| 1 |
13 |
robfinch |
; ============================================================================
|
| 2 |
|
|
; __
|
| 3 |
|
|
; \\__/ o\ (C) 2013-2022 Robert Finch, Waterloo
|
| 4 |
|
|
; \ __ / All rights reserved.
|
| 5 |
|
|
; \/_// robfinch@opencores.org
|
| 6 |
|
|
; ||
|
| 7 |
|
|
;
|
| 8 |
|
|
;
|
| 9 |
|
|
; BSD 3-Clause License
|
| 10 |
|
|
; Redistribution and use in source and binary forms, with or without
|
| 11 |
|
|
; modification, are permitted provided that the following conditions are met:
|
| 12 |
|
|
;
|
| 13 |
|
|
; 1. Redistributions of source code must retain the above copyright notice, this
|
| 14 |
|
|
; list of conditions and the following disclaimer.
|
| 15 |
|
|
;
|
| 16 |
|
|
; 2. Redistributions in binary form must reproduce the above copyright notice,
|
| 17 |
|
|
; this list of conditions and the following disclaimer in the documentation
|
| 18 |
|
|
; and/or other materials provided with the distribution.
|
| 19 |
|
|
;
|
| 20 |
|
|
; 3. Neither the name of the copyright holder nor the names of its
|
| 21 |
|
|
; contributors may be used to endorse or promote products derived from
|
| 22 |
|
|
; this software without specific prior written permission.
|
| 23 |
|
|
;
|
| 24 |
|
|
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
| 25 |
|
|
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
| 26 |
|
|
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
| 27 |
|
|
; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
| 28 |
|
|
; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
| 29 |
|
|
; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
| 30 |
|
|
; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
| 31 |
|
|
; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
| 32 |
|
|
; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
| 33 |
|
|
; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
| 34 |
|
|
;
|
| 35 |
|
|
; ============================================================================
|
| 36 |
|
|
;
|
| 37 |
|
|
;===============================================================================
|
| 38 |
|
|
; Generic I2C routines
|
| 39 |
|
|
;
|
| 40 |
|
|
; It is assumed there may be more than one I2C controller in the system, so
|
| 41 |
|
|
; the address of the controller is passed in the X register.
|
| 42 |
|
|
;===============================================================================
|
| 43 |
|
|
|
| 44 |
|
|
I2C_PREL EQU $0
|
| 45 |
|
|
I2C_PREH EQU $1
|
| 46 |
|
|
I2C_CTRL EQU $2
|
| 47 |
|
|
I2C_RXR EQU $3
|
| 48 |
|
|
I2C_TXR EQU $3
|
| 49 |
|
|
I2C_CMD EQU $4
|
| 50 |
|
|
I2C_STAT EQU $4
|
| 51 |
|
|
|
| 52 |
|
|
; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
| 53 |
|
|
; i2c initialization, sets the clock prescaler
|
| 54 |
|
|
;
|
| 55 |
|
|
; Parameters:
|
| 56 |
|
|
; x = I2C controller address
|
| 57 |
|
|
; Returns: none
|
| 58 |
|
|
; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
| 59 |
|
|
|
| 60 |
|
|
_i2c_init:
|
| 61 |
|
|
pshs b
|
| 62 |
|
|
ldb #4 ; setup prescale for 400kHz clock
|
| 63 |
|
|
stb I2C_PREL,x
|
| 64 |
|
|
clr I2C_PREH,x
|
| 65 |
|
|
puls b,pc
|
| 66 |
|
|
|
| 67 |
|
|
; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
| 68 |
|
|
; Wait for I2C transfer to complete
|
| 69 |
|
|
;
|
| 70 |
|
|
; Parameters
|
| 71 |
|
|
; x - I2C controller base address
|
| 72 |
|
|
; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
| 73 |
|
|
|
| 74 |
|
|
i2c_wait_tip:
|
| 75 |
|
|
pshs b
|
| 76 |
|
|
i2cw1:
|
| 77 |
|
|
ldb I2C_STAT,x ; would use lvb, but lb is okay since its the I/O area
|
| 78 |
|
|
bitb #1 ; wait for tip to clear
|
| 79 |
|
|
bne i2cw1
|
| 80 |
|
|
puls b,pc
|
| 81 |
|
|
|
| 82 |
|
|
; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
| 83 |
|
|
; Write command to i2c
|
| 84 |
|
|
;
|
| 85 |
|
|
; Parameters
|
| 86 |
|
|
; accb - data to transmit
|
| 87 |
|
|
; acca - command value
|
| 88 |
|
|
; x - I2C controller base address
|
| 89 |
|
|
; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
| 90 |
|
|
|
| 91 |
|
|
i2c_wr_cmd:
|
| 92 |
|
|
stb I2C_TXR,x
|
| 93 |
|
|
sta I2C_CMD,x
|
| 94 |
|
|
bsr i2c_wait_tip
|
| 95 |
|
|
ldb I2C_STAT,x
|
| 96 |
|
|
rts
|
| 97 |
|
|
|
| 98 |
|
|
; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
| 99 |
|
|
; Parameters
|
| 100 |
|
|
; x - I2C controller base address
|
| 101 |
|
|
; accb - data to send
|
| 102 |
|
|
; Returns: none
|
| 103 |
|
|
; Stack space: 2 words
|
| 104 |
|
|
; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
| 105 |
|
|
|
| 106 |
|
|
_i2c_xmit1:
|
| 107 |
|
|
pshs d ; save data value
|
| 108 |
|
|
pshs d ; and save it again
|
| 109 |
|
|
ldb #1
|
| 110 |
|
|
stb I2C_CTRL,x ; enable the core
|
| 111 |
|
|
ldb #$76 ; set slave address = %0111011
|
| 112 |
|
|
lda #$90 ; set STA, WR
|
| 113 |
|
|
bsr i2c_wr_cmd
|
| 114 |
|
|
bsr i2c_wait_rx_nack
|
| 115 |
|
|
puls d ; get back data value
|
| 116 |
|
|
lda #$50 ; set STO, WR
|
| 117 |
|
|
bsr i2c_wr_cmd
|
| 118 |
|
|
bsr i2c_wait_rx_nack
|
| 119 |
|
|
puls d,pc
|
| 120 |
|
|
|
| 121 |
|
|
; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
| 122 |
|
|
; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
| 123 |
|
|
|
| 124 |
|
|
i2c_wait_rx_nack:
|
| 125 |
|
|
pshs b ; save off accb
|
| 126 |
|
|
i2cwr1:
|
| 127 |
|
|
ldb I2C_STAT,x ; wait for RXack = 0
|
| 128 |
|
|
bitb #$80 ; test for nack
|
| 129 |
|
|
bne i2cwr1
|
| 130 |
|
|
puls b,pc
|
| 131 |
|
|
|
